Context Navigation

← Previous Revision
Latest Revision
Next Revision →
Blame
Revision Log

samd21j17a.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago
ライブラリとOS及びベーシックなサンプルの追加．
File size: 30.0 KB

Line
1	/**
2	* \file
3	*
4	* \brief Header file for SAMD21J17A
5	*
6	* Copyright (c) 2014 Atmel Corporation. All rights reserved.
7	*
8	* \asf_license_start
9	*
10	* \page License
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions are met:
14	*
15	* 1. Redistributions of source code must retain the above copyright notice,
16	* this list of conditions and the following disclaimer.
17	*
18	* 2. Redistributions in binary form must reproduce the above copyright notice,
19	* this list of conditions and the following disclaimer in the documentation
20	* and/or other materials provided with the distribution.
21	*
22	* 3. The name of Atmel may not be used to endorse or promote products derived
23	* from this software without specific prior written permission.
24	*
25	* 4. This software may only be redistributed and used in connection with an
26	* Atmel microcontroller product.
27	*
28	* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31	* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36	* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37	* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38	* POSSIBILITY OF SUCH DAMAGE.
39	*
40	* \asf_license_stop
41	*
42	*/
43
44	#ifndef _SAMD21J17A_
45	#define _SAMD21J17A_
46
47	/**
48	* \ingroup SAMD21_definitions
49	* \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
50	* This file defines all structures and symbols for SAMD21J17A:
51	* - registers and bitfields
52	* - peripheral base address
53	* - peripheral ID
54	* - PIO definitions
55	*/
56	/@{/
57
58	#ifdef __cplusplus
59	extern "C" {
60	#endif
61
62	#if !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__))
63	#include <stdint.h>
64	#ifndef __cplusplus
65	typedef volatile const uint32_t RoReg; /*< Read only 32-bit register (volatile const unsigned int) /
66	typedef volatile const uint16_t RoReg16; /*< Read only 16-bit register (volatile const unsigned int) /
67	typedef volatile const uint8_t RoReg8; /*< Read only 8-bit register (volatile const unsigned int) /
68	#else
69	typedef volatile uint32_t RoReg; /*< Read only 32-bit register (volatile const unsigned int) /
70	typedef volatile uint16_t RoReg16; /*< Read only 16-bit register (volatile const unsigned int) /
71	typedef volatile uint8_t RoReg8; /*< Read only 8-bit register (volatile const unsigned int) /
72	#endif
73	typedef volatile uint32_t WoReg; /*< Write only 32-bit register (volatile unsigned int) /
74	typedef volatile uint16_t WoReg16; /*< Write only 16-bit register (volatile unsigned int) /
75	typedef volatile uint32_t WoReg8; /*< Write only 8-bit register (volatile unsigned int) /
76	typedef volatile uint32_t RwReg; /*< Read-Write 32-bit register (volatile unsigned int) /
77	typedef volatile uint16_t RwReg16; /*< Read-Write 16-bit register (volatile unsigned int) /
78	typedef volatile uint8_t RwReg8; /*< Read-Write 8-bit register (volatile unsigned int) /
79	#define CAST(type, value) ((type *)(value))
80	#define REG_ACCESS(type, address) ((type)(address)) /*< C code: Register value /
81	#else
82	#define CAST(type, value) (value)
83	#define REG_ACCESS(type, address) (address) /*< Assembly code: Register address /
84	#endif
85
86	/* ************************************************************************** */
87	/** CMSIS DEFINITIONS FOR SAMD21J17A */
88	/* ************************************************************************** */
89	/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
90	/@{/
91
92	/** Interrupt Number Definition */
93	typedef enum IRQn
94	{
95	/**** Cortex-M0+ Processor Exceptions Numbers *****************************/
96	NonMaskableInt_IRQn = -14, /*< 2 Non Maskable Interrupt /
97	HardFault_IRQn = -13, /*< 3 Cortex-M0+ Hard Fault Interrupt /
98	SVCall_IRQn = -5, /*< 11 Cortex-M0+ SV Call Interrupt /
99	PendSV_IRQn = -2, /*< 14 Cortex-M0+ Pend SV Interrupt /
100	SysTick_IRQn = -1, /*< 15 Cortex-M0+ System Tick Interrupt /
101	/**** SAMD21J17A-specific Interrupt Numbers *********************/
102	PM_IRQn = 0, /*< 0 SAMD21J17A Power Manager (PM) /
103	SYSCTRL_IRQn = 1, /*< 1 SAMD21J17A System Control (SYSCTRL) /
104	WDT_IRQn = 2, /*< 2 SAMD21J17A Watchdog Timer (WDT) /
105	RTC_IRQn = 3, /*< 3 SAMD21J17A Real-Time Counter (RTC) /
106	EIC_IRQn = 4, /*< 4 SAMD21J17A External Interrupt Controller (EIC) /
107	NVMCTRL_IRQn = 5, /*< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) /
108	DMAC_IRQn = 6, /*< 6 SAMD21J17A Direct Memory Access Controller (DMAC) /
109	USB_IRQn = 7, /*< 7 SAMD21J17A Universal Serial Bus (USB) /
110	EVSYS_IRQn = 8, /*< 8 SAMD21J17A Event System Interface (EVSYS) /
111	SERCOM0_IRQn = 9, /*< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) /
112	SERCOM1_IRQn = 10, /*< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) /
113	SERCOM2_IRQn = 11, /*< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) /
114	SERCOM3_IRQn = 12, /*< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) /
115	SERCOM4_IRQn = 13, /*< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) /
116	SERCOM5_IRQn = 14, /*< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) /
117	TCC0_IRQn = 15, /*< 15 SAMD21J17A Timer Counter Control 0 (TCC0) /
118	TCC1_IRQn = 16, /*< 16 SAMD21J17A Timer Counter Control 1 (TCC1) /
119	TCC2_IRQn = 17, /*< 17 SAMD21J17A Timer Counter Control 2 (TCC2) /
120	TC3_IRQn = 18, /*< 18 SAMD21J17A Basic Timer Counter 3 (TC3) /
121	TC4_IRQn = 19, /*< 19 SAMD21J17A Basic Timer Counter 4 (TC4) /
122	TC5_IRQn = 20, /*< 20 SAMD21J17A Basic Timer Counter 5 (TC5) /
123	TC6_IRQn = 21, /*< 21 SAMD21J17A Basic Timer Counter 6 (TC6) /
124	TC7_IRQn = 22, /*< 22 SAMD21J17A Basic Timer Counter 7 (TC7) /
125	ADC_IRQn = 23, /*< 23 SAMD21J17A Analog Digital Converter (ADC) /
126	AC_IRQn = 24, /*< 24 SAMD21J17A Analog Comparators (AC) /
127	DAC_IRQn = 25, /*< 25 SAMD21J17A Digital Analog Converter (DAC) /
128	PTC_IRQn = 26, /*< 26 SAMD21J17A Peripheral Touch Controller (PTC) /
129	I2S_IRQn = 27, /*< 27 SAMD21J17A Inter-IC Sound Interface (I2S) /
130
131	PERIPH_COUNT_IRQn = 28 /*< Number of peripheral IDs /
132	} IRQn_Type;
133
134	typedef struct _DeviceVectors
135	{
136	/* Stack pointer */
137	void* pvStack;
138
139	/* Cortex-M handlers */
140	void* pfnReset_Handler;
141	void* pfnNMI_Handler;
142	void* pfnHardFault_Handler;
143	void* pfnReservedM12;
144	void* pfnReservedM11;
145	void* pfnReservedM10;
146	void* pfnReservedM9;
147	void* pfnReservedM8;
148	void* pfnReservedM7;
149	void* pfnReservedM6;
150	void* pfnSVC_Handler;
151	void* pfnReservedM4;
152	void* pfnReservedM3;
153	void* pfnPendSV_Handler;
154	void* pfnSysTick_Handler;
155
156	/* Peripheral handlers */
157	void* pfnPM_Handler; /* 0 Power Manager */
158	void* pfnSYSCTRL_Handler; /* 1 System Control */
159	void* pfnWDT_Handler; /* 2 Watchdog Timer */
160	void* pfnRTC_Handler; /* 3 Real-Time Counter */
161	void* pfnEIC_Handler; /* 4 External Interrupt Controller */
162	void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
163	void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
164	void* pfnUSB_Handler; /* 7 Universal Serial Bus */
165	void* pfnEVSYS_Handler; /* 8 Event System Interface */
166	void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
167	void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
168	void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
169	void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
170	void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
171	void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
172	void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
173	void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
174	void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
175	void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
176	void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
177	void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
178	void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
179	void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
180	void* pfnADC_Handler; /* 23 Analog Digital Converter */
181	void* pfnAC_Handler; /* 24 Analog Comparators */
182	void* pfnDAC_Handler; /* 25 Digital Analog Converter */
183	void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
184	void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
185	} DeviceVectors;
186
187	/* Cortex-M0+ processor handlers */
188	void Reset_Handler ( void );
189	void NMI_Handler ( void );
190	void HardFault_Handler ( void );
191	void SVC_Handler ( void );
192	void PendSV_Handler ( void );
193	void SysTick_Handler ( void );
194
195	/* Peripherals handlers */
196	void PM_Handler ( void );
197	void SYSCTRL_Handler ( void );
198	void WDT_Handler ( void );
199	void RTC_Handler ( void );
200	void EIC_Handler ( void );
201	void NVMCTRL_Handler ( void );
202	void DMAC_Handler ( void );
203	void USB_Handler ( void );
204	void EVSYS_Handler ( void );
205	void SERCOM0_Handler ( void );
206	void SERCOM1_Handler ( void );
207	void SERCOM2_Handler ( void );
208	void SERCOM3_Handler ( void );
209	void SERCOM4_Handler ( void );
210	void SERCOM5_Handler ( void );
211	void TCC0_Handler ( void );
212	void TCC1_Handler ( void );
213	void TCC2_Handler ( void );
214	void TC3_Handler ( void );
215	void TC4_Handler ( void );
216	void TC5_Handler ( void );
217	void TC6_Handler ( void );
218	void TC7_Handler ( void );
219	void ADC_Handler ( void );
220	void AC_Handler ( void );
221	void DAC_Handler ( void );
222	void PTC_Handler ( void );
223	void I2S_Handler ( void );
224
225	/*
226	* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
227	*/
228
229	#define LITTLE_ENDIAN 1
230	#define __CM0PLUS_REV 1 /!< Core revision r0p1 /
231	#define __MPU_PRESENT 0 /!< MPU present or not /
232	#define __NVIC_PRIO_BITS 2 /!< Number of bits used for Priority Levels /
233	#define __VTOR_PRESENT 1 /!< VTOR present or not /
234	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
235
236	/**
237	* \brief CMSIS includes
238	*/
239
240	#include <core_cm0plus.h>
241	#if !defined DONT_USE_CMSIS_INIT
242	#include "system_samd21.h"
243	#endif /* DONT_USE_CMSIS_INIT */
244
245	/@}/
246
247	/* ************************************************************************** */
248	/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
249	/* ************************************************************************** */
250	/** \defgroup SAMD21J17A_api Peripheral Software API */
251	/@{/
252
253	#include "component/ac.h"
254	#include "component/adc.h"
255	#include "component/dac.h"
256	#include "component/dmac.h"
257	#include "component/dsu.h"
258	#include "component/eic.h"
259	#include "component/evsys.h"
260	#include "component/gclk.h"
261	#include "component/i2s.h"
262	#include "component/mtb.h"
263	#include "component/nvmctrl.h"
264	#include "component/pac.h"
265	#include "component/pm.h"
266	#include "component/port.h"
267	#include "component/rtc.h"
268	#include "component/sercom.h"
269	#include "component/sysctrl.h"
270	#include "component/tc.h"
271	#include "component/tcc.h"
272	#include "component/usb.h"
273	#include "component/wdt.h"
274	/@}/
275
276	/* ************************************************************************** */
277	/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
278	/* ************************************************************************** */
279	/** \defgroup SAMD21J17A_reg Registers Access Definitions */
280	/@{/
281
282	#include "instance/ac.h"
283	#include "instance/adc.h"
284	#include "instance/dac.h"
285	#include "instance/dmac.h"
286	#include "instance/dsu.h"
287	#include "instance/eic.h"
288	#include "instance/evsys.h"
289	#include "instance/gclk.h"
290	#include "instance/i2s.h"
291	#include "instance/mtb.h"
292	#include "instance/nvmctrl.h"
293	#include "instance/pac0.h"
294	#include "instance/pac1.h"
295	#include "instance/pac2.h"
296	#include "instance/pm.h"
297	#include "instance/port.h"
298	#include "instance/rtc.h"
299	#include "instance/sercom0.h"
300	#include "instance/sercom1.h"
301	#include "instance/sercom2.h"
302	#include "instance/sercom3.h"
303	#include "instance/sercom4.h"
304	#include "instance/sercom5.h"
305	#include "instance/sysctrl.h"
306	#include "instance/tc3.h"
307	#include "instance/tc4.h"
308	#include "instance/tc5.h"
309	#include "instance/tc6.h"
310	#include "instance/tc7.h"
311	#include "instance/tcc0.h"
312	#include "instance/tcc1.h"
313	#include "instance/tcc2.h"
314	#include "instance/usb.h"
315	#include "instance/wdt.h"
316	/@}/
317
318	/* ************************************************************************** */
319	/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
320	/* ************************************************************************** */
321	/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
322	/@{/
323
324	// Peripheral instances on HPB0 bridge
325	#define ID_PAC0 0 /*< \brief Peripheral Access Controller PAC (PAC0) /
326	#define ID_PM 1 /*< \brief Power Manager (PM) /
327	#define ID_SYSCTRL 2 /*< \brief System Control (SYSCTRL) /
328	#define ID_GCLK 3 /*< \brief Generic Clock Generator (GCLK) /
329	#define ID_WDT 4 /*< \brief Watchdog Timer (WDT) /
330	#define ID_RTC 5 /*< \brief Real-Time Counter (RTC) /
331	#define ID_EIC 6 /*< \brief External Interrupt Controller (EIC) /
332
333	// Peripheral instances on HPB1 bridge
334	#define ID_PAC1 32 /*< \brief Peripheral Access Controller PAC (PAC1) /
335	#define ID_DSU 33 /*< \brief Device Service Unit (DSU) /
336	#define ID_NVMCTRL 34 /*< \brief Non-Volatile Memory Controller (NVMCTRL) /
337	#define ID_PORT 35 /*< \brief Port Module (PORT) /
338	#define ID_DMAC 36 /*< \brief Direct Memory Access Controller (DMAC) /
339	#define ID_USB 37 /*< \brief Universal Serial Bus (USB) /
340	#define ID_MTB 38 /*< \brief Cortex-M0+ Micro-Trace Buffer (MTB) /
341
342	// Peripheral instances on HPB2 bridge
343	#define ID_PAC2 64 /*< \brief Peripheral Access Controller PAC (PAC2) /
344	#define ID_EVSYS 65 /*< \brief Event System Interface (EVSYS) /
345	#define ID_SERCOM0 66 /*< \brief Serial Communication Interface SERCOM (SERCOM0) /
346	#define ID_SERCOM1 67 /*< \brief Serial Communication Interface SERCOM (SERCOM1) /
347	#define ID_SERCOM2 68 /*< \brief Serial Communication Interface SERCOM (SERCOM2) /
348	#define ID_SERCOM3 69 /*< \brief Serial Communication Interface SERCOM (SERCOM3) /
349	#define ID_SERCOM4 70 /*< \brief Serial Communication Interface SERCOM (SERCOM4) /
350	#define ID_SERCOM5 71 /*< \brief Serial Communication Interface SERCOM (SERCOM5) /
351	#define ID_TCC0 72 /*< \brief Timer Counter Control TCC (TCC0) /
352	#define ID_TCC1 73 /*< \brief Timer Counter Control TCC (TCC1) /
353	#define ID_TCC2 74 /*< \brief Timer Counter Control TCC (TCC2) /
354	#define ID_TC3 75 /*< \brief Basic Timer Counter TC (TC3) /
355	#define ID_TC4 76 /*< \brief Basic Timer Counter TC (TC4) /
356	#define ID_TC5 77 /*< \brief Basic Timer Counter TC (TC5) /
357	#define ID_TC6 78 /*< \brief Basic Timer Counter TC (TC6) /
358	#define ID_TC7 79 /*< \brief Basic Timer Counter TC (TC7) /
359	#define ID_ADC 80 /*< \brief Analog Digital Converter (ADC) /
360	#define ID_AC 81 /*< \brief Analog Comparators (AC) /
361	#define ID_DAC 82 /*< \brief Digital Analog Converter (DAC) /
362	#define ID_PTC 83 /*< \brief Peripheral Touch Controller (PTC) /
363	#define ID_I2S 84 /*< \brief Inter-IC Sound Interface (I2S) /
364
365	#define ID_PERIPH_COUNT 85 /*< \brief Number of peripheral IDs /
366	/@}/
367
368	/* ************************************************************************** */
369	/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
370	/* ************************************************************************** */
371	/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
372	/@{/
373
374	#if defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__)
375	#define AC (0x42004400U) /*< \brief (AC) APB Base Address /
376	#define ADC (0x42004000U) /*< \brief (ADC) APB Base Address /
377	#define DAC (0x42004800U) /*< \brief (DAC) APB Base Address /
378	#define DMAC (0x41004800U) /*< \brief (DMAC) APB Base Address /
379	#define DSU (0x41002000U) /*< \brief (DSU) APB Base Address /
380	#define EIC (0x40001800U) /*< \brief (EIC) APB Base Address /
381	#define EVSYS (0x42000400U) /*< \brief (EVSYS) APB Base Address /
382	#define GCLK (0x40000C00U) /*< \brief (GCLK) APB Base Address /
383	#define I2S (0x42005000U) /*< \brief (I2S) APB Base Address /
384	#define MTB (0x41006000U) /*< \brief (MTB) APB Base Address /
385	#define NVMCTRL (0x41004000U) /*< \brief (NVMCTRL) APB Base Address /
386	#define NVMCTRL_CAL (0x00800000U) /*< \brief (NVMCTRL) CAL Base Address /
387	#define NVMCTRL_LOCKBIT (0x00802000U) /*< \brief (NVMCTRL) LOCKBIT Base Address /
388	#define NVMCTRL_OTP1 (0x00806000U) /*< \brief (NVMCTRL) OTP1 Base Address /
389	#define NVMCTRL_OTP2 (0x00806008U) /*< \brief (NVMCTRL) OTP2 Base Address /
390	#define NVMCTRL_OTP4 (0x00806020U) /*< \brief (NVMCTRL) OTP4 Base Address /
391	#define NVMCTRL_TEMP_LOG (0x00806030U) /*< \brief (NVMCTRL) TEMP_LOG Base Address /
392	#define NVMCTRL_USER (0x00804000U) /*< \brief (NVMCTRL) USER Base Address /
393	#define PAC0 (0x40000000U) /*< \brief (PAC0) APB Base Address /
394	#define PAC1 (0x41000000U) /*< \brief (PAC1) APB Base Address /
395	#define PAC2 (0x42000000U) /*< \brief (PAC2) APB Base Address /
396	#define PM (0x40000400U) /*< \brief (PM) APB Base Address /
397	#define PORT (0x41004400U) /*< \brief (PORT) APB Base Address /
398	#define PORT_IOBUS (0x60000000U) /*< \brief (PORT) IOBUS Base Address /
399	#define RTC (0x40001400U) /*< \brief (RTC) APB Base Address /
400	#define SERCOM0 (0x42000800U) /*< \brief (SERCOM0) APB Base Address /
401	#define SERCOM1 (0x42000C00U) /*< \brief (SERCOM1) APB Base Address /
402	#define SERCOM2 (0x42001000U) /*< \brief (SERCOM2) APB Base Address /
403	#define SERCOM3 (0x42001400U) /*< \brief (SERCOM3) APB Base Address /
404	#define SERCOM4 (0x42001800U) /*< \brief (SERCOM4) APB Base Address /
405	#define SERCOM5 (0x42001C00U) /*< \brief (SERCOM5) APB Base Address /
406	#define SYSCTRL (0x40000800U) /*< \brief (SYSCTRL) APB Base Address /
407	#define TC3 (0x42002C00U) /*< \brief (TC3) APB Base Address /
408	#define TC4 (0x42003000U) /*< \brief (TC4) APB Base Address /
409	#define TC5 (0x42003400U) /*< \brief (TC5) APB Base Address /
410	#define TC6 (0x42003800U) /*< \brief (TC6) APB Base Address /
411	#define TC7 (0x42003C00U) /*< \brief (TC7) APB Base Address /
412	#define TCC0 (0x42002000U) /*< \brief (TCC0) APB Base Address /
413	#define TCC1 (0x42002400U) /*< \brief (TCC1) APB Base Address /
414	#define TCC2 (0x42002800U) /*< \brief (TCC2) APB Base Address /
415	#define USB (0x41005000U) /*< \brief (USB) APB Base Address /
416	#define WDT (0x40001000U) /*< \brief (WDT) APB Base Address /
417	#else
418	#define AC ((Ac )0x42004400U) /< \brief (AC) APB Base Address /
419	#define AC_INST_NUM 1 /*< \brief (AC) Number of instances /
420	#define AC_INSTS { AC } /*< \brief (AC) Instances List /
421
422	#define ADC ((Adc )0x42004000U) /< \brief (ADC) APB Base Address /
423	#define ADC_INST_NUM 1 /*< \brief (ADC) Number of instances /
424	#define ADC_INSTS { ADC } /*< \brief (ADC) Instances List /
425
426	#define DAC ((Dac )0x42004800U) /< \brief (DAC) APB Base Address /
427	#define DAC_INST_NUM 1 /*< \brief (DAC) Number of instances /
428	#define DAC_INSTS { DAC } /*< \brief (DAC) Instances List /
429
430	#define DMAC ((Dmac )0x41004800U) /< \brief (DMAC) APB Base Address /
431	#define DMAC_INST_NUM 1 /*< \brief (DMAC) Number of instances /
432	#define DMAC_INSTS { DMAC } /*< \brief (DMAC) Instances List /
433
434	#define DSU ((Dsu )0x41002000U) /< \brief (DSU) APB Base Address /
435	#define DSU_INST_NUM 1 /*< \brief (DSU) Number of instances /
436	#define DSU_INSTS { DSU } /*< \brief (DSU) Instances List /
437
438	#define EIC ((Eic )0x40001800U) /< \brief (EIC) APB Base Address /
439	#define EIC_INST_NUM 1 /*< \brief (EIC) Number of instances /
440	#define EIC_INSTS { EIC } /*< \brief (EIC) Instances List /
441
442	#define EVSYS ((Evsys )0x42000400U) /< \brief (EVSYS) APB Base Address /
443	#define EVSYS_INST_NUM 1 /*< \brief (EVSYS) Number of instances /
444	#define EVSYS_INSTS { EVSYS } /*< \brief (EVSYS) Instances List /
445
446	#define GCLK ((Gclk )0x40000C00U) /< \brief (GCLK) APB Base Address /
447	#define GCLK_INST_NUM 1 /*< \brief (GCLK) Number of instances /
448	#define GCLK_INSTS { GCLK } /*< \brief (GCLK) Instances List /
449
450	#define I2S ((I2s )0x42005000U) /< \brief (I2S) APB Base Address /
451	#define I2S_INST_NUM 1 /*< \brief (I2S) Number of instances /
452	#define I2S_INSTS { I2S } /*< \brief (I2S) Instances List /
453
454	#define MTB ((Mtb )0x41006000U) /< \brief (MTB) APB Base Address /
455	#define MTB_INST_NUM 1 /*< \brief (MTB) Number of instances /
456	#define MTB_INSTS { MTB } /*< \brief (MTB) Instances List /
457
458	#define NVMCTRL ((Nvmctrl )0x41004000U) /< \brief (NVMCTRL) APB Base Address /
459	#define NVMCTRL_CAL (0x00800000U) /*< \brief (NVMCTRL) CAL Base Address /
460	#define NVMCTRL_LOCKBIT (0x00802000U) /*< \brief (NVMCTRL) LOCKBIT Base Address /
461	#define NVMCTRL_OTP1 (0x00806000U) /*< \brief (NVMCTRL) OTP1 Base Address /
462	#define NVMCTRL_OTP2 (0x00806008U) /*< \brief (NVMCTRL) OTP2 Base Address /
463	#define NVMCTRL_OTP4 (0x00806020U) /*< \brief (NVMCTRL) OTP4 Base Address /
464	#define NVMCTRL_TEMP_LOG (0x00806030U) /*< \brief (NVMCTRL) TEMP_LOG Base Address /
465	#define NVMCTRL_USER (0x00804000U) /*< \brief (NVMCTRL) USER Base Address /
466	#define NVMCTRL_INST_NUM 1 /*< \brief (NVMCTRL) Number of instances /
467	#define NVMCTRL_INSTS { NVMCTRL } /*< \brief (NVMCTRL) Instances List /
468
469	#define PAC0 ((Pac )0x40000000U) /< \brief (PAC0) APB Base Address /
470	#define PAC1 ((Pac )0x41000000U) /< \brief (PAC1) APB Base Address /
471	#define PAC2 ((Pac )0x42000000U) /< \brief (PAC2) APB Base Address /
472	#define PAC_INST_NUM 3 /*< \brief (PAC) Number of instances /
473	#define PAC_INSTS { PAC0, PAC1, PAC2 } /*< \brief (PAC) Instances List /
474
475	#define PM ((Pm )0x40000400U) /< \brief (PM) APB Base Address /
476	#define PM_INST_NUM 1 /*< \brief (PM) Number of instances /
477	#define PM_INSTS { PM } /*< \brief (PM) Instances List /
478
479	#define PORT ((Port )0x41004400U) /< \brief (PORT) APB Base Address /
480	#define PORT_IOBUS ((Port )0x60000000U) /< \brief (PORT) IOBUS Base Address /
481	#define PORT_INST_NUM 1 /*< \brief (PORT) Number of instances /
482	#define PORT_INSTS { PORT } /*< \brief (PORT) Instances List /
483
484	#define PTC_GCLK_ID 34
485	#define PTC_INST_NUM 1 /*< \brief (PTC) Number of instances /
486	#define PTC_INSTS { PTC } /*< \brief (PTC) Instances List /
487
488	#define RTC ((Rtc )0x40001400U) /< \brief (RTC) APB Base Address /
489	#define RTC_INST_NUM 1 /*< \brief (RTC) Number of instances /
490	#define RTC_INSTS { RTC } /*< \brief (RTC) Instances List /
491
492	#define SERCOM0 ((Sercom )0x42000800U) /< \brief (SERCOM0) APB Base Address /
493	#define SERCOM1 ((Sercom )0x42000C00U) /< \brief (SERCOM1) APB Base Address /
494	#define SERCOM2 ((Sercom )0x42001000U) /< \brief (SERCOM2) APB Base Address /
495	#define SERCOM3 ((Sercom )0x42001400U) /< \brief (SERCOM3) APB Base Address /
496	#define SERCOM4 ((Sercom )0x42001800U) /< \brief (SERCOM4) APB Base Address /
497	#define SERCOM5 ((Sercom )0x42001C00U) /< \brief (SERCOM5) APB Base Address /
498	#define SERCOM_INST_NUM 6 /*< \brief (SERCOM) Number of instances /
499	#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /*< \brief (SERCOM) Instances List /
500
501	#define SYSCTRL ((Sysctrl )0x40000800U) /< \brief (SYSCTRL) APB Base Address /
502	#define SYSCTRL_INST_NUM 1 /*< \brief (SYSCTRL) Number of instances /
503	#define SYSCTRL_INSTS { SYSCTRL } /*< \brief (SYSCTRL) Instances List /
504
505	#define TC3 ((Tc )0x42002C00U) /< \brief (TC3) APB Base Address /
506	#define TC4 ((Tc )0x42003000U) /< \brief (TC4) APB Base Address /
507	#define TC5 ((Tc )0x42003400U) /< \brief (TC5) APB Base Address /
508	#define TC6 ((Tc )0x42003800U) /< \brief (TC6) APB Base Address /
509	#define TC7 ((Tc )0x42003C00U) /< \brief (TC7) APB Base Address /
510	#define TC_INST_NUM 5 /*< \brief (TC) Number of instances /
511	#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /*< \brief (TC) Instances List /
512
513	#define TCC0 ((Tcc )0x42002000U) /< \brief (TCC0) APB Base Address /
514	#define TCC1 ((Tcc )0x42002400U) /< \brief (TCC1) APB Base Address /
515	#define TCC2 ((Tcc )0x42002800U) /< \brief (TCC2) APB Base Address /
516	#define TCC_INST_NUM 3 /*< \brief (TCC) Number of instances /
517	#define TCC_INSTS { TCC0, TCC1, TCC2 } /*< \brief (TCC) Instances List /
518
519	#define USB ((Usb )0x41005000U) /< \brief (USB) APB Base Address /
520	#define USB_INST_NUM 1 /*< \brief (USB) Number of instances /
521	#define USB_INSTS { USB } /*< \brief (USB) Instances List /
522
523	#define WDT ((Wdt )0x40001000U) /< \brief (WDT) APB Base Address /
524	#define WDT_INST_NUM 1 /*< \brief (WDT) Number of instances /
525	#define WDT_INSTS { WDT } /*< \brief (WDT) Instances List /
526
527	#endif /* (defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__)) */
528	/@}/
529
530	/* ************************************************************************** */
531	/** PORT DEFINITIONS FOR SAMD21J17A */
532	/* ************************************************************************** */
533	/** \defgroup SAMD21J17A_port PORT Definitions */
534	/@{/
535
536	#include "pio/samd21j17a.h"
537	/@}/
538
539	/* ************************************************************************** */
540	/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
541	/* ************************************************************************** */
542
543	#define FLASH_SIZE 0x20000 /* 128 kB */
544	#define FLASH_PAGE_SIZE 64
545	#define FLASH_NB_OF_PAGES 2048
546	#define FLASH_USER_PAGE_SIZE 64
547	#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
548	#define FLASH_ADDR (0x00000000U) /*< FLASH base address /
549	#define FLASH_USER_PAGE_ADDR (0x00800000U) /*< FLASH_USER_PAGE base address /
550	#define HMCRAMC0_ADDR (0x20000000U) /*< HMCRAMC0 base address /
551
552	#define DSU_DID_RESETVALUE 0x10010001
553	#define PORT_GROUPS 2
554
555	/* ************************************************************************** */
556	/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */
557	/* ************************************************************************** */
558
559
560	#ifdef __cplusplus
561	}
562	#endif
563
564	/@}/
565
566	#endif /* SAMD21J17A_H */

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/samd21j17a.h@ 136

Download in other formats: