source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/pio/samd21j16a.h@ 136

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1/**
2 * \file
3 *
4 * \brief Peripheral I/O description for SAMD21J16A
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21J16A_PIO_
45#define _SAMD21J16A_PIO_
46
47#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
48#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
49#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
50#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
51#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
52#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
53#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
54#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
55#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
56#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
57#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
58#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
59#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
60#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
61#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
62#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
63#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
64#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
65#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
66#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
67#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
68#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
69#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
70#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
71#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
72#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
73#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
74#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
75#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
76#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
77#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
78#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
79#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
80#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
81#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
82#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
83#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
84#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
85#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
86#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
87#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
88#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
89#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
90#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
91#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
92#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
93#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
94#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
95#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
96#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
97#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
98#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
99#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
100#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
101#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
102#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
103#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
104#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
105#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
106#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
107#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
108#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */
109#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
110#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */
111#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
112#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
113#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
114#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
115#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
116#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */
117#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
118#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */
119#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
120#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */
121#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
122#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */
123#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
124#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
125#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
126#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
127#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
128#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
129#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
130#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
131#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
132#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */
133#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
134#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */
135#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
136#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */
137#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
138#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */
139#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
140#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */
141#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
142#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */
143#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
144#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
145#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
146#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
147#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
148#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */
149#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
150#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */
151/* ========== PORT definition for CORE peripheral ========== */
152#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
153#define MUX_PA30G_CORE_SWCLK 6
154#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
155#define PORT_PA30G_CORE_SWCLK (1u << 30)
156/* ========== PORT definition for GCLK peripheral ========== */
157#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */
158#define MUX_PB14H_GCLK_IO0 7
159#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
160#define PORT_PB14H_GCLK_IO0 (1u << 14)
161#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
162#define MUX_PB22H_GCLK_IO0 7
163#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
164#define PORT_PB22H_GCLK_IO0 (1u << 22)
165#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
166#define MUX_PA14H_GCLK_IO0 7
167#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
168#define PORT_PA14H_GCLK_IO0 (1u << 14)
169#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
170#define MUX_PA27H_GCLK_IO0 7
171#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
172#define PORT_PA27H_GCLK_IO0 (1u << 27)
173#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
174#define MUX_PA28H_GCLK_IO0 7
175#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
176#define PORT_PA28H_GCLK_IO0 (1u << 28)
177#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
178#define MUX_PA30H_GCLK_IO0 7
179#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
180#define PORT_PA30H_GCLK_IO0 (1u << 30)
181#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */
182#define MUX_PB15H_GCLK_IO1 7
183#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
184#define PORT_PB15H_GCLK_IO1 (1u << 15)
185#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
186#define MUX_PB23H_GCLK_IO1 7
187#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
188#define PORT_PB23H_GCLK_IO1 (1u << 23)
189#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
190#define MUX_PA15H_GCLK_IO1 7
191#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
192#define PORT_PA15H_GCLK_IO1 (1u << 15)
193#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */
194#define MUX_PB16H_GCLK_IO2 7
195#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
196#define PORT_PB16H_GCLK_IO2 (1u << 16)
197#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
198#define MUX_PA16H_GCLK_IO2 7
199#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
200#define PORT_PA16H_GCLK_IO2 (1u << 16)
201#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
202#define MUX_PA17H_GCLK_IO3 7
203#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
204#define PORT_PA17H_GCLK_IO3 (1u << 17)
205#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */
206#define MUX_PB17H_GCLK_IO3 7
207#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
208#define PORT_PB17H_GCLK_IO3 (1u << 17)
209#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
210#define MUX_PA10H_GCLK_IO4 7
211#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
212#define PORT_PA10H_GCLK_IO4 (1u << 10)
213#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
214#define MUX_PA20H_GCLK_IO4 7
215#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
216#define PORT_PA20H_GCLK_IO4 (1u << 20)
217#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
218#define MUX_PB10H_GCLK_IO4 7
219#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
220#define PORT_PB10H_GCLK_IO4 (1u << 10)
221#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
222#define MUX_PA11H_GCLK_IO5 7
223#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
224#define PORT_PA11H_GCLK_IO5 (1u << 11)
225#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
226#define MUX_PA21H_GCLK_IO5 7
227#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
228#define PORT_PA21H_GCLK_IO5 (1u << 21)
229#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
230#define MUX_PB11H_GCLK_IO5 7
231#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
232#define PORT_PB11H_GCLK_IO5 (1u << 11)
233#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
234#define MUX_PA22H_GCLK_IO6 7
235#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
236#define PORT_PA22H_GCLK_IO6 (1u << 22)
237#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */
238#define MUX_PB12H_GCLK_IO6 7
239#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
240#define PORT_PB12H_GCLK_IO6 (1u << 12)
241#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
242#define MUX_PA23H_GCLK_IO7 7
243#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
244#define PORT_PA23H_GCLK_IO7 (1u << 23)
245#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */
246#define MUX_PB13H_GCLK_IO7 7
247#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
248#define PORT_PB13H_GCLK_IO7 (1u << 13)
249/* ========== PORT definition for EIC peripheral ========== */
250#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
251#define MUX_PA16A_EIC_EXTINT0 0
252#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
253#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
254#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */
255#define MUX_PB00A_EIC_EXTINT0 0
256#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
257#define PORT_PB00A_EIC_EXTINT0 (1u << 0)
258#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */
259#define MUX_PB16A_EIC_EXTINT0 0
260#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
261#define PORT_PB16A_EIC_EXTINT0 (1u << 16)
262#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
263#define MUX_PA00A_EIC_EXTINT0 0
264#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
265#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
266#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
267#define MUX_PA17A_EIC_EXTINT1 0
268#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
269#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
270#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */
271#define MUX_PB01A_EIC_EXTINT1 0
272#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
273#define PORT_PB01A_EIC_EXTINT1 (1u << 1)
274#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */
275#define MUX_PB17A_EIC_EXTINT1 0
276#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
277#define PORT_PB17A_EIC_EXTINT1 (1u << 17)
278#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
279#define MUX_PA01A_EIC_EXTINT1 0
280#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
281#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
282#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
283#define MUX_PA18A_EIC_EXTINT2 0
284#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
285#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
286#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
287#define MUX_PA02A_EIC_EXTINT2 0
288#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
289#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
290#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
291#define MUX_PB02A_EIC_EXTINT2 0
292#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
293#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
294#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
295#define MUX_PA03A_EIC_EXTINT3 0
296#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
297#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
298#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
299#define MUX_PA19A_EIC_EXTINT3 0
300#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
301#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
302#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
303#define MUX_PB03A_EIC_EXTINT3 0
304#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
305#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
306#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
307#define MUX_PA04A_EIC_EXTINT4 0
308#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
309#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
310#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
311#define MUX_PA20A_EIC_EXTINT4 0
312#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
313#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
314#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */
315#define MUX_PB04A_EIC_EXTINT4 0
316#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
317#define PORT_PB04A_EIC_EXTINT4 (1u << 4)
318#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
319#define MUX_PA05A_EIC_EXTINT5 0
320#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
321#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
322#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
323#define MUX_PA21A_EIC_EXTINT5 0
324#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
325#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
326#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */
327#define MUX_PB05A_EIC_EXTINT5 0
328#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
329#define PORT_PB05A_EIC_EXTINT5 (1u << 5)
330#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
331#define MUX_PA06A_EIC_EXTINT6 0
332#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
333#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
334#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
335#define MUX_PA22A_EIC_EXTINT6 0
336#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
337#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
338#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */
339#define MUX_PB06A_EIC_EXTINT6 0
340#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
341#define PORT_PB06A_EIC_EXTINT6 (1u << 6)
342#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
343#define MUX_PB22A_EIC_EXTINT6 0
344#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
345#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
346#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
347#define MUX_PA07A_EIC_EXTINT7 0
348#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
349#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
350#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
351#define MUX_PA23A_EIC_EXTINT7 0
352#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
353#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
354#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */
355#define MUX_PB07A_EIC_EXTINT7 0
356#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
357#define PORT_PB07A_EIC_EXTINT7 (1u << 7)
358#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
359#define MUX_PB23A_EIC_EXTINT7 0
360#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
361#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
362#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
363#define MUX_PA28A_EIC_EXTINT8 0
364#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
365#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
366#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
367#define MUX_PB08A_EIC_EXTINT8 0
368#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
369#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
370#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
371#define MUX_PA09A_EIC_EXTINT9 0
372#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
373#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
374#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
375#define MUX_PB09A_EIC_EXTINT9 0
376#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
377#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
378#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
379#define MUX_PA10A_EIC_EXTINT10 0
380#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
381#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
382#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
383#define MUX_PA30A_EIC_EXTINT10 0
384#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
385#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
386#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
387#define MUX_PB10A_EIC_EXTINT10 0
388#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
389#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
390#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
391#define MUX_PA18A_EIC_EXTINT10 0
392#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
393#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
394#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
395#define MUX_PA11A_EIC_EXTINT11 0
396#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
397#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
398#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
399#define MUX_PA31A_EIC_EXTINT11 0
400#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
401#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
402#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
403#define MUX_PB11A_EIC_EXTINT11 0
404#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
405#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
406#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
407#define MUX_PA12A_EIC_EXTINT12 0
408#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
409#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
410#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
411#define MUX_PA24A_EIC_EXTINT12 0
412#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
413#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
414#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */
415#define MUX_PB12A_EIC_EXTINT12 0
416#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
417#define PORT_PB12A_EIC_EXTINT12 (1u << 12)
418#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
419#define MUX_PA13A_EIC_EXTINT13 0
420#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
421#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
422#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
423#define MUX_PA25A_EIC_EXTINT13 0
424#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
425#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
426#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */
427#define MUX_PB13A_EIC_EXTINT13 0
428#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
429#define PORT_PB13A_EIC_EXTINT13 (1u << 13)
430#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */
431#define MUX_PB14A_EIC_EXTINT14 0
432#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
433#define PORT_PB14A_EIC_EXTINT14 (1u << 14)
434#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */
435#define MUX_PB30A_EIC_EXTINT14 0
436#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
437#define PORT_PB30A_EIC_EXTINT14 (1u << 30)
438#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
439#define MUX_PA14A_EIC_EXTINT14 0
440#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
441#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
442#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
443#define MUX_PA15A_EIC_EXTINT15 0
444#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
445#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
446#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
447#define MUX_PA27A_EIC_EXTINT15 0
448#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
449#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
450#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */
451#define MUX_PB15A_EIC_EXTINT15 0
452#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
453#define PORT_PB15A_EIC_EXTINT15 (1u << 15)
454#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */
455#define MUX_PB31A_EIC_EXTINT15 0
456#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
457#define PORT_PB31A_EIC_EXTINT15 (1u << 31)
458#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
459#define MUX_PA12A_EIC_EXTINT17 0
460#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
461#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
462#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
463#define MUX_PA08A_EIC_NMI 0
464#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
465#define PORT_PA08A_EIC_NMI (1u << 8)
466/* ========== PORT definition for USB peripheral ========== */
467#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
468#define MUX_PA24G_USB_DM 6
469#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
470#define PORT_PA24G_USB_DM (1u << 24)
471#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
472#define MUX_PA25G_USB_DP 6
473#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
474#define PORT_PA25G_USB_DP (1u << 25)
475#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
476#define MUX_PA23G_USB_SOF_1KHZ 6
477#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
478#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
479/* ========== PORT definition for SERCOM0 peripheral ========== */
480#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
481#define MUX_PA04D_SERCOM0_PAD0 3
482#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
483#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
484#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
485#define MUX_PA08C_SERCOM0_PAD0 2
486#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
487#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
488#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
489#define MUX_PA13A_SERCOM0_PAD0 0
490#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
491#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
492#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
493#define MUX_PA05D_SERCOM0_PAD1 3
494#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
495#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
496#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
497#define MUX_PA09C_SERCOM0_PAD1 2
498#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
499#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
500#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
501#define MUX_PA06D_SERCOM0_PAD2 3
502#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
503#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
504#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
505#define MUX_PA10C_SERCOM0_PAD2 2
506#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
507#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
508#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
509#define MUX_PA07D_SERCOM0_PAD3 3
510#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
511#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
512#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
513#define MUX_PA11C_SERCOM0_PAD3 2
514#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
515#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
516/* ========== PORT definition for SERCOM1 peripheral ========== */
517#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
518#define MUX_PA16C_SERCOM1_PAD0 2
519#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
520#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
521#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
522#define MUX_PA00D_SERCOM1_PAD0 3
523#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
524#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
525#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
526#define MUX_PA17C_SERCOM1_PAD1 2
527#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
528#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
529#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
530#define MUX_PA01D_SERCOM1_PAD1 3
531#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
532#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
533#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
534#define MUX_PA30D_SERCOM1_PAD2 3
535#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
536#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
537#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
538#define MUX_PA18C_SERCOM1_PAD2 2
539#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
540#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
541#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
542#define MUX_PA31D_SERCOM1_PAD3 3
543#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
544#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
545#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
546#define MUX_PA19C_SERCOM1_PAD3 2
547#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
548#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
549/* ========== PORT definition for SERCOM2 peripheral ========== */
550#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
551#define MUX_PA08D_SERCOM2_PAD0 3
552#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
553#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
554#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
555#define MUX_PA12C_SERCOM2_PAD0 2
556#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
557#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
558#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
559#define MUX_PA15A_SERCOM2_PAD0 0
560#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
561#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
562#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
563#define MUX_PA09D_SERCOM2_PAD1 3
564#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
565#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
566#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
567#define MUX_PA13C_SERCOM2_PAD1 2
568#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
569#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
570#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
571#define MUX_PA10D_SERCOM2_PAD2 3
572#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
573#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
574#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
575#define MUX_PA14C_SERCOM2_PAD2 2
576#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
577#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
578#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
579#define MUX_PA11D_SERCOM2_PAD3 3
580#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
581#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
582#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
583#define MUX_PA15C_SERCOM2_PAD3 2
584#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
585#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
586/* ========== PORT definition for SERCOM3 peripheral ========== */
587#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
588#define MUX_PA16D_SERCOM3_PAD0 3
589#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
590#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
591#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
592#define MUX_PA22C_SERCOM3_PAD0 2
593#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
594#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
595#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
596#define MUX_PA27F_SERCOM3_PAD0 5
597#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
598#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
599#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
600#define MUX_PA17D_SERCOM3_PAD1 3
601#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
602#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
603#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
604#define MUX_PA23C_SERCOM3_PAD1 2
605#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
606#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
607#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
608#define MUX_PA28F_SERCOM3_PAD1 5
609#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
610#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
611#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
612#define MUX_PA18D_SERCOM3_PAD2 3
613#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
614#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
615#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
616#define MUX_PA20D_SERCOM3_PAD2 3
617#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
618#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
619#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
620#define MUX_PA24C_SERCOM3_PAD2 2
621#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
622#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
623#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
624#define MUX_PA19D_SERCOM3_PAD3 3
625#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
626#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
627#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
628#define MUX_PA21D_SERCOM3_PAD3 3
629#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
630#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
631#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
632#define MUX_PA25C_SERCOM3_PAD3 2
633#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
634#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
635/* ========== PORT definition for SERCOM4 peripheral ========== */
636#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
637#define MUX_PA12D_SERCOM4_PAD0 3
638#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
639#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
640#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
641#define MUX_PB08D_SERCOM4_PAD0 3
642#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
643#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
644#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
645#define MUX_PB12C_SERCOM4_PAD0 2
646#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
647#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)
648#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
649#define MUX_PA13D_SERCOM4_PAD1 3
650#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
651#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
652#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
653#define MUX_PB09D_SERCOM4_PAD1 3
654#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
655#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
656#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
657#define MUX_PB13C_SERCOM4_PAD1 2
658#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
659#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)
660#define PIN_PB31F_SERCOM4_PAD1 63 /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */
661#define MUX_PB31F_SERCOM4_PAD1 5
662#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1)
663#define PORT_PB31F_SERCOM4_PAD1 (1u << 31)
664#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
665#define MUX_PA14D_SERCOM4_PAD2 3
666#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
667#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
668#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
669#define MUX_PB10D_SERCOM4_PAD2 3
670#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
671#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
672#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
673#define MUX_PB14C_SERCOM4_PAD2 2
674#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
675#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)
676#define PIN_PB30F_SERCOM4_PAD2 62 /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */
677#define MUX_PB30F_SERCOM4_PAD2 5
678#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2)
679#define PORT_PB30F_SERCOM4_PAD2 (1u << 30)
680#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
681#define MUX_PA15D_SERCOM4_PAD3 3
682#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
683#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
684#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
685#define MUX_PB11D_SERCOM4_PAD3 3
686#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
687#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
688#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
689#define MUX_PB15C_SERCOM4_PAD3 2
690#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
691#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)
692/* ========== PORT definition for SERCOM5 peripheral ========== */
693#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
694#define MUX_PB16C_SERCOM5_PAD0 2
695#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
696#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)
697#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
698#define MUX_PA22D_SERCOM5_PAD0 3
699#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
700#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
701#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
702#define MUX_PB02D_SERCOM5_PAD0 3
703#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
704#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
705#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
706#define MUX_PB30D_SERCOM5_PAD0 3
707#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
708#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)
709#define PIN_PB17C_SERCOM5_PAD0 49 /**< \brief SERCOM5 signal: PAD0 on PB17 mux C */
710#define MUX_PB17C_SERCOM5_PAD0 2
711#define PINMUX_PB17C_SERCOM5_PAD0 ((PIN_PB17C_SERCOM5_PAD0 << 16) | MUX_PB17C_SERCOM5_PAD0)
712#define PORT_PB17C_SERCOM5_PAD0 (1u << 17)
713#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
714#define MUX_PB17C_SERCOM5_PAD1 2
715#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
716#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)
717#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
718#define MUX_PA23D_SERCOM5_PAD1 3
719#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
720#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
721#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
722#define MUX_PB03D_SERCOM5_PAD1 3
723#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
724#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
725#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
726#define MUX_PB31D_SERCOM5_PAD1 3
727#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
728#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)
729#define PIN_PB16C_SERCOM5_PAD1 48 /**< \brief SERCOM5 signal: PAD1 on PB16 mux C */
730#define MUX_PB16C_SERCOM5_PAD1 2
731#define PINMUX_PB16C_SERCOM5_PAD1 ((PIN_PB16C_SERCOM5_PAD1 << 16) | MUX_PB16C_SERCOM5_PAD1)
732#define PORT_PB16C_SERCOM5_PAD1 (1u << 16)
733#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
734#define MUX_PA24D_SERCOM5_PAD2 3
735#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
736#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
737#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
738#define MUX_PB00D_SERCOM5_PAD2 3
739#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
740#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)
741#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
742#define MUX_PB22D_SERCOM5_PAD2 3
743#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
744#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
745#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
746#define MUX_PA20C_SERCOM5_PAD2 2
747#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
748#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
749#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
750#define MUX_PA25D_SERCOM5_PAD3 3
751#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
752#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
753#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
754#define MUX_PB01D_SERCOM5_PAD3 3
755#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
756#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)
757#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
758#define MUX_PB23D_SERCOM5_PAD3 3
759#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
760#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
761#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
762#define MUX_PA21C_SERCOM5_PAD3 2
763#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
764#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
765/* ========== PORT definition for TCC0 peripheral ========== */
766#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
767#define MUX_PA04E_TCC0_WO0 4
768#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
769#define PORT_PA04E_TCC0_WO0 (1u << 4)
770#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
771#define MUX_PA08E_TCC0_WO0 4
772#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
773#define PORT_PA08E_TCC0_WO0 (1u << 8)
774#define PIN_PB30E_TCC0_WO0 62 /**< \brief TCC0 signal: WO0 on PB30 mux E */
775#define MUX_PB30E_TCC0_WO0 4
776#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
777#define PORT_PB30E_TCC0_WO0 (1u << 30)
778#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
779#define MUX_PA16F_TCC0_WO0 5
780#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
781#define PORT_PA16F_TCC0_WO0 (1u << 16)
782#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
783#define MUX_PA05E_TCC0_WO1 4
784#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
785#define PORT_PA05E_TCC0_WO1 (1u << 5)
786#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
787#define MUX_PA09E_TCC0_WO1 4
788#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
789#define PORT_PA09E_TCC0_WO1 (1u << 9)
790#define PIN_PB31E_TCC0_WO1 63 /**< \brief TCC0 signal: WO1 on PB31 mux E */
791#define MUX_PB31E_TCC0_WO1 4
792#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
793#define PORT_PB31E_TCC0_WO1 (1u << 31)
794#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
795#define MUX_PA17F_TCC0_WO1 5
796#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
797#define PORT_PA17F_TCC0_WO1 (1u << 17)
798#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
799#define MUX_PA10F_TCC0_WO2 5
800#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
801#define PORT_PA10F_TCC0_WO2 (1u << 10)
802#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
803#define MUX_PA18F_TCC0_WO2 5
804#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
805#define PORT_PA18F_TCC0_WO2 (1u << 18)
806#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
807#define MUX_PA11F_TCC0_WO3 5
808#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
809#define PORT_PA11F_TCC0_WO3 (1u << 11)
810#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
811#define MUX_PA19F_TCC0_WO3 5
812#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
813#define PORT_PA19F_TCC0_WO3 (1u << 19)
814#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
815#define MUX_PA14F_TCC0_WO4 5
816#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
817#define PORT_PA14F_TCC0_WO4 (1u << 14)
818#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
819#define MUX_PA22F_TCC0_WO4 5
820#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
821#define PORT_PA22F_TCC0_WO4 (1u << 22)
822#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
823#define MUX_PB10F_TCC0_WO4 5
824#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
825#define PORT_PB10F_TCC0_WO4 (1u << 10)
826#define PIN_PB16F_TCC0_WO4 48 /**< \brief TCC0 signal: WO4 on PB16 mux F */
827#define MUX_PB16F_TCC0_WO4 5
828#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
829#define PORT_PB16F_TCC0_WO4 (1u << 16)
830#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
831#define MUX_PA15F_TCC0_WO5 5
832#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
833#define PORT_PA15F_TCC0_WO5 (1u << 15)
834#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
835#define MUX_PA23F_TCC0_WO5 5
836#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
837#define PORT_PA23F_TCC0_WO5 (1u << 23)
838#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
839#define MUX_PB11F_TCC0_WO5 5
840#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
841#define PORT_PB11F_TCC0_WO5 (1u << 11)
842#define PIN_PB17F_TCC0_WO5 49 /**< \brief TCC0 signal: WO5 on PB17 mux F */
843#define MUX_PB17F_TCC0_WO5 5
844#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
845#define PORT_PB17F_TCC0_WO5 (1u << 17)
846#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
847#define MUX_PA12F_TCC0_WO6 5
848#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
849#define PORT_PA12F_TCC0_WO6 (1u << 12)
850#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
851#define MUX_PA20F_TCC0_WO6 5
852#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
853#define PORT_PA20F_TCC0_WO6 (1u << 20)
854#define PIN_PB12F_TCC0_WO6 44 /**< \brief TCC0 signal: WO6 on PB12 mux F */
855#define MUX_PB12F_TCC0_WO6 5
856#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
857#define PORT_PB12F_TCC0_WO6 (1u << 12)
858#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
859#define MUX_PA16F_TCC0_WO6 5
860#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
861#define PORT_PA16F_TCC0_WO6 (1u << 16)
862#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
863#define MUX_PA13F_TCC0_WO7 5
864#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
865#define PORT_PA13F_TCC0_WO7 (1u << 13)
866#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
867#define MUX_PA21F_TCC0_WO7 5
868#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
869#define PORT_PA21F_TCC0_WO7 (1u << 21)
870#define PIN_PB13F_TCC0_WO7 45 /**< \brief TCC0 signal: WO7 on PB13 mux F */
871#define MUX_PB13F_TCC0_WO7 5
872#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
873#define PORT_PB13F_TCC0_WO7 (1u << 13)
874#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
875#define MUX_PA17F_TCC0_WO7 5
876#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
877#define PORT_PA17F_TCC0_WO7 (1u << 17)
878/* ========== PORT definition for TCC1 peripheral ========== */
879#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
880#define MUX_PA06E_TCC1_WO0 4
881#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
882#define PORT_PA06E_TCC1_WO0 (1u << 6)
883#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
884#define MUX_PA10E_TCC1_WO0 4
885#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
886#define PORT_PA10E_TCC1_WO0 (1u << 10)
887#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
888#define MUX_PA30E_TCC1_WO0 4
889#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
890#define PORT_PA30E_TCC1_WO0 (1u << 30)
891#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
892#define MUX_PA07E_TCC1_WO1 4
893#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
894#define PORT_PA07E_TCC1_WO1 (1u << 7)
895#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
896#define MUX_PA11E_TCC1_WO1 4
897#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
898#define PORT_PA11E_TCC1_WO1 (1u << 11)
899#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
900#define MUX_PA31E_TCC1_WO1 4
901#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
902#define PORT_PA31E_TCC1_WO1 (1u << 31)
903#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
904#define MUX_PA08F_TCC1_WO2 5
905#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
906#define PORT_PA08F_TCC1_WO2 (1u << 8)
907#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
908#define MUX_PA24F_TCC1_WO2 5
909#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
910#define PORT_PA24F_TCC1_WO2 (1u << 24)
911#define PIN_PB30F_TCC1_WO2 62 /**< \brief TCC1 signal: WO2 on PB30 mux F */
912#define MUX_PB30F_TCC1_WO2 5
913#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
914#define PORT_PB30F_TCC1_WO2 (1u << 30)
915#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
916#define MUX_PA09F_TCC1_WO3 5
917#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
918#define PORT_PA09F_TCC1_WO3 (1u << 9)
919#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
920#define MUX_PA25F_TCC1_WO3 5
921#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
922#define PORT_PA25F_TCC1_WO3 (1u << 25)
923#define PIN_PB31F_TCC1_WO3 63 /**< \brief TCC1 signal: WO3 on PB31 mux F */
924#define MUX_PB31F_TCC1_WO3 5
925#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
926#define PORT_PB31F_TCC1_WO3 (1u << 31)
927/* ========== PORT definition for TCC2 peripheral ========== */
928#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
929#define MUX_PA12E_TCC2_WO0 4
930#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
931#define PORT_PA12E_TCC2_WO0 (1u << 12)
932#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
933#define MUX_PA16E_TCC2_WO0 4
934#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
935#define PORT_PA16E_TCC2_WO0 (1u << 16)
936#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
937#define MUX_PA00E_TCC2_WO0 4
938#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
939#define PORT_PA00E_TCC2_WO0 (1u << 0)
940#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
941#define MUX_PA13E_TCC2_WO1 4
942#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
943#define PORT_PA13E_TCC2_WO1 (1u << 13)
944#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
945#define MUX_PA17E_TCC2_WO1 4
946#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
947#define PORT_PA17E_TCC2_WO1 (1u << 17)
948#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
949#define MUX_PA01E_TCC2_WO1 4
950#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
951#define PORT_PA01E_TCC2_WO1 (1u << 1)
952/* ========== PORT definition for TC3 peripheral ========== */
953#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
954#define MUX_PA18E_TC3_WO0 4
955#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
956#define PORT_PA18E_TC3_WO0 (1u << 18)
957#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
958#define MUX_PA14E_TC3_WO0 4
959#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
960#define PORT_PA14E_TC3_WO0 (1u << 14)
961#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
962#define MUX_PA19E_TC3_WO1 4
963#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
964#define PORT_PA19E_TC3_WO1 (1u << 19)
965#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
966#define MUX_PA15E_TC3_WO1 4
967#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
968#define PORT_PA15E_TC3_WO1 (1u << 15)
969/* ========== PORT definition for TC4 peripheral ========== */
970#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
971#define MUX_PA22E_TC4_WO0 4
972#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
973#define PORT_PA22E_TC4_WO0 (1u << 22)
974#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
975#define MUX_PB08E_TC4_WO0 4
976#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
977#define PORT_PB08E_TC4_WO0 (1u << 8)
978#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */
979#define MUX_PB12E_TC4_WO0 4
980#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
981#define PORT_PB12E_TC4_WO0 (1u << 12)
982#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
983#define MUX_PA23E_TC4_WO1 4
984#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
985#define PORT_PA23E_TC4_WO1 (1u << 23)
986#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
987#define MUX_PB09E_TC4_WO1 4
988#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
989#define PORT_PB09E_TC4_WO1 (1u << 9)
990#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */
991#define MUX_PB13E_TC4_WO1 4
992#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
993#define PORT_PB13E_TC4_WO1 (1u << 13)
994/* ========== PORT definition for TC5 peripheral ========== */
995#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
996#define MUX_PA24E_TC5_WO0 4
997#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
998#define PORT_PA24E_TC5_WO0 (1u << 24)
999#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
1000#define MUX_PB10E_TC5_WO0 4
1001#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
1002#define PORT_PB10E_TC5_WO0 (1u << 10)
1003#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */
1004#define MUX_PB14E_TC5_WO0 4
1005#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
1006#define PORT_PB14E_TC5_WO0 (1u << 14)
1007#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
1008#define MUX_PA25E_TC5_WO1 4
1009#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
1010#define PORT_PA25E_TC5_WO1 (1u << 25)
1011#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
1012#define MUX_PB11E_TC5_WO1 4
1013#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
1014#define PORT_PB11E_TC5_WO1 (1u << 11)
1015#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */
1016#define MUX_PB15E_TC5_WO1 4
1017#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
1018#define PORT_PB15E_TC5_WO1 (1u << 15)
1019/* ========== PORT definition for TC6 peripheral ========== */
1020#define PIN_PB02E_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux E */
1021#define MUX_PB02E_TC6_WO0 4
1022#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
1023#define PORT_PB02E_TC6_WO0 (1u << 2)
1024#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */
1025#define MUX_PB16E_TC6_WO0 4
1026#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
1027#define PORT_PB16E_TC6_WO0 (1u << 16)
1028#define PIN_PB03E_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux E */
1029#define MUX_PB03E_TC6_WO1 4
1030#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
1031#define PORT_PB03E_TC6_WO1 (1u << 3)
1032#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */
1033#define MUX_PB17E_TC6_WO1 4
1034#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
1035#define PORT_PB17E_TC6_WO1 (1u << 17)
1036/* ========== PORT definition for TC7 peripheral ========== */
1037#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */
1038#define MUX_PA20E_TC7_WO0 4
1039#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
1040#define PORT_PA20E_TC7_WO0 (1u << 20)
1041#define PIN_PB00E_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux E */
1042#define MUX_PB00E_TC7_WO0 4
1043#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
1044#define PORT_PB00E_TC7_WO0 (1u << 0)
1045#define PIN_PB22E_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux E */
1046#define MUX_PB22E_TC7_WO0 4
1047#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
1048#define PORT_PB22E_TC7_WO0 (1u << 22)
1049#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */
1050#define MUX_PA21E_TC7_WO1 4
1051#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
1052#define PORT_PA21E_TC7_WO1 (1u << 21)
1053#define PIN_PB01E_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux E */
1054#define MUX_PB01E_TC7_WO1 4
1055#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
1056#define PORT_PB01E_TC7_WO1 (1u << 1)
1057#define PIN_PB23E_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux E */
1058#define MUX_PB23E_TC7_WO1 4
1059#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
1060#define PORT_PB23E_TC7_WO1 (1u << 23)
1061/* ========== PORT definition for ADC peripheral ========== */
1062#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
1063#define MUX_PA02B_ADC_AIN0 1
1064#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
1065#define PORT_PA02B_ADC_AIN0 (1u << 2)
1066#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
1067#define MUX_PA03B_ADC_AIN1 1
1068#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
1069#define PORT_PA03B_ADC_AIN1 (1u << 3)
1070#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
1071#define MUX_PB08B_ADC_AIN2 1
1072#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
1073#define PORT_PB08B_ADC_AIN2 (1u << 8)
1074#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
1075#define MUX_PB09B_ADC_AIN3 1
1076#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
1077#define PORT_PB09B_ADC_AIN3 (1u << 9)
1078#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
1079#define MUX_PA04B_ADC_AIN4 1
1080#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
1081#define PORT_PA04B_ADC_AIN4 (1u << 4)
1082#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
1083#define MUX_PA05B_ADC_AIN5 1
1084#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
1085#define PORT_PA05B_ADC_AIN5 (1u << 5)
1086#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
1087#define MUX_PA06B_ADC_AIN6 1
1088#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
1089#define PORT_PA06B_ADC_AIN6 (1u << 6)
1090#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
1091#define MUX_PA07B_ADC_AIN7 1
1092#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
1093#define PORT_PA07B_ADC_AIN7 (1u << 7)
1094#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */
1095#define MUX_PB00B_ADC_AIN8 1
1096#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
1097#define PORT_PB00B_ADC_AIN8 (1u << 0)
1098#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */
1099#define MUX_PB01B_ADC_AIN9 1
1100#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
1101#define PORT_PB01B_ADC_AIN9 (1u << 1)
1102#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
1103#define MUX_PB02B_ADC_AIN10 1
1104#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
1105#define PORT_PB02B_ADC_AIN10 (1u << 2)
1106#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
1107#define MUX_PB03B_ADC_AIN11 1
1108#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
1109#define PORT_PB03B_ADC_AIN11 (1u << 3)
1110#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */
1111#define MUX_PB04B_ADC_AIN12 1
1112#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
1113#define PORT_PB04B_ADC_AIN12 (1u << 4)
1114#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */
1115#define MUX_PB05B_ADC_AIN13 1
1116#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
1117#define PORT_PB05B_ADC_AIN13 (1u << 5)
1118#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */
1119#define MUX_PB06B_ADC_AIN14 1
1120#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
1121#define PORT_PB06B_ADC_AIN14 (1u << 6)
1122#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */
1123#define MUX_PB07B_ADC_AIN15 1
1124#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
1125#define PORT_PB07B_ADC_AIN15 (1u << 7)
1126#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
1127#define MUX_PA08B_ADC_AIN16 1
1128#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
1129#define PORT_PA08B_ADC_AIN16 (1u << 8)
1130#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
1131#define MUX_PA09B_ADC_AIN17 1
1132#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
1133#define PORT_PA09B_ADC_AIN17 (1u << 9)
1134#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
1135#define MUX_PA10B_ADC_AIN18 1
1136#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
1137#define PORT_PA10B_ADC_AIN18 (1u << 10)
1138#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
1139#define MUX_PA11B_ADC_AIN19 1
1140#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
1141#define PORT_PA11B_ADC_AIN19 (1u << 11)
1142#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
1143#define MUX_PA04B_ADC_VREFP 1
1144#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
1145#define PORT_PA04B_ADC_VREFP (1u << 4)
1146/* ========== PORT definition for AC peripheral ========== */
1147#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
1148#define MUX_PA04B_AC_AIN0 1
1149#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
1150#define PORT_PA04B_AC_AIN0 (1u << 4)
1151#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
1152#define MUX_PA05B_AC_AIN1 1
1153#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
1154#define PORT_PA05B_AC_AIN1 (1u << 5)
1155#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
1156#define MUX_PA06B_AC_AIN2 1
1157#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
1158#define PORT_PA06B_AC_AIN2 (1u << 6)
1159#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
1160#define MUX_PA07B_AC_AIN3 1
1161#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
1162#define PORT_PA07B_AC_AIN3 (1u << 7)
1163#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
1164#define MUX_PA12H_AC_CMP0 7
1165#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
1166#define PORT_PA12H_AC_CMP0 (1u << 12)
1167#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
1168#define MUX_PA18H_AC_CMP0 7
1169#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
1170#define PORT_PA18H_AC_CMP0 (1u << 18)
1171#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
1172#define MUX_PA13H_AC_CMP1 7
1173#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
1174#define PORT_PA13H_AC_CMP1 (1u << 13)
1175#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
1176#define MUX_PA19H_AC_CMP1 7
1177#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
1178#define PORT_PA19H_AC_CMP1 (1u << 19)
1179/* ========== PORT definition for DAC peripheral ========== */
1180#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
1181#define MUX_PA02B_DAC_VOUT 1
1182#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
1183#define PORT_PA02B_DAC_VOUT (1u << 2)
1184#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
1185#define MUX_PA03B_DAC_VREFP 1
1186#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
1187#define PORT_PA03B_DAC_VREFP (1u << 3)
1188/* ========== PORT definition for I2S peripheral ========== */
1189#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
1190#define MUX_PA11G_I2S_FS0 6
1191#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
1192#define PORT_PA11G_I2S_FS0 (1u << 11)
1193#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
1194#define MUX_PA21G_I2S_FS0 6
1195#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
1196#define PORT_PA21G_I2S_FS0 (1u << 21)
1197#define PIN_PB12G_I2S_FS1 44 /**< \brief I2S signal: FS1 on PB12 mux G */
1198#define MUX_PB12G_I2S_FS1 6
1199#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
1200#define PORT_PB12G_I2S_FS1 (1u << 12)
1201#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
1202#define MUX_PA09G_I2S_MCK0 6
1203#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
1204#define PORT_PA09G_I2S_MCK0 (1u << 9)
1205#define PIN_PB17G_I2S_MCK0 49 /**< \brief I2S signal: MCK0 on PB17 mux G */
1206#define MUX_PB17G_I2S_MCK0 6
1207#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
1208#define PORT_PB17G_I2S_MCK0 (1u << 17)
1209#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
1210#define MUX_PB10G_I2S_MCK1 6
1211#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
1212#define PORT_PB10G_I2S_MCK1 (1u << 10)
1213#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
1214#define MUX_PA10G_I2S_SCK0 6
1215#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
1216#define PORT_PA10G_I2S_SCK0 (1u << 10)
1217#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
1218#define MUX_PA20G_I2S_SCK0 6
1219#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
1220#define PORT_PA20G_I2S_SCK0 (1u << 20)
1221#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
1222#define MUX_PB11G_I2S_SCK1 6
1223#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
1224#define PORT_PB11G_I2S_SCK1 (1u << 11)
1225#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
1226#define MUX_PA07G_I2S_SD0 6
1227#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
1228#define PORT_PA07G_I2S_SD0 (1u << 7)
1229#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
1230#define MUX_PA19G_I2S_SD0 6
1231#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
1232#define PORT_PA19G_I2S_SD0 (1u << 19)
1233#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
1234#define MUX_PA08G_I2S_SD1 6
1235#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
1236#define PORT_PA08G_I2S_SD1 (1u << 8)
1237#define PIN_PB16G_I2S_SD1 48 /**< \brief I2S signal: SD1 on PB16 mux G */
1238#define MUX_PB16G_I2S_SD1 6
1239#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
1240#define PORT_PB16G_I2S_SD1 (1u << 16)
1241
1242#endif /* _SAMD21J16A_PIO_ */
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