1 | /**
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2 | * \file
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3 | *
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4 | * \brief Peripheral I/O description for SAMD21G17A
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21G17A_PIO_
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45 | #define _SAMD21G17A_PIO_
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46 |
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47 | #define PIN_PA00 0 /**< \brief Pin Number for PA00 */
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48 | #define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
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49 | #define PIN_PA01 1 /**< \brief Pin Number for PA01 */
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50 | #define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
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51 | #define PIN_PA02 2 /**< \brief Pin Number for PA02 */
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52 | #define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
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53 | #define PIN_PA03 3 /**< \brief Pin Number for PA03 */
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54 | #define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
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55 | #define PIN_PA04 4 /**< \brief Pin Number for PA04 */
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56 | #define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
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57 | #define PIN_PA05 5 /**< \brief Pin Number for PA05 */
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58 | #define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
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59 | #define PIN_PA06 6 /**< \brief Pin Number for PA06 */
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60 | #define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
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61 | #define PIN_PA07 7 /**< \brief Pin Number for PA07 */
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62 | #define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
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63 | #define PIN_PA08 8 /**< \brief Pin Number for PA08 */
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64 | #define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
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65 | #define PIN_PA09 9 /**< \brief Pin Number for PA09 */
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66 | #define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
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67 | #define PIN_PA10 10 /**< \brief Pin Number for PA10 */
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68 | #define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
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69 | #define PIN_PA11 11 /**< \brief Pin Number for PA11 */
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70 | #define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
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71 | #define PIN_PA12 12 /**< \brief Pin Number for PA12 */
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72 | #define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
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73 | #define PIN_PA13 13 /**< \brief Pin Number for PA13 */
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74 | #define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
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75 | #define PIN_PA14 14 /**< \brief Pin Number for PA14 */
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76 | #define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
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77 | #define PIN_PA15 15 /**< \brief Pin Number for PA15 */
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78 | #define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
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79 | #define PIN_PA16 16 /**< \brief Pin Number for PA16 */
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80 | #define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
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81 | #define PIN_PA17 17 /**< \brief Pin Number for PA17 */
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82 | #define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
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83 | #define PIN_PA18 18 /**< \brief Pin Number for PA18 */
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84 | #define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
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85 | #define PIN_PA19 19 /**< \brief Pin Number for PA19 */
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86 | #define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
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87 | #define PIN_PA20 20 /**< \brief Pin Number for PA20 */
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88 | #define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
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89 | #define PIN_PA21 21 /**< \brief Pin Number for PA21 */
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90 | #define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
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91 | #define PIN_PA22 22 /**< \brief Pin Number for PA22 */
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92 | #define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
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93 | #define PIN_PA23 23 /**< \brief Pin Number for PA23 */
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94 | #define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
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95 | #define PIN_PA24 24 /**< \brief Pin Number for PA24 */
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96 | #define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
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97 | #define PIN_PA25 25 /**< \brief Pin Number for PA25 */
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98 | #define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
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99 | #define PIN_PA27 27 /**< \brief Pin Number for PA27 */
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100 | #define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
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101 | #define PIN_PA28 28 /**< \brief Pin Number for PA28 */
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102 | #define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
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103 | #define PIN_PA30 30 /**< \brief Pin Number for PA30 */
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104 | #define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
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105 | #define PIN_PA31 31 /**< \brief Pin Number for PA31 */
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106 | #define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
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107 | #define PIN_PB02 34 /**< \brief Pin Number for PB02 */
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108 | #define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
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109 | #define PIN_PB03 35 /**< \brief Pin Number for PB03 */
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110 | #define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
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111 | #define PIN_PB08 40 /**< \brief Pin Number for PB08 */
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112 | #define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
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113 | #define PIN_PB09 41 /**< \brief Pin Number for PB09 */
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114 | #define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
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115 | #define PIN_PB10 42 /**< \brief Pin Number for PB10 */
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116 | #define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
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117 | #define PIN_PB11 43 /**< \brief Pin Number for PB11 */
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118 | #define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
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119 | #define PIN_PB22 54 /**< \brief Pin Number for PB22 */
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120 | #define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
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121 | #define PIN_PB23 55 /**< \brief Pin Number for PB23 */
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122 | #define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
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123 | /* ========== PORT definition for CORE peripheral ========== */
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124 | #define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
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125 | #define MUX_PA30G_CORE_SWCLK 6
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126 | #define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
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127 | #define PORT_PA30G_CORE_SWCLK (1u << 30)
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128 | /* ========== PORT definition for GCLK peripheral ========== */
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129 | #define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
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130 | #define MUX_PB22H_GCLK_IO0 7
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131 | #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
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132 | #define PORT_PB22H_GCLK_IO0 (1u << 22)
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133 | #define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
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134 | #define MUX_PA14H_GCLK_IO0 7
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135 | #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
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136 | #define PORT_PA14H_GCLK_IO0 (1u << 14)
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137 | #define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
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138 | #define MUX_PA27H_GCLK_IO0 7
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139 | #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
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140 | #define PORT_PA27H_GCLK_IO0 (1u << 27)
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141 | #define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
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142 | #define MUX_PA28H_GCLK_IO0 7
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143 | #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
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144 | #define PORT_PA28H_GCLK_IO0 (1u << 28)
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145 | #define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
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146 | #define MUX_PA30H_GCLK_IO0 7
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147 | #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
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148 | #define PORT_PA30H_GCLK_IO0 (1u << 30)
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149 | #define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
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150 | #define MUX_PB23H_GCLK_IO1 7
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151 | #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
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152 | #define PORT_PB23H_GCLK_IO1 (1u << 23)
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153 | #define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
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154 | #define MUX_PA15H_GCLK_IO1 7
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155 | #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
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156 | #define PORT_PA15H_GCLK_IO1 (1u << 15)
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157 | #define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
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158 | #define MUX_PA16H_GCLK_IO2 7
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159 | #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
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160 | #define PORT_PA16H_GCLK_IO2 (1u << 16)
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161 | #define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
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162 | #define MUX_PA17H_GCLK_IO3 7
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163 | #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
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164 | #define PORT_PA17H_GCLK_IO3 (1u << 17)
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165 | #define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
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166 | #define MUX_PA10H_GCLK_IO4 7
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167 | #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
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168 | #define PORT_PA10H_GCLK_IO4 (1u << 10)
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169 | #define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
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170 | #define MUX_PA20H_GCLK_IO4 7
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171 | #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
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172 | #define PORT_PA20H_GCLK_IO4 (1u << 20)
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173 | #define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
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174 | #define MUX_PB10H_GCLK_IO4 7
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175 | #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
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176 | #define PORT_PB10H_GCLK_IO4 (1u << 10)
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177 | #define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
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178 | #define MUX_PA11H_GCLK_IO5 7
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179 | #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
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180 | #define PORT_PA11H_GCLK_IO5 (1u << 11)
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181 | #define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
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182 | #define MUX_PA21H_GCLK_IO5 7
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183 | #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
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184 | #define PORT_PA21H_GCLK_IO5 (1u << 21)
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185 | #define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
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186 | #define MUX_PB11H_GCLK_IO5 7
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187 | #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
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188 | #define PORT_PB11H_GCLK_IO5 (1u << 11)
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189 | #define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
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190 | #define MUX_PA22H_GCLK_IO6 7
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191 | #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
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192 | #define PORT_PA22H_GCLK_IO6 (1u << 22)
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193 | #define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
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194 | #define MUX_PA23H_GCLK_IO7 7
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195 | #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
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196 | #define PORT_PA23H_GCLK_IO7 (1u << 23)
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197 | /* ========== PORT definition for EIC peripheral ========== */
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198 | #define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
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199 | #define MUX_PA16A_EIC_EXTINT0 0
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200 | #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
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201 | #define PORT_PA16A_EIC_EXTINT0 (1u << 16)
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202 | #define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
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203 | #define MUX_PA00A_EIC_EXTINT0 0
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204 | #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
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205 | #define PORT_PA00A_EIC_EXTINT0 (1u << 0)
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206 | #define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
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207 | #define MUX_PA17A_EIC_EXTINT1 0
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208 | #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
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209 | #define PORT_PA17A_EIC_EXTINT1 (1u << 17)
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210 | #define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
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211 | #define MUX_PA01A_EIC_EXTINT1 0
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212 | #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
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213 | #define PORT_PA01A_EIC_EXTINT1 (1u << 1)
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214 | #define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
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215 | #define MUX_PA18A_EIC_EXTINT2 0
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216 | #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
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217 | #define PORT_PA18A_EIC_EXTINT2 (1u << 18)
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218 | #define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
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219 | #define MUX_PA02A_EIC_EXTINT2 0
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220 | #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
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221 | #define PORT_PA02A_EIC_EXTINT2 (1u << 2)
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222 | #define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
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223 | #define MUX_PB02A_EIC_EXTINT2 0
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224 | #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
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225 | #define PORT_PB02A_EIC_EXTINT2 (1u << 2)
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226 | #define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
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227 | #define MUX_PA03A_EIC_EXTINT3 0
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228 | #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
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229 | #define PORT_PA03A_EIC_EXTINT3 (1u << 3)
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230 | #define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
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231 | #define MUX_PA19A_EIC_EXTINT3 0
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232 | #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
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233 | #define PORT_PA19A_EIC_EXTINT3 (1u << 19)
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234 | #define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
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235 | #define MUX_PB03A_EIC_EXTINT3 0
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236 | #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
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237 | #define PORT_PB03A_EIC_EXTINT3 (1u << 3)
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238 | #define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
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239 | #define MUX_PA04A_EIC_EXTINT4 0
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240 | #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
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241 | #define PORT_PA04A_EIC_EXTINT4 (1u << 4)
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242 | #define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
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243 | #define MUX_PA20A_EIC_EXTINT4 0
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244 | #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
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245 | #define PORT_PA20A_EIC_EXTINT4 (1u << 20)
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246 | #define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
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247 | #define MUX_PA05A_EIC_EXTINT5 0
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248 | #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
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249 | #define PORT_PA05A_EIC_EXTINT5 (1u << 5)
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250 | #define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
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251 | #define MUX_PA21A_EIC_EXTINT5 0
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252 | #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
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253 | #define PORT_PA21A_EIC_EXTINT5 (1u << 21)
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254 | #define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
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255 | #define MUX_PA06A_EIC_EXTINT6 0
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256 | #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
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257 | #define PORT_PA06A_EIC_EXTINT6 (1u << 6)
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258 | #define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
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259 | #define MUX_PA22A_EIC_EXTINT6 0
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260 | #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
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261 | #define PORT_PA22A_EIC_EXTINT6 (1u << 22)
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262 | #define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
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263 | #define MUX_PB22A_EIC_EXTINT6 0
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264 | #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
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265 | #define PORT_PB22A_EIC_EXTINT6 (1u << 22)
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266 | #define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
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267 | #define MUX_PA07A_EIC_EXTINT7 0
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268 | #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
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269 | #define PORT_PA07A_EIC_EXTINT7 (1u << 7)
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270 | #define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
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271 | #define MUX_PA23A_EIC_EXTINT7 0
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272 | #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
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273 | #define PORT_PA23A_EIC_EXTINT7 (1u << 23)
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274 | #define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
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275 | #define MUX_PB23A_EIC_EXTINT7 0
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276 | #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
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277 | #define PORT_PB23A_EIC_EXTINT7 (1u << 23)
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278 | #define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
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279 | #define MUX_PA28A_EIC_EXTINT8 0
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280 | #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
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281 | #define PORT_PA28A_EIC_EXTINT8 (1u << 28)
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282 | #define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
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283 | #define MUX_PB08A_EIC_EXTINT8 0
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284 | #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
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285 | #define PORT_PB08A_EIC_EXTINT8 (1u << 8)
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286 | #define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
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287 | #define MUX_PA09A_EIC_EXTINT9 0
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288 | #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
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289 | #define PORT_PA09A_EIC_EXTINT9 (1u << 9)
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290 | #define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
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291 | #define MUX_PB09A_EIC_EXTINT9 0
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292 | #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
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293 | #define PORT_PB09A_EIC_EXTINT9 (1u << 9)
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294 | #define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
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295 | #define MUX_PA10A_EIC_EXTINT10 0
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296 | #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
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297 | #define PORT_PA10A_EIC_EXTINT10 (1u << 10)
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298 | #define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
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299 | #define MUX_PA30A_EIC_EXTINT10 0
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300 | #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
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301 | #define PORT_PA30A_EIC_EXTINT10 (1u << 30)
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302 | #define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
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303 | #define MUX_PB10A_EIC_EXTINT10 0
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304 | #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
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305 | #define PORT_PB10A_EIC_EXTINT10 (1u << 10)
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306 | #define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
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307 | #define MUX_PA18A_EIC_EXTINT10 0
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308 | #define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
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309 | #define PORT_PA18A_EIC_EXTINT10 (1u << 18)
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310 | #define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
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311 | #define MUX_PA11A_EIC_EXTINT11 0
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312 | #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
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313 | #define PORT_PA11A_EIC_EXTINT11 (1u << 11)
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314 | #define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
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315 | #define MUX_PA31A_EIC_EXTINT11 0
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316 | #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
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317 | #define PORT_PA31A_EIC_EXTINT11 (1u << 31)
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318 | #define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
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319 | #define MUX_PB11A_EIC_EXTINT11 0
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320 | #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
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321 | #define PORT_PB11A_EIC_EXTINT11 (1u << 11)
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322 | #define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
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323 | #define MUX_PA12A_EIC_EXTINT12 0
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324 | #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
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325 | #define PORT_PA12A_EIC_EXTINT12 (1u << 12)
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326 | #define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
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327 | #define MUX_PA24A_EIC_EXTINT12 0
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328 | #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
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329 | #define PORT_PA24A_EIC_EXTINT12 (1u << 24)
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330 | #define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
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331 | #define MUX_PA13A_EIC_EXTINT13 0
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332 | #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
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333 | #define PORT_PA13A_EIC_EXTINT13 (1u << 13)
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334 | #define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
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335 | #define MUX_PA25A_EIC_EXTINT13 0
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336 | #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
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337 | #define PORT_PA25A_EIC_EXTINT13 (1u << 25)
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338 | #define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
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339 | #define MUX_PA14A_EIC_EXTINT14 0
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340 | #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
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341 | #define PORT_PA14A_EIC_EXTINT14 (1u << 14)
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342 | #define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
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343 | #define MUX_PA15A_EIC_EXTINT15 0
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344 | #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
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345 | #define PORT_PA15A_EIC_EXTINT15 (1u << 15)
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346 | #define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
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347 | #define MUX_PA27A_EIC_EXTINT15 0
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348 | #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
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349 | #define PORT_PA27A_EIC_EXTINT15 (1u << 27)
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350 | #define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
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351 | #define MUX_PA12A_EIC_EXTINT17 0
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352 | #define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
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353 | #define PORT_PA12A_EIC_EXTINT17 (1u << 12)
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354 | #define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
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355 | #define MUX_PA08A_EIC_NMI 0
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356 | #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
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357 | #define PORT_PA08A_EIC_NMI (1u << 8)
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358 | /* ========== PORT definition for USB peripheral ========== */
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359 | #define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
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360 | #define MUX_PA24G_USB_DM 6
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361 | #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
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362 | #define PORT_PA24G_USB_DM (1u << 24)
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363 | #define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
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364 | #define MUX_PA25G_USB_DP 6
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365 | #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
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366 | #define PORT_PA25G_USB_DP (1u << 25)
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367 | #define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
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368 | #define MUX_PA23G_USB_SOF_1KHZ 6
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369 | #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
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370 | #define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
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371 | /* ========== PORT definition for SERCOM0 peripheral ========== */
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372 | #define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
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373 | #define MUX_PA04D_SERCOM0_PAD0 3
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374 | #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
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375 | #define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
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376 | #define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
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377 | #define MUX_PA08C_SERCOM0_PAD0 2
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378 | #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
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379 | #define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
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380 | #define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
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381 | #define MUX_PA13A_SERCOM0_PAD0 0
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382 | #define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
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383 | #define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
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384 | #define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
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385 | #define MUX_PA05D_SERCOM0_PAD1 3
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386 | #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
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387 | #define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
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388 | #define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
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389 | #define MUX_PA09C_SERCOM0_PAD1 2
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390 | #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
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391 | #define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
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392 | #define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
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393 | #define MUX_PA06D_SERCOM0_PAD2 3
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394 | #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
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395 | #define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
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396 | #define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
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397 | #define MUX_PA10C_SERCOM0_PAD2 2
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398 | #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
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399 | #define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
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400 | #define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
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401 | #define MUX_PA07D_SERCOM0_PAD3 3
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402 | #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
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403 | #define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
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404 | #define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
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405 | #define MUX_PA11C_SERCOM0_PAD3 2
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406 | #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
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407 | #define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
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408 | /* ========== PORT definition for SERCOM1 peripheral ========== */
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409 | #define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
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410 | #define MUX_PA16C_SERCOM1_PAD0 2
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411 | #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
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412 | #define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
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413 | #define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
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414 | #define MUX_PA00D_SERCOM1_PAD0 3
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415 | #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
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416 | #define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
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417 | #define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
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418 | #define MUX_PA17C_SERCOM1_PAD1 2
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419 | #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
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420 | #define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
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421 | #define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
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422 | #define MUX_PA01D_SERCOM1_PAD1 3
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423 | #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
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424 | #define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
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425 | #define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
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426 | #define MUX_PA30D_SERCOM1_PAD2 3
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427 | #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
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428 | #define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
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429 | #define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
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430 | #define MUX_PA18C_SERCOM1_PAD2 2
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431 | #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
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432 | #define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
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433 | #define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
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434 | #define MUX_PA31D_SERCOM1_PAD3 3
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435 | #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
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436 | #define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
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437 | #define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
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438 | #define MUX_PA19C_SERCOM1_PAD3 2
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439 | #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
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440 | #define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
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441 | /* ========== PORT definition for SERCOM2 peripheral ========== */
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442 | #define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
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443 | #define MUX_PA08D_SERCOM2_PAD0 3
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444 | #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
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445 | #define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
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446 | #define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
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447 | #define MUX_PA12C_SERCOM2_PAD0 2
|
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448 | #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
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449 | #define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
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450 | #define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
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451 | #define MUX_PA15A_SERCOM2_PAD0 0
|
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452 | #define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
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453 | #define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
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454 | #define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
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455 | #define MUX_PA09D_SERCOM2_PAD1 3
|
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456 | #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
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457 | #define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
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458 | #define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
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459 | #define MUX_PA13C_SERCOM2_PAD1 2
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460 | #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
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461 | #define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
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462 | #define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
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463 | #define MUX_PA10D_SERCOM2_PAD2 3
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464 | #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
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465 | #define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
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466 | #define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
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467 | #define MUX_PA14C_SERCOM2_PAD2 2
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468 | #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
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469 | #define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
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470 | #define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
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471 | #define MUX_PA11D_SERCOM2_PAD3 3
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472 | #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
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473 | #define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
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474 | #define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
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475 | #define MUX_PA15C_SERCOM2_PAD3 2
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476 | #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
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477 | #define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
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478 | /* ========== PORT definition for SERCOM3 peripheral ========== */
|
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479 | #define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
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480 | #define MUX_PA16D_SERCOM3_PAD0 3
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481 | #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
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482 | #define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
|
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483 | #define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
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484 | #define MUX_PA22C_SERCOM3_PAD0 2
|
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485 | #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
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486 | #define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
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487 | #define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
|
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488 | #define MUX_PA27F_SERCOM3_PAD0 5
|
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489 | #define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
|
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490 | #define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
|
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491 | #define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
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492 | #define MUX_PA17D_SERCOM3_PAD1 3
|
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493 | #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
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494 | #define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
|
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495 | #define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
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496 | #define MUX_PA23C_SERCOM3_PAD1 2
|
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497 | #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
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498 | #define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
|
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499 | #define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
|
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500 | #define MUX_PA28F_SERCOM3_PAD1 5
|
---|
501 | #define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
|
---|
502 | #define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
|
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503 | #define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
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504 | #define MUX_PA18D_SERCOM3_PAD2 3
|
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505 | #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
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506 | #define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
|
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507 | #define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
---|
508 | #define MUX_PA20D_SERCOM3_PAD2 3
|
---|
509 | #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
---|
510 | #define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
|
---|
511 | #define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
---|
512 | #define MUX_PA24C_SERCOM3_PAD2 2
|
---|
513 | #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
---|
514 | #define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
|
---|
515 | #define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
---|
516 | #define MUX_PA19D_SERCOM3_PAD3 3
|
---|
517 | #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
---|
518 | #define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
|
---|
519 | #define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
---|
520 | #define MUX_PA21D_SERCOM3_PAD3 3
|
---|
521 | #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
---|
522 | #define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
|
---|
523 | #define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
---|
524 | #define MUX_PA25C_SERCOM3_PAD3 2
|
---|
525 | #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
---|
526 | #define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
|
---|
527 | /* ========== PORT definition for SERCOM4 peripheral ========== */
|
---|
528 | #define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
---|
529 | #define MUX_PA12D_SERCOM4_PAD0 3
|
---|
530 | #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
---|
531 | #define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
|
---|
532 | #define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
---|
533 | #define MUX_PB08D_SERCOM4_PAD0 3
|
---|
534 | #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
---|
535 | #define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
|
---|
536 | #define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
---|
537 | #define MUX_PA13D_SERCOM4_PAD1 3
|
---|
538 | #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
---|
539 | #define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
|
---|
540 | #define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
---|
541 | #define MUX_PB09D_SERCOM4_PAD1 3
|
---|
542 | #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
---|
543 | #define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
|
---|
544 | #define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
---|
545 | #define MUX_PA14D_SERCOM4_PAD2 3
|
---|
546 | #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
---|
547 | #define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
|
---|
548 | #define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
|
---|
549 | #define MUX_PB10D_SERCOM4_PAD2 3
|
---|
550 | #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
|
---|
551 | #define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
|
---|
552 | #define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
---|
553 | #define MUX_PA15D_SERCOM4_PAD3 3
|
---|
554 | #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
---|
555 | #define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
|
---|
556 | #define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
|
---|
557 | #define MUX_PB11D_SERCOM4_PAD3 3
|
---|
558 | #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
|
---|
559 | #define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
|
---|
560 | /* ========== PORT definition for SERCOM5 peripheral ========== */
|
---|
561 | #define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
---|
562 | #define MUX_PA22D_SERCOM5_PAD0 3
|
---|
563 | #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
---|
564 | #define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
|
---|
565 | #define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
---|
566 | #define MUX_PB02D_SERCOM5_PAD0 3
|
---|
567 | #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
---|
568 | #define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
|
---|
569 | #define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
---|
570 | #define MUX_PA23D_SERCOM5_PAD1 3
|
---|
571 | #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
---|
572 | #define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
|
---|
573 | #define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
---|
574 | #define MUX_PB03D_SERCOM5_PAD1 3
|
---|
575 | #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
---|
576 | #define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
|
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577 | #define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
---|
578 | #define MUX_PA24D_SERCOM5_PAD2 3
|
---|
579 | #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
---|
580 | #define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
|
---|
581 | #define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
|
---|
582 | #define MUX_PB22D_SERCOM5_PAD2 3
|
---|
583 | #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
|
---|
584 | #define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
|
---|
585 | #define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
---|
586 | #define MUX_PA20C_SERCOM5_PAD2 2
|
---|
587 | #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
---|
588 | #define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
|
---|
589 | #define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
---|
590 | #define MUX_PA25D_SERCOM5_PAD3 3
|
---|
591 | #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
---|
592 | #define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
|
---|
593 | #define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
|
---|
594 | #define MUX_PB23D_SERCOM5_PAD3 3
|
---|
595 | #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
|
---|
596 | #define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
|
---|
597 | #define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
---|
598 | #define MUX_PA21C_SERCOM5_PAD3 2
|
---|
599 | #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
---|
600 | #define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
|
---|
601 | /* ========== PORT definition for TCC0 peripheral ========== */
|
---|
602 | #define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
---|
603 | #define MUX_PA04E_TCC0_WO0 4
|
---|
604 | #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
---|
605 | #define PORT_PA04E_TCC0_WO0 (1u << 4)
|
---|
606 | #define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
---|
607 | #define MUX_PA08E_TCC0_WO0 4
|
---|
608 | #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
---|
609 | #define PORT_PA08E_TCC0_WO0 (1u << 8)
|
---|
610 | #define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
|
---|
611 | #define MUX_PA16F_TCC0_WO0 5
|
---|
612 | #define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
|
---|
613 | #define PORT_PA16F_TCC0_WO0 (1u << 16)
|
---|
614 | #define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
---|
615 | #define MUX_PA05E_TCC0_WO1 4
|
---|
616 | #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
---|
617 | #define PORT_PA05E_TCC0_WO1 (1u << 5)
|
---|
618 | #define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
---|
619 | #define MUX_PA09E_TCC0_WO1 4
|
---|
620 | #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
---|
621 | #define PORT_PA09E_TCC0_WO1 (1u << 9)
|
---|
622 | #define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
|
---|
623 | #define MUX_PA17F_TCC0_WO1 5
|
---|
624 | #define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
|
---|
625 | #define PORT_PA17F_TCC0_WO1 (1u << 17)
|
---|
626 | #define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
---|
627 | #define MUX_PA10F_TCC0_WO2 5
|
---|
628 | #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
---|
629 | #define PORT_PA10F_TCC0_WO2 (1u << 10)
|
---|
630 | #define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
---|
631 | #define MUX_PA18F_TCC0_WO2 5
|
---|
632 | #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
---|
633 | #define PORT_PA18F_TCC0_WO2 (1u << 18)
|
---|
634 | #define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
---|
635 | #define MUX_PA11F_TCC0_WO3 5
|
---|
636 | #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
---|
637 | #define PORT_PA11F_TCC0_WO3 (1u << 11)
|
---|
638 | #define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
---|
639 | #define MUX_PA19F_TCC0_WO3 5
|
---|
640 | #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
---|
641 | #define PORT_PA19F_TCC0_WO3 (1u << 19)
|
---|
642 | #define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
---|
643 | #define MUX_PA14F_TCC0_WO4 5
|
---|
644 | #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
---|
645 | #define PORT_PA14F_TCC0_WO4 (1u << 14)
|
---|
646 | #define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
---|
647 | #define MUX_PA22F_TCC0_WO4 5
|
---|
648 | #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
---|
649 | #define PORT_PA22F_TCC0_WO4 (1u << 22)
|
---|
650 | #define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
|
---|
651 | #define MUX_PB10F_TCC0_WO4 5
|
---|
652 | #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
|
---|
653 | #define PORT_PB10F_TCC0_WO4 (1u << 10)
|
---|
654 | #define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
---|
655 | #define MUX_PA15F_TCC0_WO5 5
|
---|
656 | #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
---|
657 | #define PORT_PA15F_TCC0_WO5 (1u << 15)
|
---|
658 | #define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
---|
659 | #define MUX_PA23F_TCC0_WO5 5
|
---|
660 | #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
---|
661 | #define PORT_PA23F_TCC0_WO5 (1u << 23)
|
---|
662 | #define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
|
---|
663 | #define MUX_PB11F_TCC0_WO5 5
|
---|
664 | #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
|
---|
665 | #define PORT_PB11F_TCC0_WO5 (1u << 11)
|
---|
666 | #define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
---|
667 | #define MUX_PA12F_TCC0_WO6 5
|
---|
668 | #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
---|
669 | #define PORT_PA12F_TCC0_WO6 (1u << 12)
|
---|
670 | #define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
---|
671 | #define MUX_PA20F_TCC0_WO6 5
|
---|
672 | #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
---|
673 | #define PORT_PA20F_TCC0_WO6 (1u << 20)
|
---|
674 | #define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
---|
675 | #define MUX_PA16F_TCC0_WO6 5
|
---|
676 | #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
---|
677 | #define PORT_PA16F_TCC0_WO6 (1u << 16)
|
---|
678 | #define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
---|
679 | #define MUX_PA13F_TCC0_WO7 5
|
---|
680 | #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
---|
681 | #define PORT_PA13F_TCC0_WO7 (1u << 13)
|
---|
682 | #define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
---|
683 | #define MUX_PA21F_TCC0_WO7 5
|
---|
684 | #define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
---|
685 | #define PORT_PA21F_TCC0_WO7 (1u << 21)
|
---|
686 | #define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
---|
687 | #define MUX_PA17F_TCC0_WO7 5
|
---|
688 | #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
---|
689 | #define PORT_PA17F_TCC0_WO7 (1u << 17)
|
---|
690 | /* ========== PORT definition for TCC1 peripheral ========== */
|
---|
691 | #define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
---|
692 | #define MUX_PA06E_TCC1_WO0 4
|
---|
693 | #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
---|
694 | #define PORT_PA06E_TCC1_WO0 (1u << 6)
|
---|
695 | #define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
---|
696 | #define MUX_PA10E_TCC1_WO0 4
|
---|
697 | #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
---|
698 | #define PORT_PA10E_TCC1_WO0 (1u << 10)
|
---|
699 | #define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
---|
700 | #define MUX_PA30E_TCC1_WO0 4
|
---|
701 | #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
---|
702 | #define PORT_PA30E_TCC1_WO0 (1u << 30)
|
---|
703 | #define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
---|
704 | #define MUX_PA07E_TCC1_WO1 4
|
---|
705 | #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
---|
706 | #define PORT_PA07E_TCC1_WO1 (1u << 7)
|
---|
707 | #define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
---|
708 | #define MUX_PA11E_TCC1_WO1 4
|
---|
709 | #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
---|
710 | #define PORT_PA11E_TCC1_WO1 (1u << 11)
|
---|
711 | #define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
---|
712 | #define MUX_PA31E_TCC1_WO1 4
|
---|
713 | #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
---|
714 | #define PORT_PA31E_TCC1_WO1 (1u << 31)
|
---|
715 | #define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
---|
716 | #define MUX_PA08F_TCC1_WO2 5
|
---|
717 | #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
---|
718 | #define PORT_PA08F_TCC1_WO2 (1u << 8)
|
---|
719 | #define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
---|
720 | #define MUX_PA24F_TCC1_WO2 5
|
---|
721 | #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
---|
722 | #define PORT_PA24F_TCC1_WO2 (1u << 24)
|
---|
723 | #define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
---|
724 | #define MUX_PA09F_TCC1_WO3 5
|
---|
725 | #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
---|
726 | #define PORT_PA09F_TCC1_WO3 (1u << 9)
|
---|
727 | #define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
---|
728 | #define MUX_PA25F_TCC1_WO3 5
|
---|
729 | #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
---|
730 | #define PORT_PA25F_TCC1_WO3 (1u << 25)
|
---|
731 | /* ========== PORT definition for TCC2 peripheral ========== */
|
---|
732 | #define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
---|
733 | #define MUX_PA12E_TCC2_WO0 4
|
---|
734 | #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
---|
735 | #define PORT_PA12E_TCC2_WO0 (1u << 12)
|
---|
736 | #define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
---|
737 | #define MUX_PA16E_TCC2_WO0 4
|
---|
738 | #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
---|
739 | #define PORT_PA16E_TCC2_WO0 (1u << 16)
|
---|
740 | #define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
---|
741 | #define MUX_PA00E_TCC2_WO0 4
|
---|
742 | #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
---|
743 | #define PORT_PA00E_TCC2_WO0 (1u << 0)
|
---|
744 | #define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
---|
745 | #define MUX_PA13E_TCC2_WO1 4
|
---|
746 | #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
---|
747 | #define PORT_PA13E_TCC2_WO1 (1u << 13)
|
---|
748 | #define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
---|
749 | #define MUX_PA17E_TCC2_WO1 4
|
---|
750 | #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
---|
751 | #define PORT_PA17E_TCC2_WO1 (1u << 17)
|
---|
752 | #define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
---|
753 | #define MUX_PA01E_TCC2_WO1 4
|
---|
754 | #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
---|
755 | #define PORT_PA01E_TCC2_WO1 (1u << 1)
|
---|
756 | /* ========== PORT definition for TC3 peripheral ========== */
|
---|
757 | #define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
|
---|
758 | #define MUX_PA18E_TC3_WO0 4
|
---|
759 | #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
---|
760 | #define PORT_PA18E_TC3_WO0 (1u << 18)
|
---|
761 | #define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
|
---|
762 | #define MUX_PA14E_TC3_WO0 4
|
---|
763 | #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
---|
764 | #define PORT_PA14E_TC3_WO0 (1u << 14)
|
---|
765 | #define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
|
---|
766 | #define MUX_PA19E_TC3_WO1 4
|
---|
767 | #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
---|
768 | #define PORT_PA19E_TC3_WO1 (1u << 19)
|
---|
769 | #define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
|
---|
770 | #define MUX_PA15E_TC3_WO1 4
|
---|
771 | #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
---|
772 | #define PORT_PA15E_TC3_WO1 (1u << 15)
|
---|
773 | /* ========== PORT definition for TC4 peripheral ========== */
|
---|
774 | #define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
|
---|
775 | #define MUX_PA22E_TC4_WO0 4
|
---|
776 | #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
---|
777 | #define PORT_PA22E_TC4_WO0 (1u << 22)
|
---|
778 | #define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
|
---|
779 | #define MUX_PB08E_TC4_WO0 4
|
---|
780 | #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
---|
781 | #define PORT_PB08E_TC4_WO0 (1u << 8)
|
---|
782 | #define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
|
---|
783 | #define MUX_PA23E_TC4_WO1 4
|
---|
784 | #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
---|
785 | #define PORT_PA23E_TC4_WO1 (1u << 23)
|
---|
786 | #define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
|
---|
787 | #define MUX_PB09E_TC4_WO1 4
|
---|
788 | #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
---|
789 | #define PORT_PB09E_TC4_WO1 (1u << 9)
|
---|
790 | /* ========== PORT definition for TC5 peripheral ========== */
|
---|
791 | #define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
|
---|
792 | #define MUX_PA24E_TC5_WO0 4
|
---|
793 | #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
---|
794 | #define PORT_PA24E_TC5_WO0 (1u << 24)
|
---|
795 | #define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
|
---|
796 | #define MUX_PB10E_TC5_WO0 4
|
---|
797 | #define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
|
---|
798 | #define PORT_PB10E_TC5_WO0 (1u << 10)
|
---|
799 | #define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
|
---|
800 | #define MUX_PA25E_TC5_WO1 4
|
---|
801 | #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
---|
802 | #define PORT_PA25E_TC5_WO1 (1u << 25)
|
---|
803 | #define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
|
---|
804 | #define MUX_PB11E_TC5_WO1 4
|
---|
805 | #define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
|
---|
806 | #define PORT_PB11E_TC5_WO1 (1u << 11)
|
---|
807 | /* ========== PORT definition for ADC peripheral ========== */
|
---|
808 | #define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
|
---|
809 | #define MUX_PA02B_ADC_AIN0 1
|
---|
810 | #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
---|
811 | #define PORT_PA02B_ADC_AIN0 (1u << 2)
|
---|
812 | #define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
|
---|
813 | #define MUX_PA03B_ADC_AIN1 1
|
---|
814 | #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
---|
815 | #define PORT_PA03B_ADC_AIN1 (1u << 3)
|
---|
816 | #define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
|
---|
817 | #define MUX_PB08B_ADC_AIN2 1
|
---|
818 | #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
---|
819 | #define PORT_PB08B_ADC_AIN2 (1u << 8)
|
---|
820 | #define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
|
---|
821 | #define MUX_PB09B_ADC_AIN3 1
|
---|
822 | #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
---|
823 | #define PORT_PB09B_ADC_AIN3 (1u << 9)
|
---|
824 | #define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
|
---|
825 | #define MUX_PA04B_ADC_AIN4 1
|
---|
826 | #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
---|
827 | #define PORT_PA04B_ADC_AIN4 (1u << 4)
|
---|
828 | #define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
|
---|
829 | #define MUX_PA05B_ADC_AIN5 1
|
---|
830 | #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
---|
831 | #define PORT_PA05B_ADC_AIN5 (1u << 5)
|
---|
832 | #define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
|
---|
833 | #define MUX_PA06B_ADC_AIN6 1
|
---|
834 | #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
---|
835 | #define PORT_PA06B_ADC_AIN6 (1u << 6)
|
---|
836 | #define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
|
---|
837 | #define MUX_PA07B_ADC_AIN7 1
|
---|
838 | #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
---|
839 | #define PORT_PA07B_ADC_AIN7 (1u << 7)
|
---|
840 | #define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
|
---|
841 | #define MUX_PB02B_ADC_AIN10 1
|
---|
842 | #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
---|
843 | #define PORT_PB02B_ADC_AIN10 (1u << 2)
|
---|
844 | #define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
|
---|
845 | #define MUX_PB03B_ADC_AIN11 1
|
---|
846 | #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
---|
847 | #define PORT_PB03B_ADC_AIN11 (1u << 3)
|
---|
848 | #define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
|
---|
849 | #define MUX_PA08B_ADC_AIN16 1
|
---|
850 | #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
---|
851 | #define PORT_PA08B_ADC_AIN16 (1u << 8)
|
---|
852 | #define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
|
---|
853 | #define MUX_PA09B_ADC_AIN17 1
|
---|
854 | #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
---|
855 | #define PORT_PA09B_ADC_AIN17 (1u << 9)
|
---|
856 | #define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
|
---|
857 | #define MUX_PA10B_ADC_AIN18 1
|
---|
858 | #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
---|
859 | #define PORT_PA10B_ADC_AIN18 (1u << 10)
|
---|
860 | #define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
|
---|
861 | #define MUX_PA11B_ADC_AIN19 1
|
---|
862 | #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
---|
863 | #define PORT_PA11B_ADC_AIN19 (1u << 11)
|
---|
864 | #define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
|
---|
865 | #define MUX_PA04B_ADC_VREFP 1
|
---|
866 | #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
---|
867 | #define PORT_PA04B_ADC_VREFP (1u << 4)
|
---|
868 | /* ========== PORT definition for AC peripheral ========== */
|
---|
869 | #define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
|
---|
870 | #define MUX_PA04B_AC_AIN0 1
|
---|
871 | #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
---|
872 | #define PORT_PA04B_AC_AIN0 (1u << 4)
|
---|
873 | #define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
|
---|
874 | #define MUX_PA05B_AC_AIN1 1
|
---|
875 | #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
---|
876 | #define PORT_PA05B_AC_AIN1 (1u << 5)
|
---|
877 | #define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
|
---|
878 | #define MUX_PA06B_AC_AIN2 1
|
---|
879 | #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
---|
880 | #define PORT_PA06B_AC_AIN2 (1u << 6)
|
---|
881 | #define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
|
---|
882 | #define MUX_PA07B_AC_AIN3 1
|
---|
883 | #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
---|
884 | #define PORT_PA07B_AC_AIN3 (1u << 7)
|
---|
885 | #define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
|
---|
886 | #define MUX_PA12H_AC_CMP0 7
|
---|
887 | #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
---|
888 | #define PORT_PA12H_AC_CMP0 (1u << 12)
|
---|
889 | #define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
|
---|
890 | #define MUX_PA18H_AC_CMP0 7
|
---|
891 | #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
---|
892 | #define PORT_PA18H_AC_CMP0 (1u << 18)
|
---|
893 | #define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
|
---|
894 | #define MUX_PA13H_AC_CMP1 7
|
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895 | #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
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896 | #define PORT_PA13H_AC_CMP1 (1u << 13)
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897 | #define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
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898 | #define MUX_PA19H_AC_CMP1 7
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899 | #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
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900 | #define PORT_PA19H_AC_CMP1 (1u << 19)
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901 | /* ========== PORT definition for DAC peripheral ========== */
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902 | #define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
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903 | #define MUX_PA02B_DAC_VOUT 1
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904 | #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
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905 | #define PORT_PA02B_DAC_VOUT (1u << 2)
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906 | #define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
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907 | #define MUX_PA03B_DAC_VREFP 1
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908 | #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
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909 | #define PORT_PA03B_DAC_VREFP (1u << 3)
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910 | /* ========== PORT definition for I2S peripheral ========== */
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911 | #define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
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912 | #define MUX_PA11G_I2S_FS0 6
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913 | #define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
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914 | #define PORT_PA11G_I2S_FS0 (1u << 11)
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915 | #define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
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916 | #define MUX_PA21G_I2S_FS0 6
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917 | #define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
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918 | #define PORT_PA21G_I2S_FS0 (1u << 21)
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919 | #define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
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920 | #define MUX_PA09G_I2S_MCK0 6
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921 | #define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
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922 | #define PORT_PA09G_I2S_MCK0 (1u << 9)
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923 | #define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
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924 | #define MUX_PB10G_I2S_MCK1 6
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925 | #define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
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926 | #define PORT_PB10G_I2S_MCK1 (1u << 10)
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927 | #define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
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928 | #define MUX_PA10G_I2S_SCK0 6
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929 | #define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
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930 | #define PORT_PA10G_I2S_SCK0 (1u << 10)
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931 | #define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
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932 | #define MUX_PA20G_I2S_SCK0 6
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933 | #define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
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934 | #define PORT_PA20G_I2S_SCK0 (1u << 20)
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935 | #define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
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936 | #define MUX_PB11G_I2S_SCK1 6
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937 | #define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
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938 | #define PORT_PB11G_I2S_SCK1 (1u << 11)
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939 | #define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
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940 | #define MUX_PA07G_I2S_SD0 6
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941 | #define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
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942 | #define PORT_PA07G_I2S_SD0 (1u << 7)
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943 | #define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
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944 | #define MUX_PA19G_I2S_SD0 6
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945 | #define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
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946 | #define PORT_PA19G_I2S_SD0 (1u << 19)
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947 | #define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
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948 | #define MUX_PA08G_I2S_SD1 6
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949 | #define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
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950 | #define PORT_PA08G_I2S_SD1 (1u << 8)
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951 |
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952 | #endif /* _SAMD21G17A_PIO_ */
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