source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/pio/samd21e15a.h@ 136

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1/**
2 * \file
3 *
4 * \brief Peripheral I/O description for SAMD21E15A
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21E15A_PIO_
45#define _SAMD21E15A_PIO_
46
47#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
48#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
49#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
50#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
51#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
52#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
53#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
54#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
55#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
56#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
57#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
58#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
59#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
60#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
61#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
62#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
63#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
64#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
65#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
66#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
67#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
68#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
69#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
70#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
71#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
72#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
73#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
74#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
75#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
76#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
77#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
78#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
79#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
80#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
81#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
82#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
83#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
84#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
85#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
86#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
87#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
88#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
89#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
90#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
91#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
92#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
93#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
94#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
95#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
96#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
97#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
98#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
99/* ========== PORT definition for CORE peripheral ========== */
100#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
101#define MUX_PA30G_CORE_SWCLK 6
102#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
103#define PORT_PA30G_CORE_SWCLK (1u << 30)
104/* ========== PORT definition for GCLK peripheral ========== */
105#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
106#define MUX_PA14H_GCLK_IO0 7
107#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
108#define PORT_PA14H_GCLK_IO0 (1u << 14)
109#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
110#define MUX_PA27H_GCLK_IO0 7
111#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
112#define PORT_PA27H_GCLK_IO0 (1u << 27)
113#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
114#define MUX_PA28H_GCLK_IO0 7
115#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
116#define PORT_PA28H_GCLK_IO0 (1u << 28)
117#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
118#define MUX_PA30H_GCLK_IO0 7
119#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
120#define PORT_PA30H_GCLK_IO0 (1u << 30)
121#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
122#define MUX_PA15H_GCLK_IO1 7
123#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
124#define PORT_PA15H_GCLK_IO1 (1u << 15)
125#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
126#define MUX_PA16H_GCLK_IO2 7
127#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
128#define PORT_PA16H_GCLK_IO2 (1u << 16)
129#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
130#define MUX_PA17H_GCLK_IO3 7
131#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
132#define PORT_PA17H_GCLK_IO3 (1u << 17)
133#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
134#define MUX_PA10H_GCLK_IO4 7
135#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
136#define PORT_PA10H_GCLK_IO4 (1u << 10)
137#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
138#define MUX_PA11H_GCLK_IO5 7
139#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
140#define PORT_PA11H_GCLK_IO5 (1u << 11)
141#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
142#define MUX_PA22H_GCLK_IO6 7
143#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
144#define PORT_PA22H_GCLK_IO6 (1u << 22)
145#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
146#define MUX_PA23H_GCLK_IO7 7
147#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
148#define PORT_PA23H_GCLK_IO7 (1u << 23)
149/* ========== PORT definition for EIC peripheral ========== */
150#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
151#define MUX_PA16A_EIC_EXTINT0 0
152#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
153#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
154#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
155#define MUX_PA00A_EIC_EXTINT0 0
156#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
157#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
158#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
159#define MUX_PA17A_EIC_EXTINT1 0
160#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
161#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
162#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
163#define MUX_PA01A_EIC_EXTINT1 0
164#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
165#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
166#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
167#define MUX_PA18A_EIC_EXTINT2 0
168#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
169#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
170#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
171#define MUX_PA02A_EIC_EXTINT2 0
172#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
173#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
174#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
175#define MUX_PA03A_EIC_EXTINT3 0
176#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
177#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
178#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
179#define MUX_PA19A_EIC_EXTINT3 0
180#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
181#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
182#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
183#define MUX_PA04A_EIC_EXTINT4 0
184#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
185#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
186#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
187#define MUX_PA05A_EIC_EXTINT5 0
188#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
189#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
190#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
191#define MUX_PA06A_EIC_EXTINT6 0
192#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
193#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
194#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
195#define MUX_PA22A_EIC_EXTINT6 0
196#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
197#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
198#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
199#define MUX_PA07A_EIC_EXTINT7 0
200#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
201#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
202#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
203#define MUX_PA23A_EIC_EXTINT7 0
204#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
205#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
206#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
207#define MUX_PA28A_EIC_EXTINT8 0
208#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
209#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
210#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
211#define MUX_PA09A_EIC_EXTINT9 0
212#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
213#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
214#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
215#define MUX_PA10A_EIC_EXTINT10 0
216#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
217#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
218#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
219#define MUX_PA30A_EIC_EXTINT10 0
220#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
221#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
222#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
223#define MUX_PA18A_EIC_EXTINT10 0
224#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
225#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
226#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
227#define MUX_PA11A_EIC_EXTINT11 0
228#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
229#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
230#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
231#define MUX_PA31A_EIC_EXTINT11 0
232#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
233#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
234#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
235#define MUX_PA24A_EIC_EXTINT12 0
236#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
237#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
238#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
239#define MUX_PA25A_EIC_EXTINT13 0
240#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
241#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
242#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
243#define MUX_PA14A_EIC_EXTINT14 0
244#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
245#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
246#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
247#define MUX_PA15A_EIC_EXTINT15 0
248#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
249#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
250#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
251#define MUX_PA27A_EIC_EXTINT15 0
252#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
253#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
254#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
255#define MUX_PA08A_EIC_NMI 0
256#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
257#define PORT_PA08A_EIC_NMI (1u << 8)
258/* ========== PORT definition for USB peripheral ========== */
259#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
260#define MUX_PA24G_USB_DM 6
261#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
262#define PORT_PA24G_USB_DM (1u << 24)
263#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
264#define MUX_PA25G_USB_DP 6
265#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
266#define PORT_PA25G_USB_DP (1u << 25)
267#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
268#define MUX_PA23G_USB_SOF_1KHZ 6
269#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
270#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
271/* ========== PORT definition for SERCOM0 peripheral ========== */
272#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
273#define MUX_PA04D_SERCOM0_PAD0 3
274#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
275#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
276#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
277#define MUX_PA08C_SERCOM0_PAD0 2
278#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
279#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
280#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
281#define MUX_PA05D_SERCOM0_PAD1 3
282#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
283#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
284#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
285#define MUX_PA09C_SERCOM0_PAD1 2
286#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
287#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
288#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
289#define MUX_PA06D_SERCOM0_PAD2 3
290#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
291#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
292#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
293#define MUX_PA10C_SERCOM0_PAD2 2
294#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
295#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
296#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
297#define MUX_PA07D_SERCOM0_PAD3 3
298#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
299#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
300#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
301#define MUX_PA11C_SERCOM0_PAD3 2
302#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
303#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
304/* ========== PORT definition for SERCOM1 peripheral ========== */
305#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
306#define MUX_PA16C_SERCOM1_PAD0 2
307#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
308#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
309#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
310#define MUX_PA00D_SERCOM1_PAD0 3
311#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
312#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
313#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
314#define MUX_PA17C_SERCOM1_PAD1 2
315#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
316#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
317#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
318#define MUX_PA01D_SERCOM1_PAD1 3
319#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
320#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
321#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
322#define MUX_PA30D_SERCOM1_PAD2 3
323#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
324#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
325#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
326#define MUX_PA18C_SERCOM1_PAD2 2
327#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
328#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
329#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
330#define MUX_PA31D_SERCOM1_PAD3 3
331#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
332#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
333#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
334#define MUX_PA19C_SERCOM1_PAD3 2
335#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
336#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
337/* ========== PORT definition for SERCOM2 peripheral ========== */
338#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
339#define MUX_PA08D_SERCOM2_PAD0 3
340#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
341#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
342#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
343#define MUX_PA15A_SERCOM2_PAD0 0
344#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
345#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
346#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
347#define MUX_PA09D_SERCOM2_PAD1 3
348#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
349#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
350#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
351#define MUX_PA10D_SERCOM2_PAD2 3
352#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
353#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
354#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
355#define MUX_PA14C_SERCOM2_PAD2 2
356#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
357#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
358#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
359#define MUX_PA11D_SERCOM2_PAD3 3
360#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
361#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
362#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
363#define MUX_PA15C_SERCOM2_PAD3 2
364#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
365#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
366/* ========== PORT definition for SERCOM3 peripheral ========== */
367#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
368#define MUX_PA16D_SERCOM3_PAD0 3
369#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
370#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
371#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
372#define MUX_PA22C_SERCOM3_PAD0 2
373#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
374#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
375#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
376#define MUX_PA27F_SERCOM3_PAD0 5
377#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
378#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
379#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
380#define MUX_PA17D_SERCOM3_PAD1 3
381#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
382#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
383#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
384#define MUX_PA23C_SERCOM3_PAD1 2
385#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
386#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
387#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
388#define MUX_PA28F_SERCOM3_PAD1 5
389#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
390#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
391#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
392#define MUX_PA18D_SERCOM3_PAD2 3
393#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
394#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
395#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
396#define MUX_PA24C_SERCOM3_PAD2 2
397#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
398#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
399#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
400#define MUX_PA19D_SERCOM3_PAD3 3
401#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
402#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
403#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
404#define MUX_PA25C_SERCOM3_PAD3 2
405#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
406#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
407/* ========== PORT definition for TCC0 peripheral ========== */
408#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
409#define MUX_PA04E_TCC0_WO0 4
410#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
411#define PORT_PA04E_TCC0_WO0 (1u << 4)
412#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
413#define MUX_PA08E_TCC0_WO0 4
414#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
415#define PORT_PA08E_TCC0_WO0 (1u << 8)
416#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
417#define MUX_PA16F_TCC0_WO0 5
418#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
419#define PORT_PA16F_TCC0_WO0 (1u << 16)
420#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
421#define MUX_PA05E_TCC0_WO1 4
422#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
423#define PORT_PA05E_TCC0_WO1 (1u << 5)
424#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
425#define MUX_PA09E_TCC0_WO1 4
426#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
427#define PORT_PA09E_TCC0_WO1 (1u << 9)
428#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
429#define MUX_PA17F_TCC0_WO1 5
430#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
431#define PORT_PA17F_TCC0_WO1 (1u << 17)
432#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
433#define MUX_PA10F_TCC0_WO2 5
434#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
435#define PORT_PA10F_TCC0_WO2 (1u << 10)
436#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
437#define MUX_PA18F_TCC0_WO2 5
438#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
439#define PORT_PA18F_TCC0_WO2 (1u << 18)
440#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
441#define MUX_PA11F_TCC0_WO3 5
442#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
443#define PORT_PA11F_TCC0_WO3 (1u << 11)
444#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
445#define MUX_PA19F_TCC0_WO3 5
446#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
447#define PORT_PA19F_TCC0_WO3 (1u << 19)
448#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
449#define MUX_PA14F_TCC0_WO4 5
450#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
451#define PORT_PA14F_TCC0_WO4 (1u << 14)
452#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
453#define MUX_PA22F_TCC0_WO4 5
454#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
455#define PORT_PA22F_TCC0_WO4 (1u << 22)
456#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
457#define MUX_PA15F_TCC0_WO5 5
458#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
459#define PORT_PA15F_TCC0_WO5 (1u << 15)
460#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
461#define MUX_PA23F_TCC0_WO5 5
462#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
463#define PORT_PA23F_TCC0_WO5 (1u << 23)
464#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
465#define MUX_PA16F_TCC0_WO6 5
466#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
467#define PORT_PA16F_TCC0_WO6 (1u << 16)
468#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
469#define MUX_PA17F_TCC0_WO7 5
470#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
471#define PORT_PA17F_TCC0_WO7 (1u << 17)
472/* ========== PORT definition for TCC1 peripheral ========== */
473#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
474#define MUX_PA06E_TCC1_WO0 4
475#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
476#define PORT_PA06E_TCC1_WO0 (1u << 6)
477#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
478#define MUX_PA10E_TCC1_WO0 4
479#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
480#define PORT_PA10E_TCC1_WO0 (1u << 10)
481#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
482#define MUX_PA30E_TCC1_WO0 4
483#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
484#define PORT_PA30E_TCC1_WO0 (1u << 30)
485#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
486#define MUX_PA07E_TCC1_WO1 4
487#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
488#define PORT_PA07E_TCC1_WO1 (1u << 7)
489#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
490#define MUX_PA11E_TCC1_WO1 4
491#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
492#define PORT_PA11E_TCC1_WO1 (1u << 11)
493#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
494#define MUX_PA31E_TCC1_WO1 4
495#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
496#define PORT_PA31E_TCC1_WO1 (1u << 31)
497#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
498#define MUX_PA08F_TCC1_WO2 5
499#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
500#define PORT_PA08F_TCC1_WO2 (1u << 8)
501#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
502#define MUX_PA24F_TCC1_WO2 5
503#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
504#define PORT_PA24F_TCC1_WO2 (1u << 24)
505#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
506#define MUX_PA09F_TCC1_WO3 5
507#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
508#define PORT_PA09F_TCC1_WO3 (1u << 9)
509#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
510#define MUX_PA25F_TCC1_WO3 5
511#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
512#define PORT_PA25F_TCC1_WO3 (1u << 25)
513/* ========== PORT definition for TCC2 peripheral ========== */
514#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
515#define MUX_PA16E_TCC2_WO0 4
516#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
517#define PORT_PA16E_TCC2_WO0 (1u << 16)
518#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
519#define MUX_PA00E_TCC2_WO0 4
520#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
521#define PORT_PA00E_TCC2_WO0 (1u << 0)
522#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
523#define MUX_PA17E_TCC2_WO1 4
524#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
525#define PORT_PA17E_TCC2_WO1 (1u << 17)
526#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
527#define MUX_PA01E_TCC2_WO1 4
528#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
529#define PORT_PA01E_TCC2_WO1 (1u << 1)
530/* ========== PORT definition for TC3 peripheral ========== */
531#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
532#define MUX_PA18E_TC3_WO0 4
533#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
534#define PORT_PA18E_TC3_WO0 (1u << 18)
535#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
536#define MUX_PA14E_TC3_WO0 4
537#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
538#define PORT_PA14E_TC3_WO0 (1u << 14)
539#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
540#define MUX_PA19E_TC3_WO1 4
541#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
542#define PORT_PA19E_TC3_WO1 (1u << 19)
543#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
544#define MUX_PA15E_TC3_WO1 4
545#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
546#define PORT_PA15E_TC3_WO1 (1u << 15)
547/* ========== PORT definition for TC4 peripheral ========== */
548#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
549#define MUX_PA22E_TC4_WO0 4
550#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
551#define PORT_PA22E_TC4_WO0 (1u << 22)
552#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
553#define MUX_PA23E_TC4_WO1 4
554#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
555#define PORT_PA23E_TC4_WO1 (1u << 23)
556/* ========== PORT definition for TC5 peripheral ========== */
557#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
558#define MUX_PA24E_TC5_WO0 4
559#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
560#define PORT_PA24E_TC5_WO0 (1u << 24)
561#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
562#define MUX_PA25E_TC5_WO1 4
563#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
564#define PORT_PA25E_TC5_WO1 (1u << 25)
565/* ========== PORT definition for ADC peripheral ========== */
566#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
567#define MUX_PA02B_ADC_AIN0 1
568#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
569#define PORT_PA02B_ADC_AIN0 (1u << 2)
570#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
571#define MUX_PA03B_ADC_AIN1 1
572#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
573#define PORT_PA03B_ADC_AIN1 (1u << 3)
574#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
575#define MUX_PA04B_ADC_AIN4 1
576#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
577#define PORT_PA04B_ADC_AIN4 (1u << 4)
578#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
579#define MUX_PA05B_ADC_AIN5 1
580#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
581#define PORT_PA05B_ADC_AIN5 (1u << 5)
582#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
583#define MUX_PA06B_ADC_AIN6 1
584#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
585#define PORT_PA06B_ADC_AIN6 (1u << 6)
586#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
587#define MUX_PA07B_ADC_AIN7 1
588#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
589#define PORT_PA07B_ADC_AIN7 (1u << 7)
590#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
591#define MUX_PA08B_ADC_AIN16 1
592#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
593#define PORT_PA08B_ADC_AIN16 (1u << 8)
594#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
595#define MUX_PA09B_ADC_AIN17 1
596#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
597#define PORT_PA09B_ADC_AIN17 (1u << 9)
598#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
599#define MUX_PA10B_ADC_AIN18 1
600#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
601#define PORT_PA10B_ADC_AIN18 (1u << 10)
602#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
603#define MUX_PA11B_ADC_AIN19 1
604#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
605#define PORT_PA11B_ADC_AIN19 (1u << 11)
606#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
607#define MUX_PA04B_ADC_VREFP 1
608#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
609#define PORT_PA04B_ADC_VREFP (1u << 4)
610/* ========== PORT definition for AC peripheral ========== */
611#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
612#define MUX_PA04B_AC_AIN0 1
613#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
614#define PORT_PA04B_AC_AIN0 (1u << 4)
615#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
616#define MUX_PA05B_AC_AIN1 1
617#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
618#define PORT_PA05B_AC_AIN1 (1u << 5)
619#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
620#define MUX_PA06B_AC_AIN2 1
621#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
622#define PORT_PA06B_AC_AIN2 (1u << 6)
623#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
624#define MUX_PA07B_AC_AIN3 1
625#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
626#define PORT_PA07B_AC_AIN3 (1u << 7)
627#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
628#define MUX_PA18H_AC_CMP0 7
629#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
630#define PORT_PA18H_AC_CMP0 (1u << 18)
631#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
632#define MUX_PA19H_AC_CMP1 7
633#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
634#define PORT_PA19H_AC_CMP1 (1u << 19)
635/* ========== PORT definition for DAC peripheral ========== */
636#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
637#define MUX_PA02B_DAC_VOUT 1
638#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
639#define PORT_PA02B_DAC_VOUT (1u << 2)
640#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
641#define MUX_PA03B_DAC_VREFP 1
642#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
643#define PORT_PA03B_DAC_VREFP (1u << 3)
644/* ========== PORT definition for I2S peripheral ========== */
645#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
646#define MUX_PA11G_I2S_FS0 6
647#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
648#define PORT_PA11G_I2S_FS0 (1u << 11)
649#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
650#define MUX_PA09G_I2S_MCK0 6
651#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
652#define PORT_PA09G_I2S_MCK0 (1u << 9)
653#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
654#define MUX_PA10G_I2S_SCK0 6
655#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
656#define PORT_PA10G_I2S_SCK0 (1u << 10)
657#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
658#define MUX_PA07G_I2S_SD0 6
659#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
660#define PORT_PA07G_I2S_SD0 (1u << 7)
661#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
662#define MUX_PA19G_I2S_SD0 6
663#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
664#define PORT_PA19G_I2S_SD0 (1u << 19)
665#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
666#define MUX_PA08G_I2S_SD1 6
667#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
668#define PORT_PA08G_I2S_SD1 (1u << 8)
669
670#endif /* _SAMD21E15A_PIO_ */
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