source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/instance/usb.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Instance description for USB
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_USB_INSTANCE_
45#define _SAMD21_USB_INSTANCE_
46
47/* ========== Register definition for USB peripheral ========== */
48#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
49#define REG_USB_CTRLA (0x41005000U) /**< \brief (USB) Control A */
50#define REG_USB_SYNCBUSY (0x41005002U) /**< \brief (USB) Synchronization Busy */
51#define REG_USB_FSMSTATUS (0x4100500DU) /**< \brief (USB) Finite State Machine Status */
52#define REG_USB_DESCADD (0x41005024U) /**< \brief (USB) Descriptor Address */
53#define REG_USB_PADCAL (0x41005028U) /**< \brief (USB) USB PAD Calibration */
54#define REG_USB_DEVICE_CTRLB (0x41005008U) /**< \brief (USB) DEVICE Control B */
55#define REG_USB_DEVICE_DADD (0x4100500AU) /**< \brief (USB) DEVICE Device Address */
56#define REG_USB_DEVICE_STATUS (0x4100500CU) /**< \brief (USB) DEVICE Status */
57#define REG_USB_DEVICE_FNUM (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
58#define REG_USB_DEVICE_INTENCLR (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
59#define REG_USB_DEVICE_INTENSET (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
60#define REG_USB_DEVICE_INTFLAG (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
61#define REG_USB_DEVICE_EPINTSMRY (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
62#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
63#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
64#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
65#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
66#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
67#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
68#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
69#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
70#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
71#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
72#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
73#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
74#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
75#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
76#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
77#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
78#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
79#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
80#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
81#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
82#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
83#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
84#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
85#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
86#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
87#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
88#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
89#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
90#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
91#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
92#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
93#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
94#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
95#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
96#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
97#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
98#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
99#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
100#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
101#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
102#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
103#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
104#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
105#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
106#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
107#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
108#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
109#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
110#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
111#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
112#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
113#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
114#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
115#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
116#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
117#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
118#define REG_USB_HOST_CTRLB (0x41005008U) /**< \brief (USB) HOST Control B */
119#define REG_USB_HOST_HSOFC (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
120#define REG_USB_HOST_STATUS (0x4100500CU) /**< \brief (USB) HOST Status */
121#define REG_USB_HOST_FNUM (0x41005010U) /**< \brief (USB) HOST Host Frame Number */
122#define REG_USB_HOST_FLENHIGH (0x41005012U) /**< \brief (USB) HOST Host Frame Length */
123#define REG_USB_HOST_INTENCLR (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
124#define REG_USB_HOST_INTENSET (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
125#define REG_USB_HOST_INTFLAG (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
126#define REG_USB_HOST_PINTSMRY (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
127#define REG_USB_HOST_PIPE_PCFG0 (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
128#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
129#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
130#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
131#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
132#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
133#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
134#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
135#define REG_USB_HOST_PIPE_PCFG1 (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
136#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
137#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
138#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
139#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
140#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
141#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
142#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
143#define REG_USB_HOST_PIPE_PCFG2 (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
144#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
145#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
146#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
147#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
148#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
149#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
150#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
151#define REG_USB_HOST_PIPE_PCFG3 (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
152#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
153#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
154#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
155#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
156#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
157#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
158#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
159#define REG_USB_HOST_PIPE_PCFG4 (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
160#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
161#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
162#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
163#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
164#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
165#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
166#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
167#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
168#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
169#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
170#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
171#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
172#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
173#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
174#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
175#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
176#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
177#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
178#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
179#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
180#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
181#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
182#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
183#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
184#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
185#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
186#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
187#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
188#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
189#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
190#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
191#else
192#define REG_USB_CTRLA (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */
193#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */
194#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */
195#define REG_USB_DESCADD (*(RwReg *)0x41005024U) /**< \brief (USB) Descriptor Address */
196#define REG_USB_PADCAL (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */
197#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */
198#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */
199#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */
200#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
201#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
202#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
203#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
204#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
205#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
206#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
207#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
208#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
209#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
210#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
211#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
212#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
213#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
214#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
215#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
216#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
217#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
218#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
219#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
220#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
221#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
222#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
223#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
224#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
225#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
226#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
227#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
228#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
229#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
230#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
231#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
232#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
233#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
234#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
235#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
236#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
237#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
238#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
239#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
240#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
241#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
242#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
243#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
244#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
245#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
246#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
247#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
248#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
249#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
250#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
251#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
252#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
253#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
254#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
255#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
256#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
257#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
258#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
259#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
260#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
261#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */
262#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
263#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */
264#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */
265#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */
266#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
267#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
268#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
269#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
270#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
271#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
272#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
273#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
274#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
275#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
276#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
277#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
278#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
279#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
280#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
281#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
282#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
283#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
284#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
285#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
286#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
287#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
288#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
289#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
290#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
291#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
292#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
293#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
294#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
295#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
296#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
297#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
298#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
299#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
300#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
301#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
302#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
303#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
304#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
305#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
306#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
307#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
308#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
309#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
310#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
311#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
312#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
313#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
314#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
315#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
316#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
317#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
318#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
319#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
320#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
321#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
322#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
323#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
324#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
325#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
326#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
327#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
328#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
329#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
330#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
331#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
332#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
333#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
334#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
335
336/* ========== Instance parameters for USB peripheral ========== */
337#define USB_EPT_NBR USB_EPT_NUM
338#define USB_EPT_NUM 8
339#define USB_GCLK_ID 6
340#define USB_PIPE_NUM 8
341
342#endif /* _SAMD21_USB_INSTANCE_ */
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