source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/instance/tcc2.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Instance description for TCC2
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_TCC2_INSTANCE_
45#define _SAMD21_TCC2_INSTANCE_
46
47/* ========== Register definition for TCC2 peripheral ========== */
48#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
49#define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */
50#define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */
51#define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */
52#define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
53#define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable FaultA Configuration */
54#define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable FaultB Configuration */
55#define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Configuration */
56#define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */
57#define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */
58#define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
59#define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
60#define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
61#define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */
62#define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */
63#define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */
64#define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */
65#define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
66#define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
67#define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
68#define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */
69#define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
70#define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
71#else
72#define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */
73#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
74#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
75#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
76#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable FaultA Configuration */
77#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable FaultB Configuration */
78#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Configuration */
79#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
80#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */
81#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
82#define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
83#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
84#define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */
85#define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */
86#define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
87#define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */
88#define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
89#define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
90#define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
91#define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
92#define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
93#define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
94#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
95
96/* ========== Instance parameters for TCC2 peripheral ========== */
97#define TCC2_CC_NUM 2
98#define TCC2_DITHERING 0
99#define TCC2_DMAC_ID_MC_0 22
100#define TCC2_DMAC_ID_MC_1 23
101#define TCC2_DMAC_ID_MC_LSB 22
102#define TCC2_DMAC_ID_MC_MSB 23
103#define TCC2_DMAC_ID_MC_SIZE 2
104#define TCC2_DMAC_ID_OVF 21
105#define TCC2_DTI 0
106#define TCC2_EXT (TCC2_DITHERING*16+TCC2_PG*8+TCC2_SWAP*4+TCC2_DTI*2+TCC2_OTMX*1)
107#define TCC2_GCLK_ID 27
108#define TCC2_MASTER 0
109#define TCC2_OTMX 0
110#define TCC2_OW_NUM 2
111#define TCC2_PG 0
112#define TCC2_SIZE 16
113#define TCC2_SWAP 0
114
115#endif /* _SAMD21_TCC2_INSTANCE_ */
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