source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/instance/rtc.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

ライブラリとOS及びベーシックなサンプルの追加．
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1/**
2 * \file
3 *
4 * \brief Instance description for RTC
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_RTC_INSTANCE_
45#define _SAMD21_RTC_INSTANCE_
46
47/* ========== Register definition for RTC peripheral ========== */
48#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
49#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */
50#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */
51#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */
52#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */
53#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */
54#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
55#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
56#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
57#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
58#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
59#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
60#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */
61#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
62#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
63#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
64#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
65#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
66#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
67#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
68#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
69#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */
70#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
71#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
72#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
73#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
74#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
75#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
76#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
77#else
78#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
79#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
80#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
81#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
82#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
83#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
84#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
85#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
86#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
87#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
88#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
89#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
90#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
91#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
92#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
93#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
94#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
95#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
96#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
97#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
98#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
99#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
100#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
101#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
102#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
103#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
104#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
105#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
106#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
107
108/* ========== Instance parameters for RTC peripheral ========== */
109#define RTC_ALARM_NUM 1
110#define RTC_COMP16_NUM 2
111#define RTC_COMP32_NUM RTC_ALARM_NUM
112#define RTC_GCLK_ID 4
113#define RTC_NUM_OF_ALARMS RTC_ALARM_NUM
114#define RTC_NUM_OF_COMP16 RTC_COMP16_NUM
115#define RTC_NUM_OF_COMP32 RTC_COMP32_NUM
116
117#endif /* _SAMD21_RTC_INSTANCE_ */
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