1 | /**
|
---|
2 | * \file
|
---|
3 | *
|
---|
4 | * \brief Instance description for DSU
|
---|
5 | *
|
---|
6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
|
---|
7 | *
|
---|
8 | * \asf_license_start
|
---|
9 | *
|
---|
10 | * \page License
|
---|
11 | *
|
---|
12 | * Redistribution and use in source and binary forms, with or without
|
---|
13 | * modification, are permitted provided that the following conditions are met:
|
---|
14 | *
|
---|
15 | * 1. Redistributions of source code must retain the above copyright notice,
|
---|
16 | * this list of conditions and the following disclaimer.
|
---|
17 | *
|
---|
18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
|
---|
19 | * this list of conditions and the following disclaimer in the documentation
|
---|
20 | * and/or other materials provided with the distribution.
|
---|
21 | *
|
---|
22 | * 3. The name of Atmel may not be used to endorse or promote products derived
|
---|
23 | * from this software without specific prior written permission.
|
---|
24 | *
|
---|
25 | * 4. This software may only be redistributed and used in connection with an
|
---|
26 | * Atmel microcontroller product.
|
---|
27 | *
|
---|
28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
---|
29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
---|
30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
---|
31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
---|
32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
---|
33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
---|
34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
---|
35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
---|
36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
---|
37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
---|
38 | * POSSIBILITY OF SUCH DAMAGE.
|
---|
39 | *
|
---|
40 | * \asf_license_stop
|
---|
41 | *
|
---|
42 | */
|
---|
43 |
|
---|
44 | #ifndef _SAMD21_DSU_INSTANCE_
|
---|
45 | #define _SAMD21_DSU_INSTANCE_
|
---|
46 |
|
---|
47 | /* ========== Register definition for DSU peripheral ========== */
|
---|
48 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
49 | #define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */
|
---|
50 | #define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */
|
---|
51 | #define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */
|
---|
52 | #define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */
|
---|
53 | #define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */
|
---|
54 | #define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */
|
---|
55 | #define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
|
---|
56 | #define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
|
---|
57 | #define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */
|
---|
58 | #define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
|
---|
59 | #define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
|
---|
60 | #define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
|
---|
61 | #define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
|
---|
62 | #define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
|
---|
63 | #define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
|
---|
64 | #define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
|
---|
65 | #define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
|
---|
66 | #define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
|
---|
67 | #define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
|
---|
68 | #define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
|
---|
69 | #define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
|
---|
70 | #define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
|
---|
71 | #else
|
---|
72 | #define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
|
---|
73 | #define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
|
---|
74 | #define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
|
---|
75 | #define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */
|
---|
76 | #define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */
|
---|
77 | #define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */
|
---|
78 | #define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
|
---|
79 | #define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
|
---|
80 | #define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */
|
---|
81 | #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
|
---|
82 | #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
|
---|
83 | #define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
|
---|
84 | #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
|
---|
85 | #define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
|
---|
86 | #define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
|
---|
87 | #define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
|
---|
88 | #define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
|
---|
89 | #define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
|
---|
90 | #define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
|
---|
91 | #define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
|
---|
92 | #define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
|
---|
93 | #define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
|
---|
94 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
95 |
|
---|
96 | /* ========== Instance parameters for DSU peripheral ========== */
|
---|
97 | #define DSU_CLK_HSB_ID 3
|
---|
98 |
|
---|
99 | #endif /* _SAMD21_DSU_INSTANCE_ */
|
---|