1 | /**
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2 | * \file
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3 | *
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4 | * \brief Component description for WDT
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_WDT_COMPONENT_
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45 | #define _SAMD21_WDT_COMPONENT_
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46 |
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47 | /* ========================================================================== */
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48 | /** SOFTWARE API DEFINITION FOR WDT */
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49 | /* ========================================================================== */
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50 | /** \addtogroup SAMD21_WDT Watchdog Timer */
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51 | /*@{*/
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52 |
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53 | #define WDT_U2203
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54 | #define REV_WDT 0x200
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55 |
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56 | /* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
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57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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58 | typedef union {
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59 | struct {
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60 | uint8_t :1; /*!< bit: 0 Reserved */
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61 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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62 | uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
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63 | uint8_t :4; /*!< bit: 3.. 6 Reserved */
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64 | uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
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65 | } bit; /*!< Structure used for bit access */
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66 | uint8_t reg; /*!< Type used for register access */
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67 | } WDT_CTRL_Type;
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68 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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69 |
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70 | #define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
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71 | #define WDT_CTRL_RESETVALUE 0x00 /**< \brief (WDT_CTRL reset_value) Control */
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72 |
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73 | #define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
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74 | #define WDT_CTRL_ENABLE (0x1u << WDT_CTRL_ENABLE_Pos)
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75 | #define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
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76 | #define WDT_CTRL_WEN (0x1u << WDT_CTRL_WEN_Pos)
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77 | #define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
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78 | #define WDT_CTRL_ALWAYSON (0x1u << WDT_CTRL_ALWAYSON_Pos)
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79 | #define WDT_CTRL_MASK 0x86u /**< \brief (WDT_CTRL) MASK Register */
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80 |
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81 | /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
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82 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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83 | typedef union {
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84 | struct {
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85 | uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
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86 | uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
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87 | } bit; /*!< Structure used for bit access */
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88 | uint8_t reg; /*!< Type used for register access */
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89 | } WDT_CONFIG_Type;
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90 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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91 |
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92 | #define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
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93 | #define WDT_CONFIG_RESETVALUE 0xBB /**< \brief (WDT_CONFIG reset_value) Configuration */
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94 |
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95 | #define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
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96 | #define WDT_CONFIG_PER_Msk (0xFu << WDT_CONFIG_PER_Pos)
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97 | #define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))
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98 | #define WDT_CONFIG_PER_0_Val 0x0u /**< \brief (WDT_CONFIG) 8 clock cycles */
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99 | #define WDT_CONFIG_PER_1_Val 0x1u /**< \brief (WDT_CONFIG) 16 clock cycles */
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100 | #define WDT_CONFIG_PER_2_Val 0x2u /**< \brief (WDT_CONFIG) 32 clock cycles */
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101 | #define WDT_CONFIG_PER_3_Val 0x3u /**< \brief (WDT_CONFIG) 64 clock cycles */
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102 | #define WDT_CONFIG_PER_4_Val 0x4u /**< \brief (WDT_CONFIG) 128 clock cycles */
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103 | #define WDT_CONFIG_PER_5_Val 0x5u /**< \brief (WDT_CONFIG) 256 clock cycles */
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104 | #define WDT_CONFIG_PER_6_Val 0x6u /**< \brief (WDT_CONFIG) 512 clock cycles */
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105 | #define WDT_CONFIG_PER_7_Val 0x7u /**< \brief (WDT_CONFIG) 1024 clock cycles */
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106 | #define WDT_CONFIG_PER_8_Val 0x8u /**< \brief (WDT_CONFIG) 2048 clock cycles */
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107 | #define WDT_CONFIG_PER_9_Val 0x9u /**< \brief (WDT_CONFIG) 4096 clock cycles */
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108 | #define WDT_CONFIG_PER_10_Val 0xAu /**< \brief (WDT_CONFIG) 8192 clock cycles */
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109 | #define WDT_CONFIG_PER_11_Val 0xBu /**< \brief (WDT_CONFIG) 16384 clock cycles */
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110 | #define WDT_CONFIG_PER_0 (WDT_CONFIG_PER_0_Val << WDT_CONFIG_PER_Pos)
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111 | #define WDT_CONFIG_PER_1 (WDT_CONFIG_PER_1_Val << WDT_CONFIG_PER_Pos)
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112 | #define WDT_CONFIG_PER_2 (WDT_CONFIG_PER_2_Val << WDT_CONFIG_PER_Pos)
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113 | #define WDT_CONFIG_PER_3 (WDT_CONFIG_PER_3_Val << WDT_CONFIG_PER_Pos)
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114 | #define WDT_CONFIG_PER_4 (WDT_CONFIG_PER_4_Val << WDT_CONFIG_PER_Pos)
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115 | #define WDT_CONFIG_PER_5 (WDT_CONFIG_PER_5_Val << WDT_CONFIG_PER_Pos)
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116 | #define WDT_CONFIG_PER_6 (WDT_CONFIG_PER_6_Val << WDT_CONFIG_PER_Pos)
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117 | #define WDT_CONFIG_PER_7 (WDT_CONFIG_PER_7_Val << WDT_CONFIG_PER_Pos)
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118 | #define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
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119 | #define WDT_CONFIG_PER_9 (WDT_CONFIG_PER_9_Val << WDT_CONFIG_PER_Pos)
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120 | #define WDT_CONFIG_PER_10 (WDT_CONFIG_PER_10_Val << WDT_CONFIG_PER_Pos)
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121 | #define WDT_CONFIG_PER_11 (WDT_CONFIG_PER_11_Val << WDT_CONFIG_PER_Pos)
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122 | #define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
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123 | #define WDT_CONFIG_WINDOW_Msk (0xFu << WDT_CONFIG_WINDOW_Pos)
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124 | #define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))
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125 | #define WDT_CONFIG_WINDOW_0_Val 0x0u /**< \brief (WDT_CONFIG) 8 clock cycles */
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126 | #define WDT_CONFIG_WINDOW_1_Val 0x1u /**< \brief (WDT_CONFIG) 16 clock cycles */
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127 | #define WDT_CONFIG_WINDOW_2_Val 0x2u /**< \brief (WDT_CONFIG) 32 clock cycles */
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128 | #define WDT_CONFIG_WINDOW_3_Val 0x3u /**< \brief (WDT_CONFIG) 64 clock cycles */
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129 | #define WDT_CONFIG_WINDOW_4_Val 0x4u /**< \brief (WDT_CONFIG) 128 clock cycles */
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130 | #define WDT_CONFIG_WINDOW_5_Val 0x5u /**< \brief (WDT_CONFIG) 256 clock cycles */
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131 | #define WDT_CONFIG_WINDOW_6_Val 0x6u /**< \brief (WDT_CONFIG) 512 clock cycles */
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132 | #define WDT_CONFIG_WINDOW_7_Val 0x7u /**< \brief (WDT_CONFIG) 1024 clock cycles */
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133 | #define WDT_CONFIG_WINDOW_8_Val 0x8u /**< \brief (WDT_CONFIG) 2048 clock cycles */
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134 | #define WDT_CONFIG_WINDOW_9_Val 0x9u /**< \brief (WDT_CONFIG) 4096 clock cycles */
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135 | #define WDT_CONFIG_WINDOW_10_Val 0xAu /**< \brief (WDT_CONFIG) 8192 clock cycles */
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136 | #define WDT_CONFIG_WINDOW_11_Val 0xBu /**< \brief (WDT_CONFIG) 16384 clock cycles */
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137 | #define WDT_CONFIG_WINDOW_0 (WDT_CONFIG_WINDOW_0_Val << WDT_CONFIG_WINDOW_Pos)
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138 | #define WDT_CONFIG_WINDOW_1 (WDT_CONFIG_WINDOW_1_Val << WDT_CONFIG_WINDOW_Pos)
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139 | #define WDT_CONFIG_WINDOW_2 (WDT_CONFIG_WINDOW_2_Val << WDT_CONFIG_WINDOW_Pos)
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140 | #define WDT_CONFIG_WINDOW_3 (WDT_CONFIG_WINDOW_3_Val << WDT_CONFIG_WINDOW_Pos)
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141 | #define WDT_CONFIG_WINDOW_4 (WDT_CONFIG_WINDOW_4_Val << WDT_CONFIG_WINDOW_Pos)
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142 | #define WDT_CONFIG_WINDOW_5 (WDT_CONFIG_WINDOW_5_Val << WDT_CONFIG_WINDOW_Pos)
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143 | #define WDT_CONFIG_WINDOW_6 (WDT_CONFIG_WINDOW_6_Val << WDT_CONFIG_WINDOW_Pos)
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144 | #define WDT_CONFIG_WINDOW_7 (WDT_CONFIG_WINDOW_7_Val << WDT_CONFIG_WINDOW_Pos)
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145 | #define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
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146 | #define WDT_CONFIG_WINDOW_9 (WDT_CONFIG_WINDOW_9_Val << WDT_CONFIG_WINDOW_Pos)
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147 | #define WDT_CONFIG_WINDOW_10 (WDT_CONFIG_WINDOW_10_Val << WDT_CONFIG_WINDOW_Pos)
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148 | #define WDT_CONFIG_WINDOW_11 (WDT_CONFIG_WINDOW_11_Val << WDT_CONFIG_WINDOW_Pos)
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149 | #define WDT_CONFIG_MASK 0xFFu /**< \brief (WDT_CONFIG) MASK Register */
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150 |
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151 | /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
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152 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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153 | typedef union {
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154 | struct {
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155 | uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
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156 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
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157 | } bit; /*!< Structure used for bit access */
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158 | uint8_t reg; /*!< Type used for register access */
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159 | } WDT_EWCTRL_Type;
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160 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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161 |
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162 | #define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
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163 | #define WDT_EWCTRL_RESETVALUE 0x0B /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
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164 |
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165 | #define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
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166 | #define WDT_EWCTRL_EWOFFSET_Msk (0xFu << WDT_EWCTRL_EWOFFSET_Pos)
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167 | #define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))
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168 | #define WDT_EWCTRL_EWOFFSET_0_Val 0x0u /**< \brief (WDT_EWCTRL) 8 clock cycles */
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169 | #define WDT_EWCTRL_EWOFFSET_1_Val 0x1u /**< \brief (WDT_EWCTRL) 16 clock cycles */
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170 | #define WDT_EWCTRL_EWOFFSET_2_Val 0x2u /**< \brief (WDT_EWCTRL) 32 clock cycles */
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171 | #define WDT_EWCTRL_EWOFFSET_3_Val 0x3u /**< \brief (WDT_EWCTRL) 64 clock cycles */
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172 | #define WDT_EWCTRL_EWOFFSET_4_Val 0x4u /**< \brief (WDT_EWCTRL) 128 clock cycles */
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173 | #define WDT_EWCTRL_EWOFFSET_5_Val 0x5u /**< \brief (WDT_EWCTRL) 256 clock cycles */
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174 | #define WDT_EWCTRL_EWOFFSET_6_Val 0x6u /**< \brief (WDT_EWCTRL) 512 clock cycles */
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175 | #define WDT_EWCTRL_EWOFFSET_7_Val 0x7u /**< \brief (WDT_EWCTRL) 1024 clock cycles */
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176 | #define WDT_EWCTRL_EWOFFSET_8_Val 0x8u /**< \brief (WDT_EWCTRL) 2048 clock cycles */
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177 | #define WDT_EWCTRL_EWOFFSET_9_Val 0x9u /**< \brief (WDT_EWCTRL) 4096 clock cycles */
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178 | #define WDT_EWCTRL_EWOFFSET_10_Val 0xAu /**< \brief (WDT_EWCTRL) 8192 clock cycles */
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179 | #define WDT_EWCTRL_EWOFFSET_11_Val 0xBu /**< \brief (WDT_EWCTRL) 16384 clock cycles */
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180 | #define WDT_EWCTRL_EWOFFSET_0 (WDT_EWCTRL_EWOFFSET_0_Val << WDT_EWCTRL_EWOFFSET_Pos)
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181 | #define WDT_EWCTRL_EWOFFSET_1 (WDT_EWCTRL_EWOFFSET_1_Val << WDT_EWCTRL_EWOFFSET_Pos)
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182 | #define WDT_EWCTRL_EWOFFSET_2 (WDT_EWCTRL_EWOFFSET_2_Val << WDT_EWCTRL_EWOFFSET_Pos)
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183 | #define WDT_EWCTRL_EWOFFSET_3 (WDT_EWCTRL_EWOFFSET_3_Val << WDT_EWCTRL_EWOFFSET_Pos)
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184 | #define WDT_EWCTRL_EWOFFSET_4 (WDT_EWCTRL_EWOFFSET_4_Val << WDT_EWCTRL_EWOFFSET_Pos)
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185 | #define WDT_EWCTRL_EWOFFSET_5 (WDT_EWCTRL_EWOFFSET_5_Val << WDT_EWCTRL_EWOFFSET_Pos)
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186 | #define WDT_EWCTRL_EWOFFSET_6 (WDT_EWCTRL_EWOFFSET_6_Val << WDT_EWCTRL_EWOFFSET_Pos)
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187 | #define WDT_EWCTRL_EWOFFSET_7 (WDT_EWCTRL_EWOFFSET_7_Val << WDT_EWCTRL_EWOFFSET_Pos)
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188 | #define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
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189 | #define WDT_EWCTRL_EWOFFSET_9 (WDT_EWCTRL_EWOFFSET_9_Val << WDT_EWCTRL_EWOFFSET_Pos)
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190 | #define WDT_EWCTRL_EWOFFSET_10 (WDT_EWCTRL_EWOFFSET_10_Val << WDT_EWCTRL_EWOFFSET_Pos)
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191 | #define WDT_EWCTRL_EWOFFSET_11 (WDT_EWCTRL_EWOFFSET_11_Val << WDT_EWCTRL_EWOFFSET_Pos)
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192 | #define WDT_EWCTRL_MASK 0x0Fu /**< \brief (WDT_EWCTRL) MASK Register */
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193 |
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194 | /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
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195 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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196 | typedef union {
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197 | struct {
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198 | uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
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199 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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200 | } bit; /*!< Structure used for bit access */
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201 | uint8_t reg; /*!< Type used for register access */
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202 | } WDT_INTENCLR_Type;
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203 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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204 |
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205 | #define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
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206 | #define WDT_INTENCLR_RESETVALUE 0x00 /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
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207 |
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208 | #define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
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209 | #define WDT_INTENCLR_EW (0x1u << WDT_INTENCLR_EW_Pos)
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210 | #define WDT_INTENCLR_MASK 0x01u /**< \brief (WDT_INTENCLR) MASK Register */
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211 |
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212 | /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
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213 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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214 | typedef union {
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215 | struct {
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216 | uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
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217 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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218 | } bit; /*!< Structure used for bit access */
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219 | uint8_t reg; /*!< Type used for register access */
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220 | } WDT_INTENSET_Type;
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221 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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222 |
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223 | #define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
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224 | #define WDT_INTENSET_RESETVALUE 0x00 /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
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225 |
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226 | #define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
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227 | #define WDT_INTENSET_EW (0x1u << WDT_INTENSET_EW_Pos)
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228 | #define WDT_INTENSET_MASK 0x01u /**< \brief (WDT_INTENSET) MASK Register */
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229 |
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230 | /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
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231 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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232 | typedef union {
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233 | struct {
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234 | uint8_t EW:1; /*!< bit: 0 Early Warning */
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235 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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236 | } bit; /*!< Structure used for bit access */
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237 | uint8_t reg; /*!< Type used for register access */
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238 | } WDT_INTFLAG_Type;
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239 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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240 |
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241 | #define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
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242 | #define WDT_INTFLAG_RESETVALUE 0x00 /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
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243 |
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244 | #define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
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245 | #define WDT_INTFLAG_EW (0x1u << WDT_INTFLAG_EW_Pos)
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246 | #define WDT_INTFLAG_MASK 0x01u /**< \brief (WDT_INTFLAG) MASK Register */
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247 |
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248 | /* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
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249 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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250 | typedef union {
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251 | struct {
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252 | uint8_t :7; /*!< bit: 0.. 6 Reserved */
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253 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
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254 | } bit; /*!< Structure used for bit access */
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255 | uint8_t reg; /*!< Type used for register access */
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256 | } WDT_STATUS_Type;
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257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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258 |
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259 | #define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
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260 | #define WDT_STATUS_RESETVALUE 0x00 /**< \brief (WDT_STATUS reset_value) Status */
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261 |
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262 | #define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
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263 | #define WDT_STATUS_SYNCBUSY (0x1u << WDT_STATUS_SYNCBUSY_Pos)
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264 | #define WDT_STATUS_MASK 0x80u /**< \brief (WDT_STATUS) MASK Register */
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265 |
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266 | /* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
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267 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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268 | typedef union {
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269 | struct {
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270 | uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
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271 | } bit; /*!< Structure used for bit access */
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272 | uint8_t reg; /*!< Type used for register access */
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273 | } WDT_CLEAR_Type;
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274 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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275 |
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276 | #define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
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277 | #define WDT_CLEAR_RESETVALUE 0x00 /**< \brief (WDT_CLEAR reset_value) Clear */
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278 |
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279 | #define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
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280 | #define WDT_CLEAR_CLEAR_Msk (0xFFu << WDT_CLEAR_CLEAR_Pos)
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281 | #define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))
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282 | #define WDT_CLEAR_CLEAR_KEY_Val 0xA5u /**< \brief (WDT_CLEAR) Clear Key */
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283 | #define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
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284 | #define WDT_CLEAR_MASK 0xFFu /**< \brief (WDT_CLEAR) MASK Register */
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285 |
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286 | /** \brief WDT hardware registers */
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287 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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288 | typedef struct {
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289 | __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
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290 | __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
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291 | __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
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292 | RoReg8 Reserved1[0x1];
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293 | __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
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294 | __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
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295 | __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
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296 | __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
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297 | __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
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298 | } Wdt;
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299 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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300 |
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301 | /*@}*/
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302 |
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303 | #endif /* _SAMD21_WDT_COMPONENT_ */
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