1 | /**
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2 | * \file
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3 | *
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4 | * \brief Component description for USB
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_USB_COMPONENT_
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45 | #define _SAMD21_USB_COMPONENT_
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46 |
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47 | /* ========================================================================== */
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48 | /** SOFTWARE API DEFINITION FOR USB */
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49 | /* ========================================================================== */
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50 | /** \addtogroup SAMD21_USB Universal Serial Bus */
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51 | /*@{*/
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52 |
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53 | #define USB_U2222
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54 | #define REV_USB 0x101
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55 |
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56 | /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
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57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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58 | typedef union {
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59 | struct {
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60 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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61 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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62 | uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
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63 | uint8_t :4; /*!< bit: 3.. 6 Reserved */
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64 | uint8_t MODE:1; /*!< bit: 7 Operating Mode */
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65 | } bit; /*!< Structure used for bit access */
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66 | uint8_t reg; /*!< Type used for register access */
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67 | } USB_CTRLA_Type;
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68 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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69 |
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70 | #define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
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71 | #define USB_CTRLA_RESETVALUE 0x00 /**< \brief (USB_CTRLA reset_value) Control A */
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72 |
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73 | #define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
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74 | #define USB_CTRLA_SWRST (0x1u << USB_CTRLA_SWRST_Pos)
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75 | #define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
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76 | #define USB_CTRLA_ENABLE (0x1u << USB_CTRLA_ENABLE_Pos)
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77 | #define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
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78 | #define USB_CTRLA_RUNSTDBY (0x1u << USB_CTRLA_RUNSTDBY_Pos)
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79 | #define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
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80 | #define USB_CTRLA_MODE (0x1u << USB_CTRLA_MODE_Pos)
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81 | #define USB_CTRLA_MODE_DEVICE_Val 0x0u /**< \brief (USB_CTRLA) Device Mode */
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82 | #define USB_CTRLA_MODE_HOST_Val 0x1u /**< \brief (USB_CTRLA) Host Mode */
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83 | #define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
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84 | #define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
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85 | #define USB_CTRLA_MASK 0x87u /**< \brief (USB_CTRLA) MASK Register */
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86 |
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87 | /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
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88 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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89 | typedef union {
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90 | struct {
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91 | uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
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92 | uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
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93 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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94 | } bit; /*!< Structure used for bit access */
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95 | uint8_t reg; /*!< Type used for register access */
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96 | } USB_SYNCBUSY_Type;
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97 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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98 |
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99 | #define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
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100 | #define USB_SYNCBUSY_RESETVALUE 0x00 /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
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101 |
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102 | #define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
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103 | #define USB_SYNCBUSY_SWRST (0x1u << USB_SYNCBUSY_SWRST_Pos)
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104 | #define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
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105 | #define USB_SYNCBUSY_ENABLE (0x1u << USB_SYNCBUSY_ENABLE_Pos)
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106 | #define USB_SYNCBUSY_MASK 0x03u /**< \brief (USB_SYNCBUSY) MASK Register */
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107 |
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108 | /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
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109 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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110 | typedef union {
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111 | struct {
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112 | uint16_t DETACH:1; /*!< bit: 0 Detach */
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113 | uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
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114 | uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
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115 | uint16_t NREPLY:1; /*!< bit: 4 No Reply */
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116 | uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
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117 | uint16_t TSTK:1; /*!< bit: 6 Test mode K */
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118 | uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
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119 | uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
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120 | uint16_t GNAK:1; /*!< bit: 9 Global NAK */
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121 | uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
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122 | uint16_t :4; /*!< bit: 12..15 Reserved */
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123 | } bit; /*!< Structure used for bit access */
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124 | uint16_t reg; /*!< Type used for register access */
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125 | } USB_DEVICE_CTRLB_Type;
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126 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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127 |
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128 | #define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
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129 | #define USB_DEVICE_CTRLB_RESETVALUE 0x0001 /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
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130 |
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131 | #define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
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132 | #define USB_DEVICE_CTRLB_DETACH (0x1u << USB_DEVICE_CTRLB_DETACH_Pos)
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133 | #define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
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134 | #define USB_DEVICE_CTRLB_UPRSM (0x1u << USB_DEVICE_CTRLB_UPRSM_Pos)
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135 | #define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
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136 | #define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3u << USB_DEVICE_CTRLB_SPDCONF_Pos)
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137 | #define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)))
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138 | #define USB_DEVICE_CTRLB_SPDCONF_0_Val 0x0u /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
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139 | #define USB_DEVICE_CTRLB_SPDCONF_1_Val 0x1u /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
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140 | #define USB_DEVICE_CTRLB_SPDCONF_2_Val 0x2u /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
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141 | #define USB_DEVICE_CTRLB_SPDCONF_3_Val 0x3u /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
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142 | #define USB_DEVICE_CTRLB_SPDCONF_0 (USB_DEVICE_CTRLB_SPDCONF_0_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
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143 | #define USB_DEVICE_CTRLB_SPDCONF_1 (USB_DEVICE_CTRLB_SPDCONF_1_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
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144 | #define USB_DEVICE_CTRLB_SPDCONF_2 (USB_DEVICE_CTRLB_SPDCONF_2_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
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145 | #define USB_DEVICE_CTRLB_SPDCONF_3 (USB_DEVICE_CTRLB_SPDCONF_3_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
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146 | #define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
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147 | #define USB_DEVICE_CTRLB_NREPLY (0x1u << USB_DEVICE_CTRLB_NREPLY_Pos)
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148 | #define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
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149 | #define USB_DEVICE_CTRLB_TSTJ (0x1u << USB_DEVICE_CTRLB_TSTJ_Pos)
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150 | #define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
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151 | #define USB_DEVICE_CTRLB_TSTK (0x1u << USB_DEVICE_CTRLB_TSTK_Pos)
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152 | #define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
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153 | #define USB_DEVICE_CTRLB_TSTPCKT (0x1u << USB_DEVICE_CTRLB_TSTPCKT_Pos)
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154 | #define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
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155 | #define USB_DEVICE_CTRLB_OPMODE2 (0x1u << USB_DEVICE_CTRLB_OPMODE2_Pos)
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156 | #define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
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157 | #define USB_DEVICE_CTRLB_GNAK (0x1u << USB_DEVICE_CTRLB_GNAK_Pos)
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158 | #define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
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159 | #define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3u << USB_DEVICE_CTRLB_LPMHDSK_Pos)
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160 | #define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)))
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161 | #define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0u /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
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162 | #define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1u /**< \brief (USB_DEVICE_CTRLB) ACK */
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163 | #define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2u /**< \brief (USB_DEVICE_CTRLB) NYET */
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164 | #define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3u /**< \brief (USB_DEVICE_CTRLB) STALL */
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165 | #define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
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166 | #define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
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167 | #define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
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168 | #define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
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169 | #define USB_DEVICE_CTRLB_MASK 0x0FFFu /**< \brief (USB_DEVICE_CTRLB) MASK Register */
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170 |
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171 | /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
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172 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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173 | typedef union {
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174 | struct {
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175 | uint16_t :1; /*!< bit: 0 Reserved */
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176 | uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
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177 | uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
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178 | uint16_t :1; /*!< bit: 4 Reserved */
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179 | uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
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180 | uint16_t TSTK:1; /*!< bit: 6 Test mode K */
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181 | uint16_t :1; /*!< bit: 7 Reserved */
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182 | uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
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183 | uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
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184 | uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
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185 | uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
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186 | uint16_t :4; /*!< bit: 12..15 Reserved */
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187 | } bit; /*!< Structure used for bit access */
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188 | uint16_t reg; /*!< Type used for register access */
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189 | } USB_HOST_CTRLB_Type;
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190 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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191 |
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192 | #define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
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193 | #define USB_HOST_CTRLB_RESETVALUE 0x0000 /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
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194 |
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195 | #define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
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196 | #define USB_HOST_CTRLB_RESUME (0x1u << USB_HOST_CTRLB_RESUME_Pos)
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197 | #define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
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198 | #define USB_HOST_CTRLB_SPDCONF_Msk (0x3u << USB_HOST_CTRLB_SPDCONF_Pos)
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199 | #define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)))
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200 | #define USB_HOST_CTRLB_SPDCONF_0_Val 0x0u /**< \brief (USB_HOST_CTRLB) Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheralis high-speed capable. */
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201 | #define USB_HOST_CTRLB_SPDCONF_1_Val 0x1u /**< \brief (USB_HOST_CTRLB) reserved */
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202 | #define USB_HOST_CTRLB_SPDCONF_2_Val 0x2u /**< \brief (USB_HOST_CTRLB) reserved */
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203 | #define USB_HOST_CTRLB_SPDCONF_3_Val 0x3u /**< \brief (USB_HOST_CTRLB) Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Releveant in UTMI mode only. */
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204 | #define USB_HOST_CTRLB_SPDCONF_0 (USB_HOST_CTRLB_SPDCONF_0_Val << USB_HOST_CTRLB_SPDCONF_Pos)
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205 | #define USB_HOST_CTRLB_SPDCONF_1 (USB_HOST_CTRLB_SPDCONF_1_Val << USB_HOST_CTRLB_SPDCONF_Pos)
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206 | #define USB_HOST_CTRLB_SPDCONF_2 (USB_HOST_CTRLB_SPDCONF_2_Val << USB_HOST_CTRLB_SPDCONF_Pos)
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207 | #define USB_HOST_CTRLB_SPDCONF_3 (USB_HOST_CTRLB_SPDCONF_3_Val << USB_HOST_CTRLB_SPDCONF_Pos)
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208 | #define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
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209 | #define USB_HOST_CTRLB_TSTJ (0x1u << USB_HOST_CTRLB_TSTJ_Pos)
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210 | #define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
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211 | #define USB_HOST_CTRLB_TSTK (0x1u << USB_HOST_CTRLB_TSTK_Pos)
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212 | #define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
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213 | #define USB_HOST_CTRLB_SOFE (0x1u << USB_HOST_CTRLB_SOFE_Pos)
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214 | #define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
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215 | #define USB_HOST_CTRLB_BUSRESET (0x1u << USB_HOST_CTRLB_BUSRESET_Pos)
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216 | #define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
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217 | #define USB_HOST_CTRLB_VBUSOK (0x1u << USB_HOST_CTRLB_VBUSOK_Pos)
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218 | #define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
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219 | #define USB_HOST_CTRLB_L1RESUME (0x1u << USB_HOST_CTRLB_L1RESUME_Pos)
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220 | #define USB_HOST_CTRLB_MASK 0x0F6Eu /**< \brief (USB_HOST_CTRLB) MASK Register */
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221 |
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222 | /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
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223 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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224 | typedef union {
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225 | struct {
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226 | uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
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227 | uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
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228 | } bit; /*!< Structure used for bit access */
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229 | uint8_t reg; /*!< Type used for register access */
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230 | } USB_DEVICE_DADD_Type;
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231 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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232 |
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233 | #define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
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234 | #define USB_DEVICE_DADD_RESETVALUE 0x00 /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
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235 |
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236 | #define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
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237 | #define USB_DEVICE_DADD_DADD_Msk (0x7Fu << USB_DEVICE_DADD_DADD_Pos)
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238 | #define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)))
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239 | #define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
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240 | #define USB_DEVICE_DADD_ADDEN (0x1u << USB_DEVICE_DADD_ADDEN_Pos)
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241 | #define USB_DEVICE_DADD_MASK 0xFFu /**< \brief (USB_DEVICE_DADD) MASK Register */
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242 |
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243 | /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
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244 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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245 | typedef union {
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246 | struct {
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247 | uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
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248 | uint8_t :3; /*!< bit: 4.. 6 Reserved */
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249 | uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
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250 | } bit; /*!< Structure used for bit access */
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251 | uint8_t reg; /*!< Type used for register access */
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252 | } USB_HOST_HSOFC_Type;
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253 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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254 |
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255 | #define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
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256 | #define USB_HOST_HSOFC_RESETVALUE 0x00 /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
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257 |
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258 | #define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
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259 | #define USB_HOST_HSOFC_FLENC_Msk (0xFu << USB_HOST_HSOFC_FLENC_Pos)
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260 | #define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)))
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261 | #define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
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262 | #define USB_HOST_HSOFC_FLENCE (0x1u << USB_HOST_HSOFC_FLENCE_Pos)
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263 | #define USB_HOST_HSOFC_MASK 0x8Fu /**< \brief (USB_HOST_HSOFC) MASK Register */
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264 |
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265 | /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
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266 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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267 | typedef union {
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268 | struct {
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269 | uint8_t :2; /*!< bit: 0.. 1 Reserved */
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270 | uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
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271 | uint8_t :2; /*!< bit: 4.. 5 Reserved */
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272 | uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
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273 | } bit; /*!< Structure used for bit access */
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274 | uint8_t reg; /*!< Type used for register access */
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275 | } USB_DEVICE_STATUS_Type;
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276 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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277 |
|
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278 | #define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
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279 | #define USB_DEVICE_STATUS_RESETVALUE 0x40 /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
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280 |
|
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281 | #define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
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282 | #define USB_DEVICE_STATUS_SPEED_Msk (0x3u << USB_DEVICE_STATUS_SPEED_Pos)
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283 | #define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)))
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284 | #define USB_DEVICE_STATUS_SPEED_0_Val 0x0u /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
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285 | #define USB_DEVICE_STATUS_SPEED_1_Val 0x1u /**< \brief (USB_DEVICE_STATUS) High-speed mode */
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286 | #define USB_DEVICE_STATUS_SPEED_2_Val 0x2u /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
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287 | #define USB_DEVICE_STATUS_SPEED_0 (USB_DEVICE_STATUS_SPEED_0_Val << USB_DEVICE_STATUS_SPEED_Pos)
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288 | #define USB_DEVICE_STATUS_SPEED_1 (USB_DEVICE_STATUS_SPEED_1_Val << USB_DEVICE_STATUS_SPEED_Pos)
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289 | #define USB_DEVICE_STATUS_SPEED_2 (USB_DEVICE_STATUS_SPEED_2_Val << USB_DEVICE_STATUS_SPEED_Pos)
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290 | #define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
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291 | #define USB_DEVICE_STATUS_LINESTATE_Msk (0x3u << USB_DEVICE_STATUS_LINESTATE_Pos)
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292 | #define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)))
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293 | #define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0u /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
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294 | #define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1u /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
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295 | #define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2u /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
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296 | #define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
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297 | #define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
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298 | #define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
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299 | #define USB_DEVICE_STATUS_MASK 0xCCu /**< \brief (USB_DEVICE_STATUS) MASK Register */
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300 |
|
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301 | /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
|
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302 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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303 | typedef union {
|
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304 | struct {
|
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305 | uint8_t :2; /*!< bit: 0.. 1 Reserved */
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306 | uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
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307 | uint8_t :2; /*!< bit: 4.. 5 Reserved */
|
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308 | uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
|
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309 | } bit; /*!< Structure used for bit access */
|
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310 | uint8_t reg; /*!< Type used for register access */
|
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311 | } USB_HOST_STATUS_Type;
|
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312 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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313 |
|
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314 | #define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
|
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315 | #define USB_HOST_STATUS_RESETVALUE 0x00 /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
|
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316 |
|
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317 | #define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
|
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318 | #define USB_HOST_STATUS_SPEED_Msk (0x3u << USB_HOST_STATUS_SPEED_Pos)
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319 | #define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)))
|
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320 | #define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
|
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321 | #define USB_HOST_STATUS_LINESTATE_Msk (0x3u << USB_HOST_STATUS_LINESTATE_Pos)
|
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322 | #define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)))
|
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323 | #define USB_HOST_STATUS_MASK 0xCCu /**< \brief (USB_HOST_STATUS) MASK Register */
|
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324 |
|
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325 | /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
|
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326 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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327 | typedef union {
|
---|
328 | struct {
|
---|
329 | uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
|
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330 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
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331 | } bit; /*!< Structure used for bit access */
|
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332 | uint8_t reg; /*!< Type used for register access */
|
---|
333 | } USB_FSMSTATUS_Type;
|
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334 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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335 |
|
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336 | #define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
|
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337 | #define USB_FSMSTATUS_RESETVALUE 0x01 /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
|
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338 |
|
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339 | #define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
|
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340 | #define USB_FSMSTATUS_FSMSTATE_Msk (0x3Fu << USB_FSMSTATUS_FSMSTATE_Pos)
|
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341 | #define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)))
|
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342 | #define USB_FSMSTATUS_FSMSTATE_1_Val 0x1u /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
|
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343 | #define USB_FSMSTATUS_FSMSTATE_2_Val 0x2u /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
|
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344 | #define USB_FSMSTATUS_FSMSTATE_4_Val 0x4u /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
|
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345 | #define USB_FSMSTATUS_FSMSTATE_8_Val 0x8u /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
|
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346 | #define USB_FSMSTATUS_FSMSTATE_16_Val 0x10u /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
|
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347 | #define USB_FSMSTATUS_FSMSTATE_32_Val 0x20u /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
|
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348 | #define USB_FSMSTATUS_FSMSTATE_64_Val 0x40u /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
|
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349 | #define USB_FSMSTATUS_FSMSTATE_1 (USB_FSMSTATUS_FSMSTATE_1_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
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350 | #define USB_FSMSTATUS_FSMSTATE_2 (USB_FSMSTATUS_FSMSTATE_2_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
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351 | #define USB_FSMSTATUS_FSMSTATE_4 (USB_FSMSTATUS_FSMSTATE_4_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
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352 | #define USB_FSMSTATUS_FSMSTATE_8 (USB_FSMSTATUS_FSMSTATE_8_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
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353 | #define USB_FSMSTATUS_FSMSTATE_16 (USB_FSMSTATUS_FSMSTATE_16_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
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354 | #define USB_FSMSTATUS_FSMSTATE_32 (USB_FSMSTATUS_FSMSTATE_32_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
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355 | #define USB_FSMSTATUS_FSMSTATE_64 (USB_FSMSTATUS_FSMSTATE_64_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
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356 | #define USB_FSMSTATUS_MASK 0x3Fu /**< \brief (USB_FSMSTATUS) MASK Register */
|
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357 |
|
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358 | /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
|
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359 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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360 | typedef union {
|
---|
361 | struct {
|
---|
362 | uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
|
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363 | uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
|
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364 | uint16_t :1; /*!< bit: 14 Reserved */
|
---|
365 | uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
|
---|
366 | } bit; /*!< Structure used for bit access */
|
---|
367 | uint16_t reg; /*!< Type used for register access */
|
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368 | } USB_DEVICE_FNUM_Type;
|
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369 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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370 |
|
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371 | #define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
|
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372 | #define USB_DEVICE_FNUM_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
|
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373 |
|
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374 | #define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
|
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375 | #define USB_DEVICE_FNUM_MFNUM_Msk (0x7u << USB_DEVICE_FNUM_MFNUM_Pos)
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376 | #define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)))
|
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377 | #define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
|
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378 | #define USB_DEVICE_FNUM_FNUM_Msk (0x7FFu << USB_DEVICE_FNUM_FNUM_Pos)
|
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379 | #define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)))
|
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380 | #define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
|
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381 | #define USB_DEVICE_FNUM_FNCERR (0x1u << USB_DEVICE_FNUM_FNCERR_Pos)
|
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382 | #define USB_DEVICE_FNUM_MASK 0xBFFFu /**< \brief (USB_DEVICE_FNUM) MASK Register */
|
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383 |
|
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384 | /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
|
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385 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
386 | typedef union {
|
---|
387 | struct {
|
---|
388 | uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
|
---|
389 | uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
|
---|
390 | uint16_t :2; /*!< bit: 14..15 Reserved */
|
---|
391 | } bit; /*!< Structure used for bit access */
|
---|
392 | uint16_t reg; /*!< Type used for register access */
|
---|
393 | } USB_HOST_FNUM_Type;
|
---|
394 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
395 |
|
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396 | #define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
|
---|
397 | #define USB_HOST_FNUM_RESETVALUE 0x0000 /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
|
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398 |
|
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399 | #define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
|
---|
400 | #define USB_HOST_FNUM_MFNUM_Msk (0x7u << USB_HOST_FNUM_MFNUM_Pos)
|
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401 | #define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)))
|
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402 | #define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
|
---|
403 | #define USB_HOST_FNUM_FNUM_Msk (0x7FFu << USB_HOST_FNUM_FNUM_Pos)
|
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404 | #define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)))
|
---|
405 | #define USB_HOST_FNUM_MASK 0x3FFFu /**< \brief (USB_HOST_FNUM) MASK Register */
|
---|
406 |
|
---|
407 | /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
|
---|
408 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
409 | typedef union {
|
---|
410 | struct {
|
---|
411 | uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
|
---|
412 | } bit; /*!< Structure used for bit access */
|
---|
413 | uint8_t reg; /*!< Type used for register access */
|
---|
414 | } USB_HOST_FLENHIGH_Type;
|
---|
415 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
416 |
|
---|
417 | #define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
|
---|
418 | #define USB_HOST_FLENHIGH_RESETVALUE 0x00 /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
|
---|
419 |
|
---|
420 | #define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
|
---|
421 | #define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFu << USB_HOST_FLENHIGH_FLENHIGH_Pos)
|
---|
422 | #define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)))
|
---|
423 | #define USB_HOST_FLENHIGH_MASK 0xFFu /**< \brief (USB_HOST_FLENHIGH) MASK Register */
|
---|
424 |
|
---|
425 | /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
|
---|
426 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
427 | typedef union {
|
---|
428 | struct {
|
---|
429 | uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
|
---|
430 | uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
|
---|
431 | uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
|
---|
432 | uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
|
---|
433 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
|
---|
434 | uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
|
---|
435 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
|
---|
436 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
|
---|
437 | uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
|
---|
438 | uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
|
---|
439 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
---|
440 | } bit; /*!< Structure used for bit access */
|
---|
441 | uint16_t reg; /*!< Type used for register access */
|
---|
442 | } USB_DEVICE_INTENCLR_Type;
|
---|
443 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
444 |
|
---|
445 | #define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
|
---|
446 | #define USB_DEVICE_INTENCLR_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
|
---|
447 |
|
---|
448 | #define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
|
---|
449 | #define USB_DEVICE_INTENCLR_SUSPEND (0x1u << USB_DEVICE_INTENCLR_SUSPEND_Pos)
|
---|
450 | #define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
|
---|
451 | #define USB_DEVICE_INTENCLR_MSOF (0x1u << USB_DEVICE_INTENCLR_MSOF_Pos)
|
---|
452 | #define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
|
---|
453 | #define USB_DEVICE_INTENCLR_SOF (0x1u << USB_DEVICE_INTENCLR_SOF_Pos)
|
---|
454 | #define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
|
---|
455 | #define USB_DEVICE_INTENCLR_EORST (0x1u << USB_DEVICE_INTENCLR_EORST_Pos)
|
---|
456 | #define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
|
---|
457 | #define USB_DEVICE_INTENCLR_WAKEUP (0x1u << USB_DEVICE_INTENCLR_WAKEUP_Pos)
|
---|
458 | #define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
|
---|
459 | #define USB_DEVICE_INTENCLR_EORSM (0x1u << USB_DEVICE_INTENCLR_EORSM_Pos)
|
---|
460 | #define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
|
---|
461 | #define USB_DEVICE_INTENCLR_UPRSM (0x1u << USB_DEVICE_INTENCLR_UPRSM_Pos)
|
---|
462 | #define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
|
---|
463 | #define USB_DEVICE_INTENCLR_RAMACER (0x1u << USB_DEVICE_INTENCLR_RAMACER_Pos)
|
---|
464 | #define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
|
---|
465 | #define USB_DEVICE_INTENCLR_LPMNYET (0x1u << USB_DEVICE_INTENCLR_LPMNYET_Pos)
|
---|
466 | #define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
|
---|
467 | #define USB_DEVICE_INTENCLR_LPMSUSP (0x1u << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
|
---|
468 | #define USB_DEVICE_INTENCLR_MASK 0x03FFu /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
|
---|
469 |
|
---|
470 | /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
|
---|
471 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
472 | typedef union {
|
---|
473 | struct {
|
---|
474 | uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
---|
475 | uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
|
---|
476 | uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
|
---|
477 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
|
---|
478 | uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
|
---|
479 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
|
---|
480 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
|
---|
481 | uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
|
---|
482 | uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
|
---|
483 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
---|
484 | } bit; /*!< Structure used for bit access */
|
---|
485 | uint16_t reg; /*!< Type used for register access */
|
---|
486 | } USB_HOST_INTENCLR_Type;
|
---|
487 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
488 |
|
---|
489 | #define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
|
---|
490 | #define USB_HOST_INTENCLR_RESETVALUE 0x0000 /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
|
---|
491 |
|
---|
492 | #define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
|
---|
493 | #define USB_HOST_INTENCLR_HSOF (0x1u << USB_HOST_INTENCLR_HSOF_Pos)
|
---|
494 | #define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
|
---|
495 | #define USB_HOST_INTENCLR_RST (0x1u << USB_HOST_INTENCLR_RST_Pos)
|
---|
496 | #define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
|
---|
497 | #define USB_HOST_INTENCLR_WAKEUP (0x1u << USB_HOST_INTENCLR_WAKEUP_Pos)
|
---|
498 | #define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
|
---|
499 | #define USB_HOST_INTENCLR_DNRSM (0x1u << USB_HOST_INTENCLR_DNRSM_Pos)
|
---|
500 | #define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
|
---|
501 | #define USB_HOST_INTENCLR_UPRSM (0x1u << USB_HOST_INTENCLR_UPRSM_Pos)
|
---|
502 | #define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
|
---|
503 | #define USB_HOST_INTENCLR_RAMACER (0x1u << USB_HOST_INTENCLR_RAMACER_Pos)
|
---|
504 | #define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
|
---|
505 | #define USB_HOST_INTENCLR_DCONN (0x1u << USB_HOST_INTENCLR_DCONN_Pos)
|
---|
506 | #define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
|
---|
507 | #define USB_HOST_INTENCLR_DDISC (0x1u << USB_HOST_INTENCLR_DDISC_Pos)
|
---|
508 | #define USB_HOST_INTENCLR_MASK 0x03FCu /**< \brief (USB_HOST_INTENCLR) MASK Register */
|
---|
509 |
|
---|
510 | /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
|
---|
511 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
512 | typedef union {
|
---|
513 | struct {
|
---|
514 | uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
|
---|
515 | uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
|
---|
516 | uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
|
---|
517 | uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
|
---|
518 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
|
---|
519 | uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
|
---|
520 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
|
---|
521 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
|
---|
522 | uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
|
---|
523 | uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
|
---|
524 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
---|
525 | } bit; /*!< Structure used for bit access */
|
---|
526 | uint16_t reg; /*!< Type used for register access */
|
---|
527 | } USB_DEVICE_INTENSET_Type;
|
---|
528 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
529 |
|
---|
530 | #define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
|
---|
531 | #define USB_DEVICE_INTENSET_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
|
---|
532 |
|
---|
533 | #define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
|
---|
534 | #define USB_DEVICE_INTENSET_SUSPEND (0x1u << USB_DEVICE_INTENSET_SUSPEND_Pos)
|
---|
535 | #define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
|
---|
536 | #define USB_DEVICE_INTENSET_MSOF (0x1u << USB_DEVICE_INTENSET_MSOF_Pos)
|
---|
537 | #define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
|
---|
538 | #define USB_DEVICE_INTENSET_SOF (0x1u << USB_DEVICE_INTENSET_SOF_Pos)
|
---|
539 | #define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
|
---|
540 | #define USB_DEVICE_INTENSET_EORST (0x1u << USB_DEVICE_INTENSET_EORST_Pos)
|
---|
541 | #define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
|
---|
542 | #define USB_DEVICE_INTENSET_WAKEUP (0x1u << USB_DEVICE_INTENSET_WAKEUP_Pos)
|
---|
543 | #define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
|
---|
544 | #define USB_DEVICE_INTENSET_EORSM (0x1u << USB_DEVICE_INTENSET_EORSM_Pos)
|
---|
545 | #define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
|
---|
546 | #define USB_DEVICE_INTENSET_UPRSM (0x1u << USB_DEVICE_INTENSET_UPRSM_Pos)
|
---|
547 | #define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
|
---|
548 | #define USB_DEVICE_INTENSET_RAMACER (0x1u << USB_DEVICE_INTENSET_RAMACER_Pos)
|
---|
549 | #define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
|
---|
550 | #define USB_DEVICE_INTENSET_LPMNYET (0x1u << USB_DEVICE_INTENSET_LPMNYET_Pos)
|
---|
551 | #define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
|
---|
552 | #define USB_DEVICE_INTENSET_LPMSUSP (0x1u << USB_DEVICE_INTENSET_LPMSUSP_Pos)
|
---|
553 | #define USB_DEVICE_INTENSET_MASK 0x03FFu /**< \brief (USB_DEVICE_INTENSET) MASK Register */
|
---|
554 |
|
---|
555 | /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
|
---|
556 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
557 | typedef union {
|
---|
558 | struct {
|
---|
559 | uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
---|
560 | uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
|
---|
561 | uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
|
---|
562 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
|
---|
563 | uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
|
---|
564 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
|
---|
565 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
|
---|
566 | uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
|
---|
567 | uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
|
---|
568 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
---|
569 | } bit; /*!< Structure used for bit access */
|
---|
570 | uint16_t reg; /*!< Type used for register access */
|
---|
571 | } USB_HOST_INTENSET_Type;
|
---|
572 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
573 |
|
---|
574 | #define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
|
---|
575 | #define USB_HOST_INTENSET_RESETVALUE 0x0000 /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
|
---|
576 |
|
---|
577 | #define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
|
---|
578 | #define USB_HOST_INTENSET_HSOF (0x1u << USB_HOST_INTENSET_HSOF_Pos)
|
---|
579 | #define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
|
---|
580 | #define USB_HOST_INTENSET_RST (0x1u << USB_HOST_INTENSET_RST_Pos)
|
---|
581 | #define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
|
---|
582 | #define USB_HOST_INTENSET_WAKEUP (0x1u << USB_HOST_INTENSET_WAKEUP_Pos)
|
---|
583 | #define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
|
---|
584 | #define USB_HOST_INTENSET_DNRSM (0x1u << USB_HOST_INTENSET_DNRSM_Pos)
|
---|
585 | #define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
|
---|
586 | #define USB_HOST_INTENSET_UPRSM (0x1u << USB_HOST_INTENSET_UPRSM_Pos)
|
---|
587 | #define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
|
---|
588 | #define USB_HOST_INTENSET_RAMACER (0x1u << USB_HOST_INTENSET_RAMACER_Pos)
|
---|
589 | #define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
|
---|
590 | #define USB_HOST_INTENSET_DCONN (0x1u << USB_HOST_INTENSET_DCONN_Pos)
|
---|
591 | #define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
|
---|
592 | #define USB_HOST_INTENSET_DDISC (0x1u << USB_HOST_INTENSET_DDISC_Pos)
|
---|
593 | #define USB_HOST_INTENSET_MASK 0x03FCu /**< \brief (USB_HOST_INTENSET) MASK Register */
|
---|
594 |
|
---|
595 | /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
|
---|
596 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
597 | typedef union {
|
---|
598 | struct {
|
---|
599 | uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
|
---|
600 | uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
|
---|
601 | uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
|
---|
602 | uint16_t EORST:1; /*!< bit: 3 End of Reset */
|
---|
603 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
|
---|
604 | uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
|
---|
605 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
|
---|
606 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
|
---|
607 | uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
|
---|
608 | uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
|
---|
609 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
---|
610 | } bit; /*!< Structure used for bit access */
|
---|
611 | uint16_t reg; /*!< Type used for register access */
|
---|
612 | } USB_DEVICE_INTFLAG_Type;
|
---|
613 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
614 |
|
---|
615 | #define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
|
---|
616 | #define USB_DEVICE_INTFLAG_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
|
---|
617 |
|
---|
618 | #define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
|
---|
619 | #define USB_DEVICE_INTFLAG_SUSPEND (0x1u << USB_DEVICE_INTFLAG_SUSPEND_Pos)
|
---|
620 | #define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
|
---|
621 | #define USB_DEVICE_INTFLAG_MSOF (0x1u << USB_DEVICE_INTFLAG_MSOF_Pos)
|
---|
622 | #define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
|
---|
623 | #define USB_DEVICE_INTFLAG_SOF (0x1u << USB_DEVICE_INTFLAG_SOF_Pos)
|
---|
624 | #define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
|
---|
625 | #define USB_DEVICE_INTFLAG_EORST (0x1u << USB_DEVICE_INTFLAG_EORST_Pos)
|
---|
626 | #define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
|
---|
627 | #define USB_DEVICE_INTFLAG_WAKEUP (0x1u << USB_DEVICE_INTFLAG_WAKEUP_Pos)
|
---|
628 | #define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
|
---|
629 | #define USB_DEVICE_INTFLAG_EORSM (0x1u << USB_DEVICE_INTFLAG_EORSM_Pos)
|
---|
630 | #define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
|
---|
631 | #define USB_DEVICE_INTFLAG_UPRSM (0x1u << USB_DEVICE_INTFLAG_UPRSM_Pos)
|
---|
632 | #define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
|
---|
633 | #define USB_DEVICE_INTFLAG_RAMACER (0x1u << USB_DEVICE_INTFLAG_RAMACER_Pos)
|
---|
634 | #define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
|
---|
635 | #define USB_DEVICE_INTFLAG_LPMNYET (0x1u << USB_DEVICE_INTFLAG_LPMNYET_Pos)
|
---|
636 | #define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
|
---|
637 | #define USB_DEVICE_INTFLAG_LPMSUSP (0x1u << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
|
---|
638 | #define USB_DEVICE_INTFLAG_MASK 0x03FFu /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
|
---|
639 |
|
---|
640 | /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
|
---|
641 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
642 | typedef union {
|
---|
643 | struct {
|
---|
644 | uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
---|
645 | uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
|
---|
646 | uint16_t RST:1; /*!< bit: 3 Bus Reset */
|
---|
647 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
|
---|
648 | uint16_t DNRSM:1; /*!< bit: 5 Downstream */
|
---|
649 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
|
---|
650 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
|
---|
651 | uint16_t DCONN:1; /*!< bit: 8 Device Connection */
|
---|
652 | uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
|
---|
653 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
---|
654 | } bit; /*!< Structure used for bit access */
|
---|
655 | uint16_t reg; /*!< Type used for register access */
|
---|
656 | } USB_HOST_INTFLAG_Type;
|
---|
657 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
658 |
|
---|
659 | #define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
|
---|
660 | #define USB_HOST_INTFLAG_RESETVALUE 0x0000 /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
|
---|
661 |
|
---|
662 | #define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
|
---|
663 | #define USB_HOST_INTFLAG_HSOF (0x1u << USB_HOST_INTFLAG_HSOF_Pos)
|
---|
664 | #define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
|
---|
665 | #define USB_HOST_INTFLAG_RST (0x1u << USB_HOST_INTFLAG_RST_Pos)
|
---|
666 | #define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
|
---|
667 | #define USB_HOST_INTFLAG_WAKEUP (0x1u << USB_HOST_INTFLAG_WAKEUP_Pos)
|
---|
668 | #define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
|
---|
669 | #define USB_HOST_INTFLAG_DNRSM (0x1u << USB_HOST_INTFLAG_DNRSM_Pos)
|
---|
670 | #define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
|
---|
671 | #define USB_HOST_INTFLAG_UPRSM (0x1u << USB_HOST_INTFLAG_UPRSM_Pos)
|
---|
672 | #define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
|
---|
673 | #define USB_HOST_INTFLAG_RAMACER (0x1u << USB_HOST_INTFLAG_RAMACER_Pos)
|
---|
674 | #define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
|
---|
675 | #define USB_HOST_INTFLAG_DCONN (0x1u << USB_HOST_INTFLAG_DCONN_Pos)
|
---|
676 | #define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
|
---|
677 | #define USB_HOST_INTFLAG_DDISC (0x1u << USB_HOST_INTFLAG_DDISC_Pos)
|
---|
678 | #define USB_HOST_INTFLAG_MASK 0x03FCu /**< \brief (USB_HOST_INTFLAG) MASK Register */
|
---|
679 |
|
---|
680 | /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
|
---|
681 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
682 | typedef union {
|
---|
683 | struct {
|
---|
684 | uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
|
---|
685 | uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
|
---|
686 | uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
|
---|
687 | uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
|
---|
688 | uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
|
---|
689 | uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
|
---|
690 | uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
|
---|
691 | uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
|
---|
692 | uint16_t :8; /*!< bit: 8..15 Reserved */
|
---|
693 | } bit; /*!< Structure used for bit access */
|
---|
694 | struct {
|
---|
695 | uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
|
---|
696 | uint16_t :8; /*!< bit: 8..15 Reserved */
|
---|
697 | } vec; /*!< Structure used for vec access */
|
---|
698 | uint16_t reg; /*!< Type used for register access */
|
---|
699 | } USB_DEVICE_EPINTSMRY_Type;
|
---|
700 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
701 |
|
---|
702 | #define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
|
---|
703 | #define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
|
---|
704 |
|
---|
705 | #define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
|
---|
706 | #define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
|
---|
707 | #define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
|
---|
708 | #define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
|
---|
709 | #define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
|
---|
710 | #define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
|
---|
711 | #define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
|
---|
712 | #define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
|
---|
713 | #define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
|
---|
714 | #define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
|
---|
715 | #define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
|
---|
716 | #define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
|
---|
717 | #define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
|
---|
718 | #define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
|
---|
719 | #define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
|
---|
720 | #define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
|
---|
721 | #define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
|
---|
722 | #define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFu << USB_DEVICE_EPINTSMRY_EPINT_Pos)
|
---|
723 | #define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)))
|
---|
724 | #define USB_DEVICE_EPINTSMRY_MASK 0x00FFu /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
|
---|
725 |
|
---|
726 | /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
|
---|
727 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
728 | typedef union {
|
---|
729 | struct {
|
---|
730 | uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
|
---|
731 | uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
|
---|
732 | uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
|
---|
733 | uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
|
---|
734 | uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
|
---|
735 | uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
|
---|
736 | uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
|
---|
737 | uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
|
---|
738 | uint16_t :8; /*!< bit: 8..15 Reserved */
|
---|
739 | } bit; /*!< Structure used for bit access */
|
---|
740 | struct {
|
---|
741 | uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
|
---|
742 | uint16_t :8; /*!< bit: 8..15 Reserved */
|
---|
743 | } vec; /*!< Structure used for vec access */
|
---|
744 | uint16_t reg; /*!< Type used for register access */
|
---|
745 | } USB_HOST_PINTSMRY_Type;
|
---|
746 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
747 |
|
---|
748 | #define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
|
---|
749 | #define USB_HOST_PINTSMRY_RESETVALUE 0x0000 /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
|
---|
750 |
|
---|
751 | #define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
|
---|
752 | #define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
|
---|
753 | #define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
|
---|
754 | #define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
|
---|
755 | #define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
|
---|
756 | #define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
|
---|
757 | #define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
|
---|
758 | #define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
|
---|
759 | #define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
|
---|
760 | #define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
|
---|
761 | #define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
|
---|
762 | #define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
|
---|
763 | #define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
|
---|
764 | #define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
|
---|
765 | #define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
|
---|
766 | #define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
|
---|
767 | #define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
|
---|
768 | #define USB_HOST_PINTSMRY_EPINT_Msk (0xFFu << USB_HOST_PINTSMRY_EPINT_Pos)
|
---|
769 | #define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)))
|
---|
770 | #define USB_HOST_PINTSMRY_MASK 0x00FFu /**< \brief (USB_HOST_PINTSMRY) MASK Register */
|
---|
771 |
|
---|
772 | /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
|
---|
773 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
774 | typedef union {
|
---|
775 | struct {
|
---|
776 | uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
|
---|
777 | } bit; /*!< Structure used for bit access */
|
---|
778 | uint32_t reg; /*!< Type used for register access */
|
---|
779 | } USB_DESCADD_Type;
|
---|
780 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
781 |
|
---|
782 | #define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
|
---|
783 | #define USB_DESCADD_RESETVALUE 0x00000000 /**< \brief (USB_DESCADD reset_value) Descriptor Address */
|
---|
784 |
|
---|
785 | #define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
|
---|
786 | #define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFu << USB_DESCADD_DESCADD_Pos)
|
---|
787 | #define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)))
|
---|
788 | #define USB_DESCADD_MASK 0xFFFFFFFFu /**< \brief (USB_DESCADD) MASK Register */
|
---|
789 |
|
---|
790 | /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
|
---|
791 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
792 | typedef union {
|
---|
793 | struct {
|
---|
794 | uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
|
---|
795 | uint16_t :1; /*!< bit: 5 Reserved */
|
---|
796 | uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
|
---|
797 | uint16_t :1; /*!< bit: 11 Reserved */
|
---|
798 | uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
|
---|
799 | uint16_t :1; /*!< bit: 15 Reserved */
|
---|
800 | } bit; /*!< Structure used for bit access */
|
---|
801 | uint16_t reg; /*!< Type used for register access */
|
---|
802 | } USB_PADCAL_Type;
|
---|
803 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
804 |
|
---|
805 | #define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
|
---|
806 | #define USB_PADCAL_RESETVALUE 0x0000 /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
|
---|
807 |
|
---|
808 | #define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
|
---|
809 | #define USB_PADCAL_TRANSP_Msk (0x1Fu << USB_PADCAL_TRANSP_Pos)
|
---|
810 | #define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)))
|
---|
811 | #define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
|
---|
812 | #define USB_PADCAL_TRANSN_Msk (0x1Fu << USB_PADCAL_TRANSN_Pos)
|
---|
813 | #define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)))
|
---|
814 | #define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
|
---|
815 | #define USB_PADCAL_TRIM_Msk (0x7u << USB_PADCAL_TRIM_Pos)
|
---|
816 | #define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)))
|
---|
817 | #define USB_PADCAL_MASK 0x77DFu /**< \brief (USB_PADCAL) MASK Register */
|
---|
818 |
|
---|
819 | /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
|
---|
820 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
821 | typedef union {
|
---|
822 | struct {
|
---|
823 | uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
|
---|
824 | uint8_t :1; /*!< bit: 3 Reserved */
|
---|
825 | uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
|
---|
826 | uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
|
---|
827 | } bit; /*!< Structure used for bit access */
|
---|
828 | uint8_t reg; /*!< Type used for register access */
|
---|
829 | } USB_DEVICE_EPCFG_Type;
|
---|
830 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
831 |
|
---|
832 | #define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
|
---|
833 | #define USB_DEVICE_EPCFG_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
|
---|
834 |
|
---|
835 | #define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
|
---|
836 | #define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7u << USB_DEVICE_EPCFG_EPTYPE0_Pos)
|
---|
837 | #define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)))
|
---|
838 | #define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
|
---|
839 | #define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7u << USB_DEVICE_EPCFG_EPTYPE1_Pos)
|
---|
840 | #define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)))
|
---|
841 | #define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
|
---|
842 | #define USB_DEVICE_EPCFG_NYETDIS (0x1u << USB_DEVICE_EPCFG_NYETDIS_Pos)
|
---|
843 | #define USB_DEVICE_EPCFG_MASK 0xF7u /**< \brief (USB_DEVICE_EPCFG) MASK Register */
|
---|
844 |
|
---|
845 | /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
|
---|
846 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
847 | typedef union {
|
---|
848 | struct {
|
---|
849 | uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
|
---|
850 | uint8_t BK:1; /*!< bit: 2 Pipe Bank */
|
---|
851 | uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
|
---|
852 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
853 | } bit; /*!< Structure used for bit access */
|
---|
854 | uint8_t reg; /*!< Type used for register access */
|
---|
855 | } USB_HOST_PCFG_Type;
|
---|
856 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
857 |
|
---|
858 | #define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
|
---|
859 | #define USB_HOST_PCFG_RESETVALUE 0x00 /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
|
---|
860 |
|
---|
861 | #define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
|
---|
862 | #define USB_HOST_PCFG_PTOKEN_Msk (0x3u << USB_HOST_PCFG_PTOKEN_Pos)
|
---|
863 | #define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)))
|
---|
864 | #define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
|
---|
865 | #define USB_HOST_PCFG_BK (0x1u << USB_HOST_PCFG_BK_Pos)
|
---|
866 | #define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
|
---|
867 | #define USB_HOST_PCFG_PTYPE_Msk (0x7u << USB_HOST_PCFG_PTYPE_Pos)
|
---|
868 | #define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)))
|
---|
869 | #define USB_HOST_PCFG_MASK 0x3Fu /**< \brief (USB_HOST_PCFG) MASK Register */
|
---|
870 |
|
---|
871 | /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
|
---|
872 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
873 | typedef union {
|
---|
874 | struct {
|
---|
875 | uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
|
---|
876 | } bit; /*!< Structure used for bit access */
|
---|
877 | uint8_t reg; /*!< Type used for register access */
|
---|
878 | } USB_HOST_BINTERVAL_Type;
|
---|
879 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
880 |
|
---|
881 | #define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
|
---|
882 | #define USB_HOST_BINTERVAL_RESETVALUE 0x00 /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
|
---|
883 |
|
---|
884 | #define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
|
---|
885 | #define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFu << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
|
---|
886 | #define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)))
|
---|
887 | #define USB_HOST_BINTERVAL_MASK 0xFFu /**< \brief (USB_HOST_BINTERVAL) MASK Register */
|
---|
888 |
|
---|
889 | /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
|
---|
890 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
891 | typedef union {
|
---|
892 | struct {
|
---|
893 | uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
|
---|
894 | uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
|
---|
895 | uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
|
---|
896 | uint8_t :1; /*!< bit: 3 Reserved */
|
---|
897 | uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
|
---|
898 | uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
|
---|
899 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
|
---|
900 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
|
---|
901 | } bit; /*!< Structure used for bit access */
|
---|
902 | struct {
|
---|
903 | uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
---|
904 | uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
|
---|
905 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
906 | } vec; /*!< Structure used for vec access */
|
---|
907 | uint8_t reg; /*!< Type used for register access */
|
---|
908 | } USB_DEVICE_EPSTATUSCLR_Type;
|
---|
909 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
910 |
|
---|
911 | #define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
|
---|
912 | #define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
|
---|
913 |
|
---|
914 | #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
|
---|
915 | #define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1u << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
|
---|
916 | #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
|
---|
917 | #define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1u << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
|
---|
918 | #define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
|
---|
919 | #define USB_DEVICE_EPSTATUSCLR_CURBK (0x1u << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
|
---|
920 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
|
---|
921 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
|
---|
922 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
|
---|
923 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
|
---|
924 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
|
---|
925 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3u << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
|
---|
926 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)))
|
---|
927 | #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
|
---|
928 | #define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1u << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
|
---|
929 | #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
|
---|
930 | #define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1u << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
|
---|
931 | #define USB_DEVICE_EPSTATUSCLR_MASK 0xF7u /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
|
---|
932 |
|
---|
933 | /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
|
---|
934 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
935 | typedef union {
|
---|
936 | struct {
|
---|
937 | uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
|
---|
938 | uint8_t :1; /*!< bit: 1 Reserved */
|
---|
939 | uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
|
---|
940 | uint8_t :1; /*!< bit: 3 Reserved */
|
---|
941 | uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
|
---|
942 | uint8_t :1; /*!< bit: 5 Reserved */
|
---|
943 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
|
---|
944 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
|
---|
945 | } bit; /*!< Structure used for bit access */
|
---|
946 | uint8_t reg; /*!< Type used for register access */
|
---|
947 | } USB_HOST_PSTATUSCLR_Type;
|
---|
948 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
949 |
|
---|
950 | #define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
|
---|
951 | #define USB_HOST_PSTATUSCLR_RESETVALUE 0x00 /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
|
---|
952 |
|
---|
953 | #define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
|
---|
954 | #define USB_HOST_PSTATUSCLR_DTGL (0x1u << USB_HOST_PSTATUSCLR_DTGL_Pos)
|
---|
955 | #define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
|
---|
956 | #define USB_HOST_PSTATUSCLR_CURBK (0x1u << USB_HOST_PSTATUSCLR_CURBK_Pos)
|
---|
957 | #define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
|
---|
958 | #define USB_HOST_PSTATUSCLR_PFREEZE (0x1u << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
|
---|
959 | #define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
|
---|
960 | #define USB_HOST_PSTATUSCLR_BK0RDY (0x1u << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
|
---|
961 | #define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
|
---|
962 | #define USB_HOST_PSTATUSCLR_BK1RDY (0x1u << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
|
---|
963 | #define USB_HOST_PSTATUSCLR_MASK 0xD5u /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
|
---|
964 |
|
---|
965 | /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
|
---|
966 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
967 | typedef union {
|
---|
968 | struct {
|
---|
969 | uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
|
---|
970 | uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
|
---|
971 | uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
|
---|
972 | uint8_t :1; /*!< bit: 3 Reserved */
|
---|
973 | uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
|
---|
974 | uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
|
---|
975 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
|
---|
976 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
|
---|
977 | } bit; /*!< Structure used for bit access */
|
---|
978 | struct {
|
---|
979 | uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
---|
980 | uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
|
---|
981 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
982 | } vec; /*!< Structure used for vec access */
|
---|
983 | uint8_t reg; /*!< Type used for register access */
|
---|
984 | } USB_DEVICE_EPSTATUSSET_Type;
|
---|
985 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
986 |
|
---|
987 | #define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
|
---|
988 | #define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
|
---|
989 |
|
---|
990 | #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
|
---|
991 | #define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1u << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
|
---|
992 | #define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
|
---|
993 | #define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1u << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
|
---|
994 | #define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
|
---|
995 | #define USB_DEVICE_EPSTATUSSET_CURBK (0x1u << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
|
---|
996 | #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
|
---|
997 | #define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
|
---|
998 | #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
|
---|
999 | #define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
|
---|
1000 | #define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
|
---|
1001 | #define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3u << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
|
---|
1002 | #define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)))
|
---|
1003 | #define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
|
---|
1004 | #define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1u << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
|
---|
1005 | #define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
|
---|
1006 | #define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1u << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
|
---|
1007 | #define USB_DEVICE_EPSTATUSSET_MASK 0xF7u /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
|
---|
1008 |
|
---|
1009 | /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
|
---|
1010 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1011 | typedef union {
|
---|
1012 | struct {
|
---|
1013 | uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
|
---|
1014 | uint8_t :1; /*!< bit: 1 Reserved */
|
---|
1015 | uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
|
---|
1016 | uint8_t :1; /*!< bit: 3 Reserved */
|
---|
1017 | uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
|
---|
1018 | uint8_t :1; /*!< bit: 5 Reserved */
|
---|
1019 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
|
---|
1020 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
|
---|
1021 | } bit; /*!< Structure used for bit access */
|
---|
1022 | uint8_t reg; /*!< Type used for register access */
|
---|
1023 | } USB_HOST_PSTATUSSET_Type;
|
---|
1024 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1025 |
|
---|
1026 | #define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
|
---|
1027 | #define USB_HOST_PSTATUSSET_RESETVALUE 0x00 /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
|
---|
1028 |
|
---|
1029 | #define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
|
---|
1030 | #define USB_HOST_PSTATUSSET_DTGL (0x1u << USB_HOST_PSTATUSSET_DTGL_Pos)
|
---|
1031 | #define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
|
---|
1032 | #define USB_HOST_PSTATUSSET_CURBK (0x1u << USB_HOST_PSTATUSSET_CURBK_Pos)
|
---|
1033 | #define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
|
---|
1034 | #define USB_HOST_PSTATUSSET_PFREEZE (0x1u << USB_HOST_PSTATUSSET_PFREEZE_Pos)
|
---|
1035 | #define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
|
---|
1036 | #define USB_HOST_PSTATUSSET_BK0RDY (0x1u << USB_HOST_PSTATUSSET_BK0RDY_Pos)
|
---|
1037 | #define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
|
---|
1038 | #define USB_HOST_PSTATUSSET_BK1RDY (0x1u << USB_HOST_PSTATUSSET_BK1RDY_Pos)
|
---|
1039 | #define USB_HOST_PSTATUSSET_MASK 0xD5u /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
|
---|
1040 |
|
---|
1041 | /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
|
---|
1042 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1043 | typedef union {
|
---|
1044 | struct {
|
---|
1045 | uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
|
---|
1046 | uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
|
---|
1047 | uint8_t CURBK:1; /*!< bit: 2 Current Bank */
|
---|
1048 | uint8_t :1; /*!< bit: 3 Reserved */
|
---|
1049 | uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
|
---|
1050 | uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
|
---|
1051 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
|
---|
1052 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
|
---|
1053 | } bit; /*!< Structure used for bit access */
|
---|
1054 | struct {
|
---|
1055 | uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
---|
1056 | uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
|
---|
1057 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
1058 | } vec; /*!< Structure used for vec access */
|
---|
1059 | uint8_t reg; /*!< Type used for register access */
|
---|
1060 | } USB_DEVICE_EPSTATUS_Type;
|
---|
1061 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1062 |
|
---|
1063 | #define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
|
---|
1064 | #define USB_DEVICE_EPSTATUS_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
|
---|
1065 |
|
---|
1066 | #define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
|
---|
1067 | #define USB_DEVICE_EPSTATUS_DTGLOUT (0x1u << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
|
---|
1068 | #define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
|
---|
1069 | #define USB_DEVICE_EPSTATUS_DTGLIN (0x1u << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
|
---|
1070 | #define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
|
---|
1071 | #define USB_DEVICE_EPSTATUS_CURBK (0x1u << USB_DEVICE_EPSTATUS_CURBK_Pos)
|
---|
1072 | #define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
|
---|
1073 | #define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
|
---|
1074 | #define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
|
---|
1075 | #define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
|
---|
1076 | #define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
|
---|
1077 | #define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3u << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
|
---|
1078 | #define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)))
|
---|
1079 | #define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
|
---|
1080 | #define USB_DEVICE_EPSTATUS_BK0RDY (0x1u << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
|
---|
1081 | #define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
|
---|
1082 | #define USB_DEVICE_EPSTATUS_BK1RDY (0x1u << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
|
---|
1083 | #define USB_DEVICE_EPSTATUS_MASK 0xF7u /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
|
---|
1084 |
|
---|
1085 | /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
|
---|
1086 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1087 | typedef union {
|
---|
1088 | struct {
|
---|
1089 | uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
|
---|
1090 | uint8_t :1; /*!< bit: 1 Reserved */
|
---|
1091 | uint8_t CURBK:1; /*!< bit: 2 Current Bank */
|
---|
1092 | uint8_t :1; /*!< bit: 3 Reserved */
|
---|
1093 | uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
|
---|
1094 | uint8_t :1; /*!< bit: 5 Reserved */
|
---|
1095 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
|
---|
1096 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
|
---|
1097 | } bit; /*!< Structure used for bit access */
|
---|
1098 | uint8_t reg; /*!< Type used for register access */
|
---|
1099 | } USB_HOST_PSTATUS_Type;
|
---|
1100 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1101 |
|
---|
1102 | #define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
|
---|
1103 | #define USB_HOST_PSTATUS_RESETVALUE 0x00 /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
|
---|
1104 |
|
---|
1105 | #define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
|
---|
1106 | #define USB_HOST_PSTATUS_DTGL (0x1u << USB_HOST_PSTATUS_DTGL_Pos)
|
---|
1107 | #define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
|
---|
1108 | #define USB_HOST_PSTATUS_CURBK (0x1u << USB_HOST_PSTATUS_CURBK_Pos)
|
---|
1109 | #define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
|
---|
1110 | #define USB_HOST_PSTATUS_PFREEZE (0x1u << USB_HOST_PSTATUS_PFREEZE_Pos)
|
---|
1111 | #define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
|
---|
1112 | #define USB_HOST_PSTATUS_BK0RDY (0x1u << USB_HOST_PSTATUS_BK0RDY_Pos)
|
---|
1113 | #define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
|
---|
1114 | #define USB_HOST_PSTATUS_BK1RDY (0x1u << USB_HOST_PSTATUS_BK1RDY_Pos)
|
---|
1115 | #define USB_HOST_PSTATUS_MASK 0xD5u /**< \brief (USB_HOST_PSTATUS) MASK Register */
|
---|
1116 |
|
---|
1117 | /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
|
---|
1118 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1119 | typedef union {
|
---|
1120 | struct {
|
---|
1121 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
|
---|
1122 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
|
---|
1123 | uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
|
---|
1124 | uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
|
---|
1125 | uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
|
---|
1126 | uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
|
---|
1127 | uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
|
---|
1128 | uint8_t :1; /*!< bit: 7 Reserved */
|
---|
1129 | } bit; /*!< Structure used for bit access */
|
---|
1130 | struct {
|
---|
1131 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
|
---|
1132 | uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
|
---|
1133 | uint8_t :1; /*!< bit: 4 Reserved */
|
---|
1134 | uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
|
---|
1135 | uint8_t :1; /*!< bit: 7 Reserved */
|
---|
1136 | } vec; /*!< Structure used for vec access */
|
---|
1137 | uint8_t reg; /*!< Type used for register access */
|
---|
1138 | } USB_DEVICE_EPINTFLAG_Type;
|
---|
1139 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1140 |
|
---|
1141 | #define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
|
---|
1142 | #define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
|
---|
1143 |
|
---|
1144 | #define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
|
---|
1145 | #define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
|
---|
1146 | #define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
|
---|
1147 | #define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
|
---|
1148 | #define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
|
---|
1149 | #define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3u << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
|
---|
1150 | #define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)))
|
---|
1151 | #define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
|
---|
1152 | #define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
|
---|
1153 | #define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
|
---|
1154 | #define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
|
---|
1155 | #define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
|
---|
1156 | #define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3u << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
|
---|
1157 | #define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)))
|
---|
1158 | #define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
|
---|
1159 | #define USB_DEVICE_EPINTFLAG_RXSTP (0x1u << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
|
---|
1160 | #define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
|
---|
1161 | #define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
|
---|
1162 | #define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
|
---|
1163 | #define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
|
---|
1164 | #define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
|
---|
1165 | #define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3u << USB_DEVICE_EPINTFLAG_STALL_Pos)
|
---|
1166 | #define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)))
|
---|
1167 | #define USB_DEVICE_EPINTFLAG_MASK 0x7Fu /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
|
---|
1168 |
|
---|
1169 | /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
|
---|
1170 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1171 | typedef union {
|
---|
1172 | struct {
|
---|
1173 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
|
---|
1174 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
|
---|
1175 | uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
|
---|
1176 | uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
|
---|
1177 | uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
|
---|
1178 | uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
|
---|
1179 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
1180 | } bit; /*!< Structure used for bit access */
|
---|
1181 | struct {
|
---|
1182 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
|
---|
1183 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
1184 | } vec; /*!< Structure used for vec access */
|
---|
1185 | uint8_t reg; /*!< Type used for register access */
|
---|
1186 | } USB_HOST_PINTFLAG_Type;
|
---|
1187 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1188 |
|
---|
1189 | #define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
|
---|
1190 | #define USB_HOST_PINTFLAG_RESETVALUE 0x00 /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
|
---|
1191 |
|
---|
1192 | #define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
|
---|
1193 | #define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
|
---|
1194 | #define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
|
---|
1195 | #define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
|
---|
1196 | #define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
|
---|
1197 | #define USB_HOST_PINTFLAG_TRCPT_Msk (0x3u << USB_HOST_PINTFLAG_TRCPT_Pos)
|
---|
1198 | #define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)))
|
---|
1199 | #define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
|
---|
1200 | #define USB_HOST_PINTFLAG_TRFAIL (0x1u << USB_HOST_PINTFLAG_TRFAIL_Pos)
|
---|
1201 | #define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
|
---|
1202 | #define USB_HOST_PINTFLAG_PERR (0x1u << USB_HOST_PINTFLAG_PERR_Pos)
|
---|
1203 | #define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
|
---|
1204 | #define USB_HOST_PINTFLAG_TXSTP (0x1u << USB_HOST_PINTFLAG_TXSTP_Pos)
|
---|
1205 | #define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
|
---|
1206 | #define USB_HOST_PINTFLAG_STALL (0x1u << USB_HOST_PINTFLAG_STALL_Pos)
|
---|
1207 | #define USB_HOST_PINTFLAG_MASK 0x3Fu /**< \brief (USB_HOST_PINTFLAG) MASK Register */
|
---|
1208 |
|
---|
1209 | /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
|
---|
1210 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1211 | typedef union {
|
---|
1212 | struct {
|
---|
1213 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
|
---|
1214 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
|
---|
1215 | uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
|
---|
1216 | uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
|
---|
1217 | uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
|
---|
1218 | uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
|
---|
1219 | uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
|
---|
1220 | uint8_t :1; /*!< bit: 7 Reserved */
|
---|
1221 | } bit; /*!< Structure used for bit access */
|
---|
1222 | struct {
|
---|
1223 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
|
---|
1224 | uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
|
---|
1225 | uint8_t :1; /*!< bit: 4 Reserved */
|
---|
1226 | uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
|
---|
1227 | uint8_t :1; /*!< bit: 7 Reserved */
|
---|
1228 | } vec; /*!< Structure used for vec access */
|
---|
1229 | uint8_t reg; /*!< Type used for register access */
|
---|
1230 | } USB_DEVICE_EPINTENCLR_Type;
|
---|
1231 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1232 |
|
---|
1233 | #define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
|
---|
1234 | #define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
|
---|
1235 |
|
---|
1236 | #define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
|
---|
1237 | #define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
|
---|
1238 | #define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
|
---|
1239 | #define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
|
---|
1240 | #define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
|
---|
1241 | #define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3u << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
|
---|
1242 | #define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)))
|
---|
1243 | #define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
|
---|
1244 | #define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
|
---|
1245 | #define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
|
---|
1246 | #define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
|
---|
1247 | #define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
|
---|
1248 | #define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3u << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
|
---|
1249 | #define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)))
|
---|
1250 | #define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
|
---|
1251 | #define USB_DEVICE_EPINTENCLR_RXSTP (0x1u << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
|
---|
1252 | #define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
|
---|
1253 | #define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
|
---|
1254 | #define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
|
---|
1255 | #define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
|
---|
1256 | #define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
|
---|
1257 | #define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3u << USB_DEVICE_EPINTENCLR_STALL_Pos)
|
---|
1258 | #define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)))
|
---|
1259 | #define USB_DEVICE_EPINTENCLR_MASK 0x7Fu /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
|
---|
1260 |
|
---|
1261 | /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
|
---|
1262 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1263 | typedef union {
|
---|
1264 | struct {
|
---|
1265 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
|
---|
1266 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
|
---|
1267 | uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
|
---|
1268 | uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
|
---|
1269 | uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
|
---|
1270 | uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
|
---|
1271 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
1272 | } bit; /*!< Structure used for bit access */
|
---|
1273 | struct {
|
---|
1274 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
|
---|
1275 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
1276 | } vec; /*!< Structure used for vec access */
|
---|
1277 | uint8_t reg; /*!< Type used for register access */
|
---|
1278 | } USB_HOST_PINTENCLR_Type;
|
---|
1279 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1280 |
|
---|
1281 | #define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
|
---|
1282 | #define USB_HOST_PINTENCLR_RESETVALUE 0x00 /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
|
---|
1283 |
|
---|
1284 | #define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
|
---|
1285 | #define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
|
---|
1286 | #define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
|
---|
1287 | #define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
|
---|
1288 | #define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
|
---|
1289 | #define USB_HOST_PINTENCLR_TRCPT_Msk (0x3u << USB_HOST_PINTENCLR_TRCPT_Pos)
|
---|
1290 | #define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)))
|
---|
1291 | #define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
|
---|
1292 | #define USB_HOST_PINTENCLR_TRFAIL (0x1u << USB_HOST_PINTENCLR_TRFAIL_Pos)
|
---|
1293 | #define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
|
---|
1294 | #define USB_HOST_PINTENCLR_PERR (0x1u << USB_HOST_PINTENCLR_PERR_Pos)
|
---|
1295 | #define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
|
---|
1296 | #define USB_HOST_PINTENCLR_TXSTP (0x1u << USB_HOST_PINTENCLR_TXSTP_Pos)
|
---|
1297 | #define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
|
---|
1298 | #define USB_HOST_PINTENCLR_STALL (0x1u << USB_HOST_PINTENCLR_STALL_Pos)
|
---|
1299 | #define USB_HOST_PINTENCLR_MASK 0x3Fu /**< \brief (USB_HOST_PINTENCLR) MASK Register */
|
---|
1300 |
|
---|
1301 | /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
|
---|
1302 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1303 | typedef union {
|
---|
1304 | struct {
|
---|
1305 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
|
---|
1306 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
|
---|
1307 | uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
|
---|
1308 | uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
|
---|
1309 | uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
|
---|
1310 | uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
|
---|
1311 | uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
|
---|
1312 | uint8_t :1; /*!< bit: 7 Reserved */
|
---|
1313 | } bit; /*!< Structure used for bit access */
|
---|
1314 | struct {
|
---|
1315 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
|
---|
1316 | uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
|
---|
1317 | uint8_t :1; /*!< bit: 4 Reserved */
|
---|
1318 | uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
|
---|
1319 | uint8_t :1; /*!< bit: 7 Reserved */
|
---|
1320 | } vec; /*!< Structure used for vec access */
|
---|
1321 | uint8_t reg; /*!< Type used for register access */
|
---|
1322 | } USB_DEVICE_EPINTENSET_Type;
|
---|
1323 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1324 |
|
---|
1325 | #define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
|
---|
1326 | #define USB_DEVICE_EPINTENSET_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
|
---|
1327 |
|
---|
1328 | #define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
|
---|
1329 | #define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
|
---|
1330 | #define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
|
---|
1331 | #define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
|
---|
1332 | #define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
|
---|
1333 | #define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3u << USB_DEVICE_EPINTENSET_TRCPT_Pos)
|
---|
1334 | #define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)))
|
---|
1335 | #define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
|
---|
1336 | #define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
|
---|
1337 | #define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
|
---|
1338 | #define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
|
---|
1339 | #define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
|
---|
1340 | #define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3u << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
|
---|
1341 | #define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)))
|
---|
1342 | #define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
|
---|
1343 | #define USB_DEVICE_EPINTENSET_RXSTP (0x1u << USB_DEVICE_EPINTENSET_RXSTP_Pos)
|
---|
1344 | #define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
|
---|
1345 | #define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
|
---|
1346 | #define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
|
---|
1347 | #define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
|
---|
1348 | #define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
|
---|
1349 | #define USB_DEVICE_EPINTENSET_STALL_Msk (0x3u << USB_DEVICE_EPINTENSET_STALL_Pos)
|
---|
1350 | #define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)))
|
---|
1351 | #define USB_DEVICE_EPINTENSET_MASK 0x7Fu /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
|
---|
1352 |
|
---|
1353 | /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
|
---|
1354 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1355 | typedef union {
|
---|
1356 | struct {
|
---|
1357 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
|
---|
1358 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
|
---|
1359 | uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
|
---|
1360 | uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
|
---|
1361 | uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
|
---|
1362 | uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
|
---|
1363 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
1364 | } bit; /*!< Structure used for bit access */
|
---|
1365 | struct {
|
---|
1366 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
|
---|
1367 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
1368 | } vec; /*!< Structure used for vec access */
|
---|
1369 | uint8_t reg; /*!< Type used for register access */
|
---|
1370 | } USB_HOST_PINTENSET_Type;
|
---|
1371 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1372 |
|
---|
1373 | #define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
|
---|
1374 | #define USB_HOST_PINTENSET_RESETVALUE 0x00 /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
|
---|
1375 |
|
---|
1376 | #define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
|
---|
1377 | #define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
|
---|
1378 | #define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
|
---|
1379 | #define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
|
---|
1380 | #define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
|
---|
1381 | #define USB_HOST_PINTENSET_TRCPT_Msk (0x3u << USB_HOST_PINTENSET_TRCPT_Pos)
|
---|
1382 | #define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)))
|
---|
1383 | #define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
|
---|
1384 | #define USB_HOST_PINTENSET_TRFAIL (0x1u << USB_HOST_PINTENSET_TRFAIL_Pos)
|
---|
1385 | #define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
|
---|
1386 | #define USB_HOST_PINTENSET_PERR (0x1u << USB_HOST_PINTENSET_PERR_Pos)
|
---|
1387 | #define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
|
---|
1388 | #define USB_HOST_PINTENSET_TXSTP (0x1u << USB_HOST_PINTENSET_TXSTP_Pos)
|
---|
1389 | #define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
|
---|
1390 | #define USB_HOST_PINTENSET_STALL (0x1u << USB_HOST_PINTENSET_STALL_Pos)
|
---|
1391 | #define USB_HOST_PINTENSET_MASK 0x3Fu /**< \brief (USB_HOST_PINTENSET) MASK Register */
|
---|
1392 |
|
---|
1393 | /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
|
---|
1394 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1395 | typedef union {
|
---|
1396 | struct {
|
---|
1397 | uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
|
---|
1398 | } bit; /*!< Structure used for bit access */
|
---|
1399 | uint32_t reg; /*!< Type used for register access */
|
---|
1400 | } USB_DEVICE_ADDR_Type;
|
---|
1401 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1402 |
|
---|
1403 | #define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
|
---|
1404 |
|
---|
1405 | #define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
|
---|
1406 | #define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFu << USB_DEVICE_ADDR_ADDR_Pos)
|
---|
1407 | #define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)))
|
---|
1408 | #define USB_DEVICE_ADDR_MASK 0xFFFFFFFFu /**< \brief (USB_DEVICE_ADDR) MASK Register */
|
---|
1409 |
|
---|
1410 | /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
|
---|
1411 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1412 | typedef union {
|
---|
1413 | struct {
|
---|
1414 | uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
|
---|
1415 | } bit; /*!< Structure used for bit access */
|
---|
1416 | uint32_t reg; /*!< Type used for register access */
|
---|
1417 | } USB_HOST_ADDR_Type;
|
---|
1418 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1419 |
|
---|
1420 | #define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
|
---|
1421 |
|
---|
1422 | #define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
|
---|
1423 | #define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFu << USB_HOST_ADDR_ADDR_Pos)
|
---|
1424 | #define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)))
|
---|
1425 | #define USB_HOST_ADDR_MASK 0xFFFFFFFFu /**< \brief (USB_HOST_ADDR) MASK Register */
|
---|
1426 |
|
---|
1427 | /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
|
---|
1428 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1429 | typedef union {
|
---|
1430 | struct {
|
---|
1431 | uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
|
---|
1432 | uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
|
---|
1433 | uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
|
---|
1434 | uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
|
---|
1435 | } bit; /*!< Structure used for bit access */
|
---|
1436 | uint32_t reg; /*!< Type used for register access */
|
---|
1437 | } USB_DEVICE_PCKSIZE_Type;
|
---|
1438 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1439 |
|
---|
1440 | #define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
|
---|
1441 |
|
---|
1442 | #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
|
---|
1443 | #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFu << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
|
---|
1444 | #define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)))
|
---|
1445 | #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
|
---|
1446 | #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFu << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
|
---|
1447 | #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
|
---|
1448 | #define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
|
---|
1449 | #define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7u << USB_DEVICE_PCKSIZE_SIZE_Pos)
|
---|
1450 | #define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)))
|
---|
1451 | #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
|
---|
1452 | #define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1u << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
|
---|
1453 | #define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFu /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
|
---|
1454 |
|
---|
1455 | /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
|
---|
1456 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1457 | typedef union {
|
---|
1458 | struct {
|
---|
1459 | uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
|
---|
1460 | uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
|
---|
1461 | uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
|
---|
1462 | uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
|
---|
1463 | } bit; /*!< Structure used for bit access */
|
---|
1464 | uint32_t reg; /*!< Type used for register access */
|
---|
1465 | } USB_HOST_PCKSIZE_Type;
|
---|
1466 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1467 |
|
---|
1468 | #define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
|
---|
1469 |
|
---|
1470 | #define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
|
---|
1471 | #define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFu << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
|
---|
1472 | #define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)))
|
---|
1473 | #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
|
---|
1474 | #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFu << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
|
---|
1475 | #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
|
---|
1476 | #define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
|
---|
1477 | #define USB_HOST_PCKSIZE_SIZE_Msk (0x7u << USB_HOST_PCKSIZE_SIZE_Pos)
|
---|
1478 | #define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)))
|
---|
1479 | #define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
|
---|
1480 | #define USB_HOST_PCKSIZE_AUTO_ZLP (0x1u << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
|
---|
1481 | #define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFu /**< \brief (USB_HOST_PCKSIZE) MASK Register */
|
---|
1482 |
|
---|
1483 | /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
|
---|
1484 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1485 | typedef union {
|
---|
1486 | struct {
|
---|
1487 | uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
|
---|
1488 | uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
|
---|
1489 | uint16_t :1; /*!< bit: 15 Reserved */
|
---|
1490 | } bit; /*!< Structure used for bit access */
|
---|
1491 | uint16_t reg; /*!< Type used for register access */
|
---|
1492 | } USB_DEVICE_EXTREG_Type;
|
---|
1493 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1494 |
|
---|
1495 | #define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
|
---|
1496 |
|
---|
1497 | #define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
|
---|
1498 | #define USB_DEVICE_EXTREG_SUBPID_Msk (0xFu << USB_DEVICE_EXTREG_SUBPID_Pos)
|
---|
1499 | #define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)))
|
---|
1500 | #define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
|
---|
1501 | #define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFu << USB_DEVICE_EXTREG_VARIABLE_Pos)
|
---|
1502 | #define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)))
|
---|
1503 | #define USB_DEVICE_EXTREG_MASK 0x7FFFu /**< \brief (USB_DEVICE_EXTREG) MASK Register */
|
---|
1504 |
|
---|
1505 | /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
|
---|
1506 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1507 | typedef union {
|
---|
1508 | struct {
|
---|
1509 | uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
|
---|
1510 | uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
|
---|
1511 | uint16_t :1; /*!< bit: 15 Reserved */
|
---|
1512 | } bit; /*!< Structure used for bit access */
|
---|
1513 | uint16_t reg; /*!< Type used for register access */
|
---|
1514 | } USB_HOST_EXTREG_Type;
|
---|
1515 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1516 |
|
---|
1517 | #define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
|
---|
1518 |
|
---|
1519 | #define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
|
---|
1520 | #define USB_HOST_EXTREG_SUBPID_Msk (0xFu << USB_HOST_EXTREG_SUBPID_Pos)
|
---|
1521 | #define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)))
|
---|
1522 | #define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
|
---|
1523 | #define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFu << USB_HOST_EXTREG_VARIABLE_Pos)
|
---|
1524 | #define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)))
|
---|
1525 | #define USB_HOST_EXTREG_MASK 0x7FFFu /**< \brief (USB_HOST_EXTREG) MASK Register */
|
---|
1526 |
|
---|
1527 | /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
|
---|
1528 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1529 | typedef union {
|
---|
1530 | struct {
|
---|
1531 | uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
|
---|
1532 | uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
|
---|
1533 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
1534 | } bit; /*!< Structure used for bit access */
|
---|
1535 | uint8_t reg; /*!< Type used for register access */
|
---|
1536 | } USB_DEVICE_STATUS_BK_Type;
|
---|
1537 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1538 |
|
---|
1539 | #define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
|
---|
1540 |
|
---|
1541 | #define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
|
---|
1542 | #define USB_DEVICE_STATUS_BK_CRCERR (0x1u << USB_DEVICE_STATUS_BK_CRCERR_Pos)
|
---|
1543 | #define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
|
---|
1544 | #define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1u << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
|
---|
1545 | #define USB_DEVICE_STATUS_BK_MASK 0x03u /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
|
---|
1546 |
|
---|
1547 | /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
|
---|
1548 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1549 | typedef union {
|
---|
1550 | struct {
|
---|
1551 | uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
|
---|
1552 | uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
|
---|
1553 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
1554 | } bit; /*!< Structure used for bit access */
|
---|
1555 | uint8_t reg; /*!< Type used for register access */
|
---|
1556 | } USB_HOST_STATUS_BK_Type;
|
---|
1557 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1558 |
|
---|
1559 | #define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
|
---|
1560 |
|
---|
1561 | #define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
|
---|
1562 | #define USB_HOST_STATUS_BK_CRCERR (0x1u << USB_HOST_STATUS_BK_CRCERR_Pos)
|
---|
1563 | #define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
|
---|
1564 | #define USB_HOST_STATUS_BK_ERRORFLOW (0x1u << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
|
---|
1565 | #define USB_HOST_STATUS_BK_MASK 0x03u /**< \brief (USB_HOST_STATUS_BK) MASK Register */
|
---|
1566 |
|
---|
1567 | /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
|
---|
1568 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1569 | typedef union {
|
---|
1570 | struct {
|
---|
1571 | uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
|
---|
1572 | uint16_t :1; /*!< bit: 7 Reserved */
|
---|
1573 | uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
|
---|
1574 | uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
|
---|
1575 | } bit; /*!< Structure used for bit access */
|
---|
1576 | uint16_t reg; /*!< Type used for register access */
|
---|
1577 | } USB_HOST_CTRL_PIPE_Type;
|
---|
1578 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1579 |
|
---|
1580 | #define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
|
---|
1581 | #define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000 /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
|
---|
1582 |
|
---|
1583 | #define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
|
---|
1584 | #define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Fu << USB_HOST_CTRL_PIPE_PDADDR_Pos)
|
---|
1585 | #define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)))
|
---|
1586 | #define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
|
---|
1587 | #define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFu << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
|
---|
1588 | #define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)))
|
---|
1589 | #define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
|
---|
1590 | #define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFu << USB_HOST_CTRL_PIPE_PERMAX_Pos)
|
---|
1591 | #define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)))
|
---|
1592 | #define USB_HOST_CTRL_PIPE_MASK 0xFF7Fu /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
|
---|
1593 |
|
---|
1594 | /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
|
---|
1595 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1596 | typedef union {
|
---|
1597 | struct {
|
---|
1598 | uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
|
---|
1599 | uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
|
---|
1600 | uint16_t PIDER:1; /*!< bit: 2 PID Error */
|
---|
1601 | uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
|
---|
1602 | uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
|
---|
1603 | uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
|
---|
1604 | uint16_t :8; /*!< bit: 8..15 Reserved */
|
---|
1605 | } bit; /*!< Structure used for bit access */
|
---|
1606 | uint16_t reg; /*!< Type used for register access */
|
---|
1607 | } USB_HOST_STATUS_PIPE_Type;
|
---|
1608 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1609 |
|
---|
1610 | #define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
|
---|
1611 |
|
---|
1612 | #define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
|
---|
1613 | #define USB_HOST_STATUS_PIPE_DTGLER (0x1u << USB_HOST_STATUS_PIPE_DTGLER_Pos)
|
---|
1614 | #define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
|
---|
1615 | #define USB_HOST_STATUS_PIPE_DAPIDER (0x1u << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
|
---|
1616 | #define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
|
---|
1617 | #define USB_HOST_STATUS_PIPE_PIDER (0x1u << USB_HOST_STATUS_PIPE_PIDER_Pos)
|
---|
1618 | #define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
|
---|
1619 | #define USB_HOST_STATUS_PIPE_TOUTER (0x1u << USB_HOST_STATUS_PIPE_TOUTER_Pos)
|
---|
1620 | #define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
|
---|
1621 | #define USB_HOST_STATUS_PIPE_CRC16ER (0x1u << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
|
---|
1622 | #define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
|
---|
1623 | #define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7u << USB_HOST_STATUS_PIPE_ERCNT_Pos)
|
---|
1624 | #define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)))
|
---|
1625 | #define USB_HOST_STATUS_PIPE_MASK 0x00FFu /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
|
---|
1626 |
|
---|
1627 | /** \brief UsbDeviceDescBank SRAM registers */
|
---|
1628 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1629 | typedef struct {
|
---|
1630 | __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
|
---|
1631 | __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
|
---|
1632 | __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
|
---|
1633 | __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
|
---|
1634 | RoReg8 Reserved1[0x5];
|
---|
1635 | } UsbDeviceDescBank;
|
---|
1636 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1637 |
|
---|
1638 | /** \brief UsbHostDescBank SRAM registers */
|
---|
1639 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1640 | typedef struct {
|
---|
1641 | __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
|
---|
1642 | __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
|
---|
1643 | __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
|
---|
1644 | __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
|
---|
1645 | RoReg8 Reserved1[0x1];
|
---|
1646 | __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
|
---|
1647 | __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
|
---|
1648 | } UsbHostDescBank;
|
---|
1649 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1650 |
|
---|
1651 | /** \brief UsbDeviceEndpoint hardware registers */
|
---|
1652 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1653 | typedef struct {
|
---|
1654 | __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
|
---|
1655 | RoReg8 Reserved1[0x3];
|
---|
1656 | __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
|
---|
1657 | __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
|
---|
1658 | __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
|
---|
1659 | __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
|
---|
1660 | __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
|
---|
1661 | __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
|
---|
1662 | RoReg8 Reserved2[0x16];
|
---|
1663 | } UsbDeviceEndpoint;
|
---|
1664 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1665 |
|
---|
1666 | /** \brief UsbHostPipe hardware registers */
|
---|
1667 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1668 | typedef struct {
|
---|
1669 | __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
|
---|
1670 | RoReg8 Reserved1[0x2];
|
---|
1671 | __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
|
---|
1672 | __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
|
---|
1673 | __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
|
---|
1674 | __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
|
---|
1675 | __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
|
---|
1676 | __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
|
---|
1677 | __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
|
---|
1678 | RoReg8 Reserved2[0x16];
|
---|
1679 | } UsbHostPipe;
|
---|
1680 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1681 |
|
---|
1682 | /** \brief USB_DEVICE APB hardware registers */
|
---|
1683 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1684 | typedef struct { /* USB is Device */
|
---|
1685 | __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
|
---|
1686 | RoReg8 Reserved1[0x1];
|
---|
1687 | __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
|
---|
1688 | RoReg8 Reserved2[0x5];
|
---|
1689 | __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
|
---|
1690 | __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
|
---|
1691 | RoReg8 Reserved3[0x1];
|
---|
1692 | __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
|
---|
1693 | __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
|
---|
1694 | RoReg8 Reserved4[0x2];
|
---|
1695 | __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
|
---|
1696 | RoReg8 Reserved5[0x2];
|
---|
1697 | __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
|
---|
1698 | RoReg8 Reserved6[0x2];
|
---|
1699 | __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
|
---|
1700 | RoReg8 Reserved7[0x2];
|
---|
1701 | __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
|
---|
1702 | RoReg8 Reserved8[0x2];
|
---|
1703 | __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
|
---|
1704 | RoReg8 Reserved9[0x2];
|
---|
1705 | __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
|
---|
1706 | __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
|
---|
1707 | RoReg8 Reserved10[0xD6];
|
---|
1708 | UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
|
---|
1709 | } UsbDevice;
|
---|
1710 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1711 |
|
---|
1712 | /** \brief USB_HOST hardware registers */
|
---|
1713 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1714 | typedef struct { /* USB is Host */
|
---|
1715 | __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
|
---|
1716 | RoReg8 Reserved1[0x1];
|
---|
1717 | __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
|
---|
1718 | RoReg8 Reserved2[0x5];
|
---|
1719 | __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
|
---|
1720 | __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
|
---|
1721 | RoReg8 Reserved3[0x1];
|
---|
1722 | __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
|
---|
1723 | __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
|
---|
1724 | RoReg8 Reserved4[0x2];
|
---|
1725 | __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
|
---|
1726 | __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
|
---|
1727 | RoReg8 Reserved5[0x1];
|
---|
1728 | __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
|
---|
1729 | RoReg8 Reserved6[0x2];
|
---|
1730 | __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
|
---|
1731 | RoReg8 Reserved7[0x2];
|
---|
1732 | __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
|
---|
1733 | RoReg8 Reserved8[0x2];
|
---|
1734 | __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
|
---|
1735 | RoReg8 Reserved9[0x2];
|
---|
1736 | __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
|
---|
1737 | __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
|
---|
1738 | RoReg8 Reserved10[0xD6];
|
---|
1739 | UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM] */
|
---|
1740 | } UsbHost;
|
---|
1741 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1742 |
|
---|
1743 | /** \brief USB_DEVICE Descriptor SRAM registers */
|
---|
1744 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1745 | typedef struct { /* USB is Device */
|
---|
1746 | UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
|
---|
1747 | } UsbDeviceDescriptor;
|
---|
1748 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1749 |
|
---|
1750 | /** \brief USB_HOST Descriptor SRAM registers */
|
---|
1751 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1752 | typedef struct { /* USB is Host */
|
---|
1753 | UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups */
|
---|
1754 | } UsbHostDescriptor;
|
---|
1755 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1756 | #define SECTION_USB_DESCRIPTOR
|
---|
1757 |
|
---|
1758 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1759 | typedef union {
|
---|
1760 | UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
|
---|
1761 | UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
|
---|
1762 | } Usb;
|
---|
1763 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1764 |
|
---|
1765 | /*@}*/
|
---|
1766 |
|
---|
1767 | #endif /* _SAMD21_USB_COMPONENT_ */
|
---|