source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/sysctrl.h@ 136

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1/**
2 * \file
3 *
4 * \brief Component description for SYSCTRL
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_SYSCTRL_COMPONENT_
45#define _SAMD21_SYSCTRL_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR SYSCTRL */
49/* ========================================================================== */
50/** \addtogroup SAMD21_SYSCTRL System Control */
51/*@{*/
52
53#define SYSCTRL_U2100
54#define REV_SYSCTRL 0x201
55
56/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
61 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
62 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
63 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
64 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
65 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
66 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
67 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
68 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
69 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
70 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
71 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
72 uint32_t :3; /*!< bit: 12..14 Reserved */
73 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
74 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
75 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
76 uint32_t :14; /*!< bit: 18..31 Reserved */
77 } bit; /*!< Structure used for bit access */
78 uint32_t reg; /*!< Type used for register access */
79} SYSCTRL_INTENCLR_Type;
80#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
81
82#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
83#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
84
85#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
86#define SYSCTRL_INTENCLR_XOSCRDY (0x1u << SYSCTRL_INTENCLR_XOSCRDY_Pos)
87#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
88#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1u << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
89#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
90#define SYSCTRL_INTENCLR_OSC32KRDY (0x1u << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
91#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
92#define SYSCTRL_INTENCLR_OSC8MRDY (0x1u << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
93#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
94#define SYSCTRL_INTENCLR_DFLLRDY (0x1u << SYSCTRL_INTENCLR_DFLLRDY_Pos)
95#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
96#define SYSCTRL_INTENCLR_DFLLOOB (0x1u << SYSCTRL_INTENCLR_DFLLOOB_Pos)
97#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
98#define SYSCTRL_INTENCLR_DFLLLCKF (0x1u << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
99#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
100#define SYSCTRL_INTENCLR_DFLLLCKC (0x1u << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
101#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
102#define SYSCTRL_INTENCLR_DFLLRCS (0x1u << SYSCTRL_INTENCLR_DFLLRCS_Pos)
103#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
104#define SYSCTRL_INTENCLR_BOD33RDY (0x1u << SYSCTRL_INTENCLR_BOD33RDY_Pos)
105#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
106#define SYSCTRL_INTENCLR_BOD33DET (0x1u << SYSCTRL_INTENCLR_BOD33DET_Pos)
107#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
108#define SYSCTRL_INTENCLR_B33SRDY (0x1u << SYSCTRL_INTENCLR_B33SRDY_Pos)
109#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
110#define SYSCTRL_INTENCLR_DPLLLCKR (0x1u << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
111#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
112#define SYSCTRL_INTENCLR_DPLLLCKF (0x1u << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
113#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
114#define SYSCTRL_INTENCLR_DPLLLTO (0x1u << SYSCTRL_INTENCLR_DPLLLTO_Pos)
115#define SYSCTRL_INTENCLR_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTENCLR) MASK Register */
116
117/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
118#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
119typedef union {
120 struct {
121 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
122 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
123 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
124 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
125 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
126 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
127 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
128 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
129 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
130 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
131 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
132 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
133 uint32_t :3; /*!< bit: 12..14 Reserved */
134 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
135 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
136 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
137 uint32_t :14; /*!< bit: 18..31 Reserved */
138 } bit; /*!< Structure used for bit access */
139 uint32_t reg; /*!< Type used for register access */
140} SYSCTRL_INTENSET_Type;
141#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
142
143#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
144#define SYSCTRL_INTENSET_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
145
146#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
147#define SYSCTRL_INTENSET_XOSCRDY (0x1u << SYSCTRL_INTENSET_XOSCRDY_Pos)
148#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
149#define SYSCTRL_INTENSET_XOSC32KRDY (0x1u << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
150#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
151#define SYSCTRL_INTENSET_OSC32KRDY (0x1u << SYSCTRL_INTENSET_OSC32KRDY_Pos)
152#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
153#define SYSCTRL_INTENSET_OSC8MRDY (0x1u << SYSCTRL_INTENSET_OSC8MRDY_Pos)
154#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
155#define SYSCTRL_INTENSET_DFLLRDY (0x1u << SYSCTRL_INTENSET_DFLLRDY_Pos)
156#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
157#define SYSCTRL_INTENSET_DFLLOOB (0x1u << SYSCTRL_INTENSET_DFLLOOB_Pos)
158#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
159#define SYSCTRL_INTENSET_DFLLLCKF (0x1u << SYSCTRL_INTENSET_DFLLLCKF_Pos)
160#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
161#define SYSCTRL_INTENSET_DFLLLCKC (0x1u << SYSCTRL_INTENSET_DFLLLCKC_Pos)
162#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
163#define SYSCTRL_INTENSET_DFLLRCS (0x1u << SYSCTRL_INTENSET_DFLLRCS_Pos)
164#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
165#define SYSCTRL_INTENSET_BOD33RDY (0x1u << SYSCTRL_INTENSET_BOD33RDY_Pos)
166#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
167#define SYSCTRL_INTENSET_BOD33DET (0x1u << SYSCTRL_INTENSET_BOD33DET_Pos)
168#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
169#define SYSCTRL_INTENSET_B33SRDY (0x1u << SYSCTRL_INTENSET_B33SRDY_Pos)
170#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
171#define SYSCTRL_INTENSET_DPLLLCKR (0x1u << SYSCTRL_INTENSET_DPLLLCKR_Pos)
172#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
173#define SYSCTRL_INTENSET_DPLLLCKF (0x1u << SYSCTRL_INTENSET_DPLLLCKF_Pos)
174#define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
175#define SYSCTRL_INTENSET_DPLLLTO (0x1u << SYSCTRL_INTENSET_DPLLLTO_Pos)
176#define SYSCTRL_INTENSET_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTENSET) MASK Register */
177
178/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
179#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
180typedef union {
181 struct {
182 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
183 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
184 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
185 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
186 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
187 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
188 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
189 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
190 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
191 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
192 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
193 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
194 uint32_t :3; /*!< bit: 12..14 Reserved */
195 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
196 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
197 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
198 uint32_t :14; /*!< bit: 18..31 Reserved */
199 } bit; /*!< Structure used for bit access */
200 uint32_t reg; /*!< Type used for register access */
201} SYSCTRL_INTFLAG_Type;
202#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
203
204#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
205#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
206
207#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
208#define SYSCTRL_INTFLAG_XOSCRDY (0x1u << SYSCTRL_INTFLAG_XOSCRDY_Pos)
209#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
210#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1u << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
211#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
212#define SYSCTRL_INTFLAG_OSC32KRDY (0x1u << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
213#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
214#define SYSCTRL_INTFLAG_OSC8MRDY (0x1u << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
215#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
216#define SYSCTRL_INTFLAG_DFLLRDY (0x1u << SYSCTRL_INTFLAG_DFLLRDY_Pos)
217#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
218#define SYSCTRL_INTFLAG_DFLLOOB (0x1u << SYSCTRL_INTFLAG_DFLLOOB_Pos)
219#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
220#define SYSCTRL_INTFLAG_DFLLLCKF (0x1u << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
221#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
222#define SYSCTRL_INTFLAG_DFLLLCKC (0x1u << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
223#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
224#define SYSCTRL_INTFLAG_DFLLRCS (0x1u << SYSCTRL_INTFLAG_DFLLRCS_Pos)
225#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
226#define SYSCTRL_INTFLAG_BOD33RDY (0x1u << SYSCTRL_INTFLAG_BOD33RDY_Pos)
227#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
228#define SYSCTRL_INTFLAG_BOD33DET (0x1u << SYSCTRL_INTFLAG_BOD33DET_Pos)
229#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
230#define SYSCTRL_INTFLAG_B33SRDY (0x1u << SYSCTRL_INTFLAG_B33SRDY_Pos)
231#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
232#define SYSCTRL_INTFLAG_DPLLLCKR (0x1u << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
233#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
234#define SYSCTRL_INTFLAG_DPLLLCKF (0x1u << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
235#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
236#define SYSCTRL_INTFLAG_DPLLLTO (0x1u << SYSCTRL_INTFLAG_DPLLLTO_Pos)
237#define SYSCTRL_INTFLAG_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTFLAG) MASK Register */
238
239/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
240#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
241typedef union {
242 struct {
243 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
244 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
245 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
246 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
247 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
248 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
249 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
250 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
251 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
252 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
253 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
254 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
255 uint32_t :3; /*!< bit: 12..14 Reserved */
256 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
257 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
258 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
259 uint32_t :14; /*!< bit: 18..31 Reserved */
260 } bit; /*!< Structure used for bit access */
261 uint32_t reg; /*!< Type used for register access */
262} SYSCTRL_PCLKSR_Type;
263#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
264
265#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
266#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
267
268#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
269#define SYSCTRL_PCLKSR_XOSCRDY (0x1u << SYSCTRL_PCLKSR_XOSCRDY_Pos)
270#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
271#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1u << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
272#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
273#define SYSCTRL_PCLKSR_OSC32KRDY (0x1u << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
274#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
275#define SYSCTRL_PCLKSR_OSC8MRDY (0x1u << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
276#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
277#define SYSCTRL_PCLKSR_DFLLRDY (0x1u << SYSCTRL_PCLKSR_DFLLRDY_Pos)
278#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
279#define SYSCTRL_PCLKSR_DFLLOOB (0x1u << SYSCTRL_PCLKSR_DFLLOOB_Pos)
280#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
281#define SYSCTRL_PCLKSR_DFLLLCKF (0x1u << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
282#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
283#define SYSCTRL_PCLKSR_DFLLLCKC (0x1u << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
284#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
285#define SYSCTRL_PCLKSR_DFLLRCS (0x1u << SYSCTRL_PCLKSR_DFLLRCS_Pos)
286#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
287#define SYSCTRL_PCLKSR_BOD33RDY (0x1u << SYSCTRL_PCLKSR_BOD33RDY_Pos)
288#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
289#define SYSCTRL_PCLKSR_BOD33DET (0x1u << SYSCTRL_PCLKSR_BOD33DET_Pos)
290#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
291#define SYSCTRL_PCLKSR_B33SRDY (0x1u << SYSCTRL_PCLKSR_B33SRDY_Pos)
292#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
293#define SYSCTRL_PCLKSR_DPLLLCKR (0x1u << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
294#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
295#define SYSCTRL_PCLKSR_DPLLLCKF (0x1u << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
296#define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
297#define SYSCTRL_PCLKSR_DPLLLTO (0x1u << SYSCTRL_PCLKSR_DPLLLTO_Pos)
298#define SYSCTRL_PCLKSR_MASK 0x00038FFFu /**< \brief (SYSCTRL_PCLKSR) MASK Register */
299
300/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
301#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
302typedef union {
303 struct {
304 uint16_t :1; /*!< bit: 0 Reserved */
305 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
306 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
307 uint16_t :3; /*!< bit: 3.. 5 Reserved */
308 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
309 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
310 uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
311 uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
312 uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
313 } bit; /*!< Structure used for bit access */
314 uint16_t reg; /*!< Type used for register access */
315} SYSCTRL_XOSC_Type;
316#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
317
318#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
319#define SYSCTRL_XOSC_RESETVALUE 0x0080 /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
320
321#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
322#define SYSCTRL_XOSC_ENABLE (0x1u << SYSCTRL_XOSC_ENABLE_Pos)
323#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
324#define SYSCTRL_XOSC_XTALEN (0x1u << SYSCTRL_XOSC_XTALEN_Pos)
325#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */
326#define SYSCTRL_XOSC_RUNSTDBY (0x1u << SYSCTRL_XOSC_RUNSTDBY_Pos)
327#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */
328#define SYSCTRL_XOSC_ONDEMAND (0x1u << SYSCTRL_XOSC_ONDEMAND_Pos)
329#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
330#define SYSCTRL_XOSC_GAIN_Msk (0x7u << SYSCTRL_XOSC_GAIN_Pos)
331#define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
332#define SYSCTRL_XOSC_GAIN_0_Val 0x0u /**< \brief (SYSCTRL_XOSC) 2MHz */
333#define SYSCTRL_XOSC_GAIN_1_Val 0x1u /**< \brief (SYSCTRL_XOSC) 4MHz */
334#define SYSCTRL_XOSC_GAIN_2_Val 0x2u /**< \brief (SYSCTRL_XOSC) 8MHz */
335#define SYSCTRL_XOSC_GAIN_3_Val 0x3u /**< \brief (SYSCTRL_XOSC) 16MHz */
336#define SYSCTRL_XOSC_GAIN_4_Val 0x4u /**< \brief (SYSCTRL_XOSC) 30MHz */
337#define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos)
338#define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos)
339#define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos)
340#define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos)
341#define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos)
342#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
343#define SYSCTRL_XOSC_AMPGC (0x1u << SYSCTRL_XOSC_AMPGC_Pos)
344#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
345#define SYSCTRL_XOSC_STARTUP_Msk (0xFu << SYSCTRL_XOSC_STARTUP_Pos)
346#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
347#define SYSCTRL_XOSC_MASK 0xFFC6u /**< \brief (SYSCTRL_XOSC) MASK Register */
348
349/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
350#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
351typedef union {
352 struct {
353 uint16_t :1; /*!< bit: 0 Reserved */
354 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
355 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
356 uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
357 uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
358 uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
359 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
360 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
361 uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
362 uint16_t :1; /*!< bit: 11 Reserved */
363 uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
364 uint16_t :3; /*!< bit: 13..15 Reserved */
365 } bit; /*!< Structure used for bit access */
366 uint16_t reg; /*!< Type used for register access */
367} SYSCTRL_XOSC32K_Type;
368#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
369
370#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
371#define SYSCTRL_XOSC32K_RESETVALUE 0x0080 /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
372
373#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
374#define SYSCTRL_XOSC32K_ENABLE (0x1u << SYSCTRL_XOSC32K_ENABLE_Pos)
375#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
376#define SYSCTRL_XOSC32K_XTALEN (0x1u << SYSCTRL_XOSC32K_XTALEN_Pos)
377#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
378#define SYSCTRL_XOSC32K_EN32K (0x1u << SYSCTRL_XOSC32K_EN32K_Pos)
379#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
380#define SYSCTRL_XOSC32K_EN1K (0x1u << SYSCTRL_XOSC32K_EN1K_Pos)
381#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
382#define SYSCTRL_XOSC32K_AAMPEN (0x1u << SYSCTRL_XOSC32K_AAMPEN_Pos)
383#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
384#define SYSCTRL_XOSC32K_RUNSTDBY (0x1u << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
385#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
386#define SYSCTRL_XOSC32K_ONDEMAND (0x1u << SYSCTRL_XOSC32K_ONDEMAND_Pos)
387#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
388#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7u << SYSCTRL_XOSC32K_STARTUP_Pos)
389#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
390#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
391#define SYSCTRL_XOSC32K_WRTLOCK (0x1u << SYSCTRL_XOSC32K_WRTLOCK_Pos)
392#define SYSCTRL_XOSC32K_MASK 0x17FEu /**< \brief (SYSCTRL_XOSC32K) MASK Register */
393
394/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
395#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
396typedef union {
397 struct {
398 uint32_t :1; /*!< bit: 0 Reserved */
399 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
400 uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
401 uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
402 uint32_t :2; /*!< bit: 4.. 5 Reserved */
403 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
404 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
405 uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
406 uint32_t :1; /*!< bit: 11 Reserved */
407 uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
408 uint32_t :3; /*!< bit: 13..15 Reserved */
409 uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
410 uint32_t :9; /*!< bit: 23..31 Reserved */
411 } bit; /*!< Structure used for bit access */
412 uint32_t reg; /*!< Type used for register access */
413} SYSCTRL_OSC32K_Type;
414#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
415
416#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
417#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080 /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
418
419#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
420#define SYSCTRL_OSC32K_ENABLE (0x1u << SYSCTRL_OSC32K_ENABLE_Pos)
421#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
422#define SYSCTRL_OSC32K_EN32K (0x1u << SYSCTRL_OSC32K_EN32K_Pos)
423#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
424#define SYSCTRL_OSC32K_EN1K (0x1u << SYSCTRL_OSC32K_EN1K_Pos)
425#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */
426#define SYSCTRL_OSC32K_RUNSTDBY (0x1u << SYSCTRL_OSC32K_RUNSTDBY_Pos)
427#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */
428#define SYSCTRL_OSC32K_ONDEMAND (0x1u << SYSCTRL_OSC32K_ONDEMAND_Pos)
429#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
430#define SYSCTRL_OSC32K_STARTUP_Msk (0x7u << SYSCTRL_OSC32K_STARTUP_Pos)
431#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
432#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
433#define SYSCTRL_OSC32K_WRTLOCK (0x1u << SYSCTRL_OSC32K_WRTLOCK_Pos)
434#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
435#define SYSCTRL_OSC32K_CALIB_Msk (0x7Fu << SYSCTRL_OSC32K_CALIB_Pos)
436#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
437#define SYSCTRL_OSC32K_MASK 0x007F17CEu /**< \brief (SYSCTRL_OSC32K) MASK Register */
438
439/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
440#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
441typedef union {
442 struct {
443 uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
444 uint8_t :2; /*!< bit: 5.. 6 Reserved */
445 uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
446 } bit; /*!< Structure used for bit access */
447 uint8_t reg; /*!< Type used for register access */
448} SYSCTRL_OSCULP32K_Type;
449#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
450
451#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
452#define SYSCTRL_OSCULP32K_RESETVALUE 0x1F /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
453
454#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
455#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Fu << SYSCTRL_OSCULP32K_CALIB_Pos)
456#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
457#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
458#define SYSCTRL_OSCULP32K_WRTLOCK (0x1u << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
459#define SYSCTRL_OSCULP32K_MASK 0x9Fu /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
460
461/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
462#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
463typedef union {
464 struct {
465 uint32_t :1; /*!< bit: 0 Reserved */
466 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
467 uint32_t :4; /*!< bit: 2.. 5 Reserved */
468 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
469 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
470 uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
471 uint32_t :6; /*!< bit: 10..15 Reserved */
472 uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
473 uint32_t :2; /*!< bit: 28..29 Reserved */
474 uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
475 } bit; /*!< Structure used for bit access */
476 uint32_t reg; /*!< Type used for register access */
477} SYSCTRL_OSC8M_Type;
478#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
479
480#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
481#define SYSCTRL_OSC8M_RESETVALUE 0x87070382 /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
482
483#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
484#define SYSCTRL_OSC8M_ENABLE (0x1u << SYSCTRL_OSC8M_ENABLE_Pos)
485#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */
486#define SYSCTRL_OSC8M_RUNSTDBY (0x1u << SYSCTRL_OSC8M_RUNSTDBY_Pos)
487#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */
488#define SYSCTRL_OSC8M_ONDEMAND (0x1u << SYSCTRL_OSC8M_ONDEMAND_Pos)
489#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
490#define SYSCTRL_OSC8M_PRESC_Msk (0x3u << SYSCTRL_OSC8M_PRESC_Pos)
491#define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
492#define SYSCTRL_OSC8M_PRESC_0_Val 0x0u /**< \brief (SYSCTRL_OSC8M) 1 */
493#define SYSCTRL_OSC8M_PRESC_1_Val 0x1u /**< \brief (SYSCTRL_OSC8M) 2 */
494#define SYSCTRL_OSC8M_PRESC_2_Val 0x2u /**< \brief (SYSCTRL_OSC8M) 4 */
495#define SYSCTRL_OSC8M_PRESC_3_Val 0x3u /**< \brief (SYSCTRL_OSC8M) 8 */
496#define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos)
497#define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos)
498#define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos)
499#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
500#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
501#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFu << SYSCTRL_OSC8M_CALIB_Pos)
502#define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
503#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
504#define SYSCTRL_OSC8M_FRANGE_Msk (0x3u << SYSCTRL_OSC8M_FRANGE_Pos)
505#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
506#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0u /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
507#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1u /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
508#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2u /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
509#define SYSCTRL_OSC8M_FRANGE_3_Val 0x3u /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
510#define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos)
511#define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos)
512#define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos)
513#define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos)
514#define SYSCTRL_OSC8M_MASK 0xCFFF03C2u /**< \brief (SYSCTRL_OSC8M) MASK Register */
515
516/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
517#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
518typedef union {
519 struct {
520 uint16_t :1; /*!< bit: 0 Reserved */
521 uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
522 uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
523 uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
524 uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
525 uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
526 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
527 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
528 uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
529 uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
530 uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
531 uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
532 uint16_t :4; /*!< bit: 12..15 Reserved */
533 } bit; /*!< Structure used for bit access */
534 uint16_t reg; /*!< Type used for register access */
535} SYSCTRL_DFLLCTRL_Type;
536#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
537
538#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
539#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080 /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
540
541#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
542#define SYSCTRL_DFLLCTRL_ENABLE (0x1u << SYSCTRL_DFLLCTRL_ENABLE_Pos)
543#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
544#define SYSCTRL_DFLLCTRL_MODE (0x1u << SYSCTRL_DFLLCTRL_MODE_Pos)
545#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
546#define SYSCTRL_DFLLCTRL_STABLE (0x1u << SYSCTRL_DFLLCTRL_STABLE_Pos)
547#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
548#define SYSCTRL_DFLLCTRL_LLAW (0x1u << SYSCTRL_DFLLCTRL_LLAW_Pos)
549#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
550#define SYSCTRL_DFLLCTRL_USBCRM (0x1u << SYSCTRL_DFLLCTRL_USBCRM_Pos)
551#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
552#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1u << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
553#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
554#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1u << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
555#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
556#define SYSCTRL_DFLLCTRL_CCDIS (0x1u << SYSCTRL_DFLLCTRL_CCDIS_Pos)
557#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
558#define SYSCTRL_DFLLCTRL_QLDIS (0x1u << SYSCTRL_DFLLCTRL_QLDIS_Pos)
559#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
560#define SYSCTRL_DFLLCTRL_BPLCKC (0x1u << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
561#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
562#define SYSCTRL_DFLLCTRL_WAITLOCK (0x1u << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
563#define SYSCTRL_DFLLCTRL_MASK 0x0FFEu /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
564
565/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
566#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
567typedef union {
568 struct {
569 uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
570 uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
571 uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
572 } bit; /*!< Structure used for bit access */
573 uint32_t reg; /*!< Type used for register access */
574} SYSCTRL_DFLLVAL_Type;
575#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
576
577#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
578#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
579
580#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
581#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFu << SYSCTRL_DFLLVAL_FINE_Pos)
582#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
583#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
584#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Fu << SYSCTRL_DFLLVAL_COARSE_Pos)
585#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
586#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
587#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFu << SYSCTRL_DFLLVAL_DIFF_Pos)
588#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
589#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFu /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
590
591/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
592#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
593typedef union {
594 struct {
595 uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
596 uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
597 uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
598 } bit; /*!< Structure used for bit access */
599 uint32_t reg; /*!< Type used for register access */
600} SYSCTRL_DFLLMUL_Type;
601#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
602
603#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
604#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
605
606#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
607#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFu << SYSCTRL_DFLLMUL_MUL_Pos)
608#define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
609#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
610#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFu << SYSCTRL_DFLLMUL_FSTEP_Pos)
611#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
612#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
613#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Fu << SYSCTRL_DFLLMUL_CSTEP_Pos)
614#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
615#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFu /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
616
617/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
618#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
619typedef union {
620 struct {
621 uint8_t :7; /*!< bit: 0.. 6 Reserved */
622 uint8_t READREQ:1; /*!< bit: 7 Read Request */
623 } bit; /*!< Structure used for bit access */
624 uint8_t reg; /*!< Type used for register access */
625} SYSCTRL_DFLLSYNC_Type;
626#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
627
628#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
629#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00 /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
630
631#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
632#define SYSCTRL_DFLLSYNC_READREQ (0x1u << SYSCTRL_DFLLSYNC_READREQ_Pos)
633#define SYSCTRL_DFLLSYNC_MASK 0x80u /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
634
635/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
636#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
637typedef union {
638 struct {
639 uint32_t :1; /*!< bit: 0 Reserved */
640 uint32_t ENABLE:1; /*!< bit: 1 Enable */
641 uint32_t HYST:1; /*!< bit: 2 Hysteresis */
642 uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
643 uint32_t :1; /*!< bit: 5 Reserved */
644 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
645 uint32_t :1; /*!< bit: 7 Reserved */
646 uint32_t MODE:1; /*!< bit: 8 Operation Mode */
647 uint32_t CEN:1; /*!< bit: 9 Clock Enable */
648 uint32_t :2; /*!< bit: 10..11 Reserved */
649 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
650 uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
651 uint32_t :10; /*!< bit: 22..31 Reserved */
652 } bit; /*!< Structure used for bit access */
653 uint32_t reg; /*!< Type used for register access */
654} SYSCTRL_BOD33_Type;
655#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
656
657#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
658#define SYSCTRL_BOD33_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
659
660#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */
661#define SYSCTRL_BOD33_ENABLE (0x1u << SYSCTRL_BOD33_ENABLE_Pos)
662#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */
663#define SYSCTRL_BOD33_HYST (0x1u << SYSCTRL_BOD33_HYST_Pos)
664#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
665#define SYSCTRL_BOD33_ACTION_Msk (0x3u << SYSCTRL_BOD33_ACTION_Pos)
666#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
667#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0u /**< \brief (SYSCTRL_BOD33) No action */
668#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1u /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
669#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2u /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
670#define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
671#define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
672#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
673#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */
674#define SYSCTRL_BOD33_RUNSTDBY (0x1u << SYSCTRL_BOD33_RUNSTDBY_Pos)
675#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */
676#define SYSCTRL_BOD33_MODE (0x1u << SYSCTRL_BOD33_MODE_Pos)
677#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */
678#define SYSCTRL_BOD33_CEN (0x1u << SYSCTRL_BOD33_CEN_Pos)
679#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
680#define SYSCTRL_BOD33_PSEL_Msk (0xFu << SYSCTRL_BOD33_PSEL_Pos)
681#define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
682#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0u /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
683#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1u /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
684#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2u /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
685#define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3u /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
686#define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4u /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
687#define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5u /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
688#define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6u /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
689#define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7u /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
690#define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8u /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
691#define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9u /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
692#define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAu /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
693#define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBu /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
694#define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCu /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
695#define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDu /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
696#define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEu /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
697#define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFu /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
698#define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos)
699#define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos)
700#define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos)
701#define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos)
702#define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos)
703#define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos)
704#define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
705#define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
706#define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
707#define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos)
708#define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos)
709#define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos)
710#define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos)
711#define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
712#define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
713#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
714#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
715#define SYSCTRL_BOD33_LEVEL_Msk (0x3Fu << SYSCTRL_BOD33_LEVEL_Pos)
716#define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
717#define SYSCTRL_BOD33_MASK 0x003FF35Eu /**< \brief (SYSCTRL_BOD33) MASK Register */
718
719/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
720#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
721typedef union {
722 struct {
723 uint16_t :6; /*!< bit: 0.. 5 Reserved */
724 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
725 uint16_t :9; /*!< bit: 7..15 Reserved */
726 } bit; /*!< Structure used for bit access */
727 uint16_t reg; /*!< Type used for register access */
728} SYSCTRL_VREG_Type;
729#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
730
731#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
732#define SYSCTRL_VREG_RESETVALUE 0x0000 /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
733
734#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */
735#define SYSCTRL_VREG_RUNSTDBY (0x1u << SYSCTRL_VREG_RUNSTDBY_Pos)
736#define SYSCTRL_VREG_MASK 0x0040u /**< \brief (SYSCTRL_VREG) MASK Register */
737
738/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
739#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
740typedef union {
741 struct {
742 uint32_t :1; /*!< bit: 0 Reserved */
743 uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
744 uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
745 uint32_t :13; /*!< bit: 3..15 Reserved */
746 uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
747 uint32_t :5; /*!< bit: 27..31 Reserved */
748 } bit; /*!< Structure used for bit access */
749 uint32_t reg; /*!< Type used for register access */
750} SYSCTRL_VREF_Type;
751#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
752
753#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
754#define SYSCTRL_VREF_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
755
756#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
757#define SYSCTRL_VREF_TSEN (0x1u << SYSCTRL_VREF_TSEN_Pos)
758#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
759#define SYSCTRL_VREF_BGOUTEN (0x1u << SYSCTRL_VREF_BGOUTEN_Pos)
760#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
761#define SYSCTRL_VREF_CALIB_Msk (0x7FFu << SYSCTRL_VREF_CALIB_Pos)
762#define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
763#define SYSCTRL_VREF_MASK 0x07FF0006u /**< \brief (SYSCTRL_VREF) MASK Register */
764
765/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
766#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
767typedef union {
768 struct {
769 uint8_t :1; /*!< bit: 0 Reserved */
770 uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
771 uint8_t :4; /*!< bit: 2.. 5 Reserved */
772 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
773 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
774 } bit; /*!< Structure used for bit access */
775 uint8_t reg; /*!< Type used for register access */
776} SYSCTRL_DPLLCTRLA_Type;
777#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
778
779#define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
780#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80 /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
781
782#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
783#define SYSCTRL_DPLLCTRLA_ENABLE (0x1u << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
784#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
785#define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1u << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
786#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
787#define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1u << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
788#define SYSCTRL_DPLLCTRLA_MASK 0xC2u /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
789
790/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
791#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
792typedef union {
793 struct {
794 uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
795 uint32_t :4; /*!< bit: 12..15 Reserved */
796 uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
797 uint32_t :12; /*!< bit: 20..31 Reserved */
798 } bit; /*!< Structure used for bit access */
799 uint32_t reg; /*!< Type used for register access */
800} SYSCTRL_DPLLRATIO_Type;
801#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
802
803#define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
804#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
805
806#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
807#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFu << SYSCTRL_DPLLRATIO_LDR_Pos)
808#define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)))
809#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
810#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFu << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
811#define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)))
812#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFu /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
813
814/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
815#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
816typedef union {
817 struct {
818 uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
819 uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
820 uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
821 uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
822 uint32_t :2; /*!< bit: 6.. 7 Reserved */
823 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
824 uint32_t :1; /*!< bit: 11 Reserved */
825 uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
826 uint32_t :3; /*!< bit: 13..15 Reserved */
827 uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
828 uint32_t :5; /*!< bit: 27..31 Reserved */
829 } bit; /*!< Structure used for bit access */
830 uint32_t reg; /*!< Type used for register access */
831} SYSCTRL_DPLLCTRLB_Type;
832#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
833
834#define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
835#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
836
837#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
838#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3u << SYSCTRL_DPLLCTRLB_FILTER_Pos)
839#define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)))
840#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
841#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1u /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
842#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2u /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
843#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3u /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
844#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
845#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
846#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
847#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
848#define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
849#define SYSCTRL_DPLLCTRLB_LPEN (0x1u << SYSCTRL_DPLLCTRLB_LPEN_Pos)
850#define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
851#define SYSCTRL_DPLLCTRLB_WUF (0x1u << SYSCTRL_DPLLCTRLB_WUF_Pos)
852#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
853#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3u << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
854#define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)))
855#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
856#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1u /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
857#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2u /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
858#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
859#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
860#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
861#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
862#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7u << SYSCTRL_DPLLCTRLB_LTIME_Pos)
863#define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)))
864#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
865#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
866#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
867#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
868#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
869#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
870#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
871#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
872#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
873#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
874#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
875#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1u << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
876#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
877#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFu << SYSCTRL_DPLLCTRLB_DIV_Pos)
878#define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)))
879#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Fu /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
880
881/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
882#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
883typedef union {
884 struct {
885 uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
886 uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
887 uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
888 uint8_t DIV:1; /*!< bit: 3 Divider Enable */
889 uint8_t :4; /*!< bit: 4.. 7 Reserved */
890 } bit; /*!< Structure used for bit access */
891 uint8_t reg; /*!< Type used for register access */
892} SYSCTRL_DPLLSTATUS_Type;
893#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
894
895#define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
896#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00 /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
897
898#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
899#define SYSCTRL_DPLLSTATUS_LOCK (0x1u << SYSCTRL_DPLLSTATUS_LOCK_Pos)
900#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
901#define SYSCTRL_DPLLSTATUS_CLKRDY (0x1u << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
902#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
903#define SYSCTRL_DPLLSTATUS_ENABLE (0x1u << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
904#define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
905#define SYSCTRL_DPLLSTATUS_DIV (0x1u << SYSCTRL_DPLLSTATUS_DIV_Pos)
906#define SYSCTRL_DPLLSTATUS_MASK 0x0Fu /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
907
908/** \brief SYSCTRL hardware registers */
909#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
910typedef struct {
911 __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
912 __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
913 __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
914 __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
915 __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
916 RoReg8 Reserved1[0x2];
917 __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
918 RoReg8 Reserved2[0x2];
919 __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
920 __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
921 RoReg8 Reserved3[0x3];
922 __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
923 __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
924 RoReg8 Reserved4[0x2];
925 __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
926 __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
927 __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
928 RoReg8 Reserved5[0x3];
929 __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
930 RoReg8 Reserved6[0x4];
931 __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
932 RoReg8 Reserved7[0x2];
933 __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
934 __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
935 RoReg8 Reserved8[0x3];
936 __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
937 __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
938 __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
939} Sysctrl;
940#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
941
942/*@}*/
943
944#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
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