source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/sercom.h@ 136

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1/**
2 * \file
3 *
4 * \brief Component description for SERCOM
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_SERCOM_COMPONENT_
45#define _SAMD21_SERCOM_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR SERCOM */
49/* ========================================================================== */
50/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
51/*@{*/
52
53#define SERCOM_U2201
54#define REV_SERCOM 0x200
55
56/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
61 uint32_t ENABLE:1; /*!< bit: 1 Enable */
62 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
63 uint32_t :2; /*!< bit: 5.. 6 Reserved */
64 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
65 uint32_t :8; /*!< bit: 8..15 Reserved */
66 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
67 uint32_t :3; /*!< bit: 17..19 Reserved */
68 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
69 uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
70 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
71 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
72 uint32_t :1; /*!< bit: 26 Reserved */
73 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
74 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
75 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
76 uint32_t :1; /*!< bit: 31 Reserved */
77 } bit; /*!< Structure used for bit access */
78 uint32_t reg; /*!< Type used for register access */
79} SERCOM_I2CM_CTRLA_Type;
80#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
81
82#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
83#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
84
85#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
86#define SERCOM_I2CM_CTRLA_SWRST (0x1u << SERCOM_I2CM_CTRLA_SWRST_Pos)
87#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
88#define SERCOM_I2CM_CTRLA_ENABLE (0x1u << SERCOM_I2CM_CTRLA_ENABLE_Pos)
89#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
90#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7u << SERCOM_I2CM_CTRLA_MODE_Pos)
91#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))
92#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0u /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
93#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1u /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
94#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2u /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
95#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3u /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
96#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4u /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
97#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5u /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
98#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
99#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
100#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
101#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
102#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
103#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
104#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
105#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1u << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
106#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
107#define SERCOM_I2CM_CTRLA_PINOUT (0x1u << SERCOM_I2CM_CTRLA_PINOUT_Pos)
108#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
109#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3u << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
110#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))
111#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
112#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1u << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
113#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
114#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1u << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
115#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
116#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3u << SERCOM_I2CM_CTRLA_SPEED_Pos)
117#define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)))
118#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
119#define SERCOM_I2CM_CTRLA_SCLSM (0x1u << SERCOM_I2CM_CTRLA_SCLSM_Pos)
120#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
121#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3u << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
122#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))
123#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
124#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1u << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
125#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Fu /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
126
127/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
128#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
129typedef union {
130 struct {
131 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
132 uint32_t ENABLE:1; /*!< bit: 1 Enable */
133 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
134 uint32_t :2; /*!< bit: 5.. 6 Reserved */
135 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
136 uint32_t :8; /*!< bit: 8..15 Reserved */
137 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
138 uint32_t :3; /*!< bit: 17..19 Reserved */
139 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
140 uint32_t :1; /*!< bit: 22 Reserved */
141 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
142 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
143 uint32_t :1; /*!< bit: 26 Reserved */
144 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
145 uint32_t :2; /*!< bit: 28..29 Reserved */
146 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
147 uint32_t :1; /*!< bit: 31 Reserved */
148 } bit; /*!< Structure used for bit access */
149 uint32_t reg; /*!< Type used for register access */
150} SERCOM_I2CS_CTRLA_Type;
151#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
152
153#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
154#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
155
156#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
157#define SERCOM_I2CS_CTRLA_SWRST (0x1u << SERCOM_I2CS_CTRLA_SWRST_Pos)
158#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
159#define SERCOM_I2CS_CTRLA_ENABLE (0x1u << SERCOM_I2CS_CTRLA_ENABLE_Pos)
160#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
161#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7u << SERCOM_I2CS_CTRLA_MODE_Pos)
162#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))
163#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0u /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
164#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1u /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
165#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2u /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
166#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3u /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
167#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4u /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
168#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5u /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
169#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
170#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
171#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
172#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
173#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
174#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
175#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
176#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1u << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
177#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
178#define SERCOM_I2CS_CTRLA_PINOUT (0x1u << SERCOM_I2CS_CTRLA_PINOUT_Pos)
179#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
180#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3u << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
181#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))
182#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
183#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1u << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
184#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
185#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3u << SERCOM_I2CS_CTRLA_SPEED_Pos)
186#define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)))
187#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
188#define SERCOM_I2CS_CTRLA_SCLSM (0x1u << SERCOM_I2CS_CTRLA_SCLSM_Pos)
189#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
190#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1u << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
191#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Fu /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
192
193/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
194#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
195typedef union {
196 struct {
197 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
198 uint32_t ENABLE:1; /*!< bit: 1 Enable */
199 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
200 uint32_t :2; /*!< bit: 5.. 6 Reserved */
201 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
202 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
203 uint32_t :7; /*!< bit: 9..15 Reserved */
204 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
205 uint32_t :2; /*!< bit: 18..19 Reserved */
206 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
207 uint32_t :2; /*!< bit: 22..23 Reserved */
208 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
209 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
210 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
211 uint32_t DORD:1; /*!< bit: 30 Data Order */
212 uint32_t :1; /*!< bit: 31 Reserved */
213 } bit; /*!< Structure used for bit access */
214 uint32_t reg; /*!< Type used for register access */
215} SERCOM_SPI_CTRLA_Type;
216#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
217
218#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
219#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
220
221#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
222#define SERCOM_SPI_CTRLA_SWRST (0x1u << SERCOM_SPI_CTRLA_SWRST_Pos)
223#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
224#define SERCOM_SPI_CTRLA_ENABLE (0x1u << SERCOM_SPI_CTRLA_ENABLE_Pos)
225#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
226#define SERCOM_SPI_CTRLA_MODE_Msk (0x7u << SERCOM_SPI_CTRLA_MODE_Pos)
227#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))
228#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0u /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
229#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1u /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
230#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2u /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
231#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3u /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
232#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4u /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
233#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5u /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
234#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
235#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
236#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
237#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
238#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
239#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
240#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
241#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1u << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
242#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
243#define SERCOM_SPI_CTRLA_IBON (0x1u << SERCOM_SPI_CTRLA_IBON_Pos)
244#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
245#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3u << SERCOM_SPI_CTRLA_DOPO_Pos)
246#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)))
247#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
248#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3u << SERCOM_SPI_CTRLA_DIPO_Pos)
249#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))
250#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
251#define SERCOM_SPI_CTRLA_FORM_Msk (0xFu << SERCOM_SPI_CTRLA_FORM_Pos)
252#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))
253#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
254#define SERCOM_SPI_CTRLA_CPHA (0x1u << SERCOM_SPI_CTRLA_CPHA_Pos)
255#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
256#define SERCOM_SPI_CTRLA_CPOL (0x1u << SERCOM_SPI_CTRLA_CPOL_Pos)
257#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
258#define SERCOM_SPI_CTRLA_DORD (0x1u << SERCOM_SPI_CTRLA_DORD_Pos)
259#define SERCOM_SPI_CTRLA_MASK 0x7F33019Fu /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
260
261/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
262#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
263typedef union {
264 struct {
265 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
266 uint32_t ENABLE:1; /*!< bit: 1 Enable */
267 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
268 uint32_t :2; /*!< bit: 5.. 6 Reserved */
269 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
270 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
271 uint32_t :4; /*!< bit: 9..12 Reserved */
272 uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
273 uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
274 uint32_t :2; /*!< bit: 18..19 Reserved */
275 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
276 uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
277 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
278 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
279 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
280 uint32_t DORD:1; /*!< bit: 30 Data Order */
281 uint32_t :1; /*!< bit: 31 Reserved */
282 } bit; /*!< Structure used for bit access */
283 uint32_t reg; /*!< Type used for register access */
284} SERCOM_USART_CTRLA_Type;
285#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
286
287#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
288#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
289
290#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
291#define SERCOM_USART_CTRLA_SWRST (0x1u << SERCOM_USART_CTRLA_SWRST_Pos)
292#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
293#define SERCOM_USART_CTRLA_ENABLE (0x1u << SERCOM_USART_CTRLA_ENABLE_Pos)
294#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
295#define SERCOM_USART_CTRLA_MODE_Msk (0x7u << SERCOM_USART_CTRLA_MODE_Pos)
296#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))
297#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0u /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
298#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1u /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
299#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2u /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
300#define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3u /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
301#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4u /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
302#define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5u /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
303#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
304#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
305#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
306#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
307#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
308#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
309#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
310#define SERCOM_USART_CTRLA_RUNSTDBY (0x1u << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
311#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
312#define SERCOM_USART_CTRLA_IBON (0x1u << SERCOM_USART_CTRLA_IBON_Pos)
313#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
314#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7u << SERCOM_USART_CTRLA_SAMPR_Pos)
315#define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)))
316#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
317#define SERCOM_USART_CTRLA_TXPO_Msk (0x3u << SERCOM_USART_CTRLA_TXPO_Pos)
318#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)))
319#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
320#define SERCOM_USART_CTRLA_RXPO_Msk (0x3u << SERCOM_USART_CTRLA_RXPO_Pos)
321#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
322#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
323#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3u << SERCOM_USART_CTRLA_SAMPA_Pos)
324#define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)))
325#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
326#define SERCOM_USART_CTRLA_FORM_Msk (0xFu << SERCOM_USART_CTRLA_FORM_Pos)
327#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))
328#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
329#define SERCOM_USART_CTRLA_CMODE (0x1u << SERCOM_USART_CTRLA_CMODE_Pos)
330#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
331#define SERCOM_USART_CTRLA_CPOL (0x1u << SERCOM_USART_CTRLA_CPOL_Pos)
332#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
333#define SERCOM_USART_CTRLA_DORD (0x1u << SERCOM_USART_CTRLA_DORD_Pos)
334#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Fu /**< \brief (SERCOM_USART_CTRLA) MASK Register */
335
336/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
337#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
338typedef union {
339 struct {
340 uint32_t :8; /*!< bit: 0.. 7 Reserved */
341 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
342 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
343 uint32_t :6; /*!< bit: 10..15 Reserved */
344 uint32_t CMD:2; /*!< bit: 16..17 Command */
345 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
346 uint32_t :13; /*!< bit: 19..31 Reserved */
347 } bit; /*!< Structure used for bit access */
348 uint32_t reg; /*!< Type used for register access */
349} SERCOM_I2CM_CTRLB_Type;
350#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
351
352#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
353#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
354
355#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
356#define SERCOM_I2CM_CTRLB_SMEN (0x1u << SERCOM_I2CM_CTRLB_SMEN_Pos)
357#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
358#define SERCOM_I2CM_CTRLB_QCEN (0x1u << SERCOM_I2CM_CTRLB_QCEN_Pos)
359#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
360#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3u << SERCOM_I2CM_CTRLB_CMD_Pos)
361#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))
362#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
363#define SERCOM_I2CM_CTRLB_ACKACT (0x1u << SERCOM_I2CM_CTRLB_ACKACT_Pos)
364#define SERCOM_I2CM_CTRLB_MASK 0x00070300u /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
365
366/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
367#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
368typedef union {
369 struct {
370 uint32_t :8; /*!< bit: 0.. 7 Reserved */
371 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
372 uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
373 uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
374 uint32_t :3; /*!< bit: 11..13 Reserved */
375 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
376 uint32_t CMD:2; /*!< bit: 16..17 Command */
377 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
378 uint32_t :13; /*!< bit: 19..31 Reserved */
379 } bit; /*!< Structure used for bit access */
380 uint32_t reg; /*!< Type used for register access */
381} SERCOM_I2CS_CTRLB_Type;
382#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
383
384#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
385#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
386
387#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
388#define SERCOM_I2CS_CTRLB_SMEN (0x1u << SERCOM_I2CS_CTRLB_SMEN_Pos)
389#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
390#define SERCOM_I2CS_CTRLB_GCMD (0x1u << SERCOM_I2CS_CTRLB_GCMD_Pos)
391#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
392#define SERCOM_I2CS_CTRLB_AACKEN (0x1u << SERCOM_I2CS_CTRLB_AACKEN_Pos)
393#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
394#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3u << SERCOM_I2CS_CTRLB_AMODE_Pos)
395#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))
396#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
397#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3u << SERCOM_I2CS_CTRLB_CMD_Pos)
398#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))
399#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
400#define SERCOM_I2CS_CTRLB_ACKACT (0x1u << SERCOM_I2CS_CTRLB_ACKACT_Pos)
401#define SERCOM_I2CS_CTRLB_MASK 0x0007C700u /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
402
403/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
404#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
405typedef union {
406 struct {
407 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
408 uint32_t :3; /*!< bit: 3.. 5 Reserved */
409 uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
410 uint32_t :2; /*!< bit: 7.. 8 Reserved */
411 uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
412 uint32_t :3; /*!< bit: 10..12 Reserved */
413 uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
414 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
415 uint32_t :1; /*!< bit: 16 Reserved */
416 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
417 uint32_t :14; /*!< bit: 18..31 Reserved */
418 } bit; /*!< Structure used for bit access */
419 uint32_t reg; /*!< Type used for register access */
420} SERCOM_SPI_CTRLB_Type;
421#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
422
423#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
424#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
425
426#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
427#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7u << SERCOM_SPI_CTRLB_CHSIZE_Pos)
428#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))
429#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
430#define SERCOM_SPI_CTRLB_PLOADEN (0x1u << SERCOM_SPI_CTRLB_PLOADEN_Pos)
431#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
432#define SERCOM_SPI_CTRLB_SSDE (0x1u << SERCOM_SPI_CTRLB_SSDE_Pos)
433#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
434#define SERCOM_SPI_CTRLB_MSSEN (0x1u << SERCOM_SPI_CTRLB_MSSEN_Pos)
435#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
436#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3u << SERCOM_SPI_CTRLB_AMODE_Pos)
437#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))
438#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
439#define SERCOM_SPI_CTRLB_RXEN (0x1u << SERCOM_SPI_CTRLB_RXEN_Pos)
440#define SERCOM_SPI_CTRLB_MASK 0x0002E247u /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
441
442/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
443#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
444typedef union {
445 struct {
446 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
447 uint32_t :3; /*!< bit: 3.. 5 Reserved */
448 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
449 uint32_t :1; /*!< bit: 7 Reserved */
450 uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
451 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
452 uint32_t ENC:1; /*!< bit: 10 Encoding Format */
453 uint32_t :2; /*!< bit: 11..12 Reserved */
454 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
455 uint32_t :2; /*!< bit: 14..15 Reserved */
456 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
457 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
458 uint32_t :14; /*!< bit: 18..31 Reserved */
459 } bit; /*!< Structure used for bit access */
460 uint32_t reg; /*!< Type used for register access */
461} SERCOM_USART_CTRLB_Type;
462#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
463
464#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
465#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
466
467#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
468#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7u << SERCOM_USART_CTRLB_CHSIZE_Pos)
469#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))
470#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
471#define SERCOM_USART_CTRLB_SBMODE (0x1u << SERCOM_USART_CTRLB_SBMODE_Pos)
472#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
473#define SERCOM_USART_CTRLB_COLDEN (0x1u << SERCOM_USART_CTRLB_COLDEN_Pos)
474#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
475#define SERCOM_USART_CTRLB_SFDE (0x1u << SERCOM_USART_CTRLB_SFDE_Pos)
476#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
477#define SERCOM_USART_CTRLB_ENC (0x1u << SERCOM_USART_CTRLB_ENC_Pos)
478#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
479#define SERCOM_USART_CTRLB_PMODE (0x1u << SERCOM_USART_CTRLB_PMODE_Pos)
480#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
481#define SERCOM_USART_CTRLB_TXEN (0x1u << SERCOM_USART_CTRLB_TXEN_Pos)
482#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
483#define SERCOM_USART_CTRLB_RXEN (0x1u << SERCOM_USART_CTRLB_RXEN_Pos)
484#define SERCOM_USART_CTRLB_MASK 0x00032747u /**< \brief (SERCOM_USART_CTRLB) MASK Register */
485
486/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
487#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
488typedef union {
489 struct {
490 uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
491 uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
492 uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
493 uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
494 } bit; /*!< Structure used for bit access */
495 uint32_t reg; /*!< Type used for register access */
496} SERCOM_I2CM_BAUD_Type;
497#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
498
499#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
500#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
501
502#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
503#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFu << SERCOM_I2CM_BAUD_BAUD_Pos)
504#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))
505#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
506#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFu << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
507#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))
508#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
509#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFu << SERCOM_I2CM_BAUD_HSBAUD_Pos)
510#define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)))
511#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
512#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFu << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
513#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)))
514#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFu /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
515
516/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
517#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
518typedef union {
519 struct {
520 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
521 } bit; /*!< Structure used for bit access */
522 uint8_t reg; /*!< Type used for register access */
523} SERCOM_SPI_BAUD_Type;
524#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
525
526#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
527#define SERCOM_SPI_BAUD_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
528
529#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
530#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFu << SERCOM_SPI_BAUD_BAUD_Pos)
531#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))
532#define SERCOM_SPI_BAUD_MASK 0xFFu /**< \brief (SERCOM_SPI_BAUD) MASK Register */
533
534/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
535#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
536typedef union {
537 struct {
538 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
539 } bit; /*!< Structure used for bit access */
540 struct { // FRAC mode
541 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
542 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
543 } FRAC; /*!< Structure used for FRAC */
544 struct { // FRACFP mode
545 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
546 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
547 } FRACFP; /*!< Structure used for FRACFP */
548 struct { // USARTFP mode
549 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
550 } USARTFP; /*!< Structure used for USARTFP */
551 uint16_t reg; /*!< Type used for register access */
552} SERCOM_USART_BAUD_Type;
553#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
554
555#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
556#define SERCOM_USART_BAUD_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
557
558#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
559#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFu << SERCOM_USART_BAUD_BAUD_Pos)
560#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))
561#define SERCOM_USART_BAUD_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD) MASK Register */
562
563// FRAC mode
564#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
565#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFu << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
566#define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)))
567#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
568#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7u << SERCOM_USART_BAUD_FRAC_FP_Pos)
569#define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)))
570#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
571
572// FRACFP mode
573#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
574#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFu << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
575#define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)))
576#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
577#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7u << SERCOM_USART_BAUD_FRACFP_FP_Pos)
578#define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)))
579#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
580
581// USARTFP mode
582#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
583#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFu << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
584#define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)))
585#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
586
587/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
588#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
589typedef union {
590 struct {
591 uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
592 } bit; /*!< Structure used for bit access */
593 uint8_t reg; /*!< Type used for register access */
594} SERCOM_USART_RXPL_Type;
595#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
596
597#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
598#define SERCOM_USART_RXPL_RESETVALUE 0x00 /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
599
600#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
601#define SERCOM_USART_RXPL_RXPL_Msk (0xFFu << SERCOM_USART_RXPL_RXPL_Pos)
602#define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)))
603#define SERCOM_USART_RXPL_MASK 0xFFu /**< \brief (SERCOM_USART_RXPL) MASK Register */
604
605/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
606#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
607typedef union {
608 struct {
609 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
610 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
611 uint8_t :5; /*!< bit: 2.. 6 Reserved */
612 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
613 } bit; /*!< Structure used for bit access */
614 uint8_t reg; /*!< Type used for register access */
615} SERCOM_I2CM_INTENCLR_Type;
616#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
617
618#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
619#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
620
621#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
622#define SERCOM_I2CM_INTENCLR_MB (0x1u << SERCOM_I2CM_INTENCLR_MB_Pos)
623#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
624#define SERCOM_I2CM_INTENCLR_SB (0x1u << SERCOM_I2CM_INTENCLR_SB_Pos)
625#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
626#define SERCOM_I2CM_INTENCLR_ERROR (0x1u << SERCOM_I2CM_INTENCLR_ERROR_Pos)
627#define SERCOM_I2CM_INTENCLR_MASK 0x83u /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
628
629/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
630#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
631typedef union {
632 struct {
633 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
634 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
635 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
636 uint8_t :4; /*!< bit: 3.. 6 Reserved */
637 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
638 } bit; /*!< Structure used for bit access */
639 uint8_t reg; /*!< Type used for register access */
640} SERCOM_I2CS_INTENCLR_Type;
641#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
642
643#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
644#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
645
646#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
647#define SERCOM_I2CS_INTENCLR_PREC (0x1u << SERCOM_I2CS_INTENCLR_PREC_Pos)
648#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
649#define SERCOM_I2CS_INTENCLR_AMATCH (0x1u << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
650#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
651#define SERCOM_I2CS_INTENCLR_DRDY (0x1u << SERCOM_I2CS_INTENCLR_DRDY_Pos)
652#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
653#define SERCOM_I2CS_INTENCLR_ERROR (0x1u << SERCOM_I2CS_INTENCLR_ERROR_Pos)
654#define SERCOM_I2CS_INTENCLR_MASK 0x87u /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
655
656/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
657#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
658typedef union {
659 struct {
660 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
661 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
662 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
663 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
664 uint8_t :3; /*!< bit: 4.. 6 Reserved */
665 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
666 } bit; /*!< Structure used for bit access */
667 uint8_t reg; /*!< Type used for register access */
668} SERCOM_SPI_INTENCLR_Type;
669#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
670
671#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
672#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
673
674#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
675#define SERCOM_SPI_INTENCLR_DRE (0x1u << SERCOM_SPI_INTENCLR_DRE_Pos)
676#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
677#define SERCOM_SPI_INTENCLR_TXC (0x1u << SERCOM_SPI_INTENCLR_TXC_Pos)
678#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
679#define SERCOM_SPI_INTENCLR_RXC (0x1u << SERCOM_SPI_INTENCLR_RXC_Pos)
680#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
681#define SERCOM_SPI_INTENCLR_SSL (0x1u << SERCOM_SPI_INTENCLR_SSL_Pos)
682#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
683#define SERCOM_SPI_INTENCLR_ERROR (0x1u << SERCOM_SPI_INTENCLR_ERROR_Pos)
684#define SERCOM_SPI_INTENCLR_MASK 0x8Fu /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
685
686/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
687#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
688typedef union {
689 struct {
690 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
691 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
692 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
693 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
694 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
695 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
696 uint8_t :1; /*!< bit: 6 Reserved */
697 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
698 } bit; /*!< Structure used for bit access */
699 uint8_t reg; /*!< Type used for register access */
700} SERCOM_USART_INTENCLR_Type;
701#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
702
703#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
704#define SERCOM_USART_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
705
706#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
707#define SERCOM_USART_INTENCLR_DRE (0x1u << SERCOM_USART_INTENCLR_DRE_Pos)
708#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
709#define SERCOM_USART_INTENCLR_TXC (0x1u << SERCOM_USART_INTENCLR_TXC_Pos)
710#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
711#define SERCOM_USART_INTENCLR_RXC (0x1u << SERCOM_USART_INTENCLR_RXC_Pos)
712#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
713#define SERCOM_USART_INTENCLR_RXS (0x1u << SERCOM_USART_INTENCLR_RXS_Pos)
714#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
715#define SERCOM_USART_INTENCLR_CTSIC (0x1u << SERCOM_USART_INTENCLR_CTSIC_Pos)
716#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
717#define SERCOM_USART_INTENCLR_RXBRK (0x1u << SERCOM_USART_INTENCLR_RXBRK_Pos)
718#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
719#define SERCOM_USART_INTENCLR_ERROR (0x1u << SERCOM_USART_INTENCLR_ERROR_Pos)
720#define SERCOM_USART_INTENCLR_MASK 0xBFu /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
721
722/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
723#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
724typedef union {
725 struct {
726 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
727 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
728 uint8_t :5; /*!< bit: 2.. 6 Reserved */
729 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
730 } bit; /*!< Structure used for bit access */
731 uint8_t reg; /*!< Type used for register access */
732} SERCOM_I2CM_INTENSET_Type;
733#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
734
735#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
736#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
737
738#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
739#define SERCOM_I2CM_INTENSET_MB (0x1u << SERCOM_I2CM_INTENSET_MB_Pos)
740#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
741#define SERCOM_I2CM_INTENSET_SB (0x1u << SERCOM_I2CM_INTENSET_SB_Pos)
742#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
743#define SERCOM_I2CM_INTENSET_ERROR (0x1u << SERCOM_I2CM_INTENSET_ERROR_Pos)
744#define SERCOM_I2CM_INTENSET_MASK 0x83u /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
745
746/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
747#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
748typedef union {
749 struct {
750 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
751 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
752 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
753 uint8_t :4; /*!< bit: 3.. 6 Reserved */
754 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
755 } bit; /*!< Structure used for bit access */
756 uint8_t reg; /*!< Type used for register access */
757} SERCOM_I2CS_INTENSET_Type;
758#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
759
760#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
761#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
762
763#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
764#define SERCOM_I2CS_INTENSET_PREC (0x1u << SERCOM_I2CS_INTENSET_PREC_Pos)
765#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
766#define SERCOM_I2CS_INTENSET_AMATCH (0x1u << SERCOM_I2CS_INTENSET_AMATCH_Pos)
767#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
768#define SERCOM_I2CS_INTENSET_DRDY (0x1u << SERCOM_I2CS_INTENSET_DRDY_Pos)
769#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
770#define SERCOM_I2CS_INTENSET_ERROR (0x1u << SERCOM_I2CS_INTENSET_ERROR_Pos)
771#define SERCOM_I2CS_INTENSET_MASK 0x87u /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
772
773/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
774#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
775typedef union {
776 struct {
777 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
778 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
779 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
780 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
781 uint8_t :3; /*!< bit: 4.. 6 Reserved */
782 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
783 } bit; /*!< Structure used for bit access */
784 uint8_t reg; /*!< Type used for register access */
785} SERCOM_SPI_INTENSET_Type;
786#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
787
788#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
789#define SERCOM_SPI_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
790
791#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
792#define SERCOM_SPI_INTENSET_DRE (0x1u << SERCOM_SPI_INTENSET_DRE_Pos)
793#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
794#define SERCOM_SPI_INTENSET_TXC (0x1u << SERCOM_SPI_INTENSET_TXC_Pos)
795#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
796#define SERCOM_SPI_INTENSET_RXC (0x1u << SERCOM_SPI_INTENSET_RXC_Pos)
797#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
798#define SERCOM_SPI_INTENSET_SSL (0x1u << SERCOM_SPI_INTENSET_SSL_Pos)
799#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
800#define SERCOM_SPI_INTENSET_ERROR (0x1u << SERCOM_SPI_INTENSET_ERROR_Pos)
801#define SERCOM_SPI_INTENSET_MASK 0x8Fu /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
802
803/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
804#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
805typedef union {
806 struct {
807 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
808 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
809 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
810 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
811 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
812 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
813 uint8_t :1; /*!< bit: 6 Reserved */
814 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
815 } bit; /*!< Structure used for bit access */
816 uint8_t reg; /*!< Type used for register access */
817} SERCOM_USART_INTENSET_Type;
818#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
819
820#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
821#define SERCOM_USART_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
822
823#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
824#define SERCOM_USART_INTENSET_DRE (0x1u << SERCOM_USART_INTENSET_DRE_Pos)
825#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
826#define SERCOM_USART_INTENSET_TXC (0x1u << SERCOM_USART_INTENSET_TXC_Pos)
827#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
828#define SERCOM_USART_INTENSET_RXC (0x1u << SERCOM_USART_INTENSET_RXC_Pos)
829#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
830#define SERCOM_USART_INTENSET_RXS (0x1u << SERCOM_USART_INTENSET_RXS_Pos)
831#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
832#define SERCOM_USART_INTENSET_CTSIC (0x1u << SERCOM_USART_INTENSET_CTSIC_Pos)
833#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
834#define SERCOM_USART_INTENSET_RXBRK (0x1u << SERCOM_USART_INTENSET_RXBRK_Pos)
835#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
836#define SERCOM_USART_INTENSET_ERROR (0x1u << SERCOM_USART_INTENSET_ERROR_Pos)
837#define SERCOM_USART_INTENSET_MASK 0xBFu /**< \brief (SERCOM_USART_INTENSET) MASK Register */
838
839/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
840#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
841typedef union {
842 struct {
843 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
844 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
845 uint8_t :5; /*!< bit: 2.. 6 Reserved */
846 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
847 } bit; /*!< Structure used for bit access */
848 uint8_t reg; /*!< Type used for register access */
849} SERCOM_I2CM_INTFLAG_Type;
850#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
851
852#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
853#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
854
855#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
856#define SERCOM_I2CM_INTFLAG_MB (0x1u << SERCOM_I2CM_INTFLAG_MB_Pos)
857#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
858#define SERCOM_I2CM_INTFLAG_SB (0x1u << SERCOM_I2CM_INTFLAG_SB_Pos)
859#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
860#define SERCOM_I2CM_INTFLAG_ERROR (0x1u << SERCOM_I2CM_INTFLAG_ERROR_Pos)
861#define SERCOM_I2CM_INTFLAG_MASK 0x83u /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
862
863/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
864#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
865typedef union {
866 struct {
867 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
868 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
869 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
870 uint8_t :4; /*!< bit: 3.. 6 Reserved */
871 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
872 } bit; /*!< Structure used for bit access */
873 uint8_t reg; /*!< Type used for register access */
874} SERCOM_I2CS_INTFLAG_Type;
875#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
876
877#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
878#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
879
880#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
881#define SERCOM_I2CS_INTFLAG_PREC (0x1u << SERCOM_I2CS_INTFLAG_PREC_Pos)
882#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
883#define SERCOM_I2CS_INTFLAG_AMATCH (0x1u << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
884#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
885#define SERCOM_I2CS_INTFLAG_DRDY (0x1u << SERCOM_I2CS_INTFLAG_DRDY_Pos)
886#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
887#define SERCOM_I2CS_INTFLAG_ERROR (0x1u << SERCOM_I2CS_INTFLAG_ERROR_Pos)
888#define SERCOM_I2CS_INTFLAG_MASK 0x87u /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
889
890/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
891#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
892typedef union {
893 struct {
894 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
895 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
896 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
897 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
898 uint8_t :3; /*!< bit: 4.. 6 Reserved */
899 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
900 } bit; /*!< Structure used for bit access */
901 uint8_t reg; /*!< Type used for register access */
902} SERCOM_SPI_INTFLAG_Type;
903#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
904
905#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
906#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
907
908#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
909#define SERCOM_SPI_INTFLAG_DRE (0x1u << SERCOM_SPI_INTFLAG_DRE_Pos)
910#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
911#define SERCOM_SPI_INTFLAG_TXC (0x1u << SERCOM_SPI_INTFLAG_TXC_Pos)
912#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
913#define SERCOM_SPI_INTFLAG_RXC (0x1u << SERCOM_SPI_INTFLAG_RXC_Pos)
914#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
915#define SERCOM_SPI_INTFLAG_SSL (0x1u << SERCOM_SPI_INTFLAG_SSL_Pos)
916#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
917#define SERCOM_SPI_INTFLAG_ERROR (0x1u << SERCOM_SPI_INTFLAG_ERROR_Pos)
918#define SERCOM_SPI_INTFLAG_MASK 0x8Fu /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
919
920/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
921#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
922typedef union {
923 struct {
924 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
925 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
926 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
927 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
928 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
929 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
930 uint8_t :1; /*!< bit: 6 Reserved */
931 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
932 } bit; /*!< Structure used for bit access */
933 uint8_t reg; /*!< Type used for register access */
934} SERCOM_USART_INTFLAG_Type;
935#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
936
937#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
938#define SERCOM_USART_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
939
940#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
941#define SERCOM_USART_INTFLAG_DRE (0x1u << SERCOM_USART_INTFLAG_DRE_Pos)
942#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
943#define SERCOM_USART_INTFLAG_TXC (0x1u << SERCOM_USART_INTFLAG_TXC_Pos)
944#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
945#define SERCOM_USART_INTFLAG_RXC (0x1u << SERCOM_USART_INTFLAG_RXC_Pos)
946#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
947#define SERCOM_USART_INTFLAG_RXS (0x1u << SERCOM_USART_INTFLAG_RXS_Pos)
948#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
949#define SERCOM_USART_INTFLAG_CTSIC (0x1u << SERCOM_USART_INTFLAG_CTSIC_Pos)
950#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
951#define SERCOM_USART_INTFLAG_RXBRK (0x1u << SERCOM_USART_INTFLAG_RXBRK_Pos)
952#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
953#define SERCOM_USART_INTFLAG_ERROR (0x1u << SERCOM_USART_INTFLAG_ERROR_Pos)
954#define SERCOM_USART_INTFLAG_MASK 0xBFu /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
955
956/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
957#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
958typedef union {
959 struct {
960 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
961 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
962 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
963 uint16_t :1; /*!< bit: 3 Reserved */
964 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
965 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
966 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
967 uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
968 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
969 uint16_t LENERR:1; /*!< bit: 10 Length Error */
970 uint16_t :5; /*!< bit: 11..15 Reserved */
971 } bit; /*!< Structure used for bit access */
972 uint16_t reg; /*!< Type used for register access */
973} SERCOM_I2CM_STATUS_Type;
974#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
975
976#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
977#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
978
979#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
980#define SERCOM_I2CM_STATUS_BUSERR (0x1u << SERCOM_I2CM_STATUS_BUSERR_Pos)
981#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
982#define SERCOM_I2CM_STATUS_ARBLOST (0x1u << SERCOM_I2CM_STATUS_ARBLOST_Pos)
983#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
984#define SERCOM_I2CM_STATUS_RXNACK (0x1u << SERCOM_I2CM_STATUS_RXNACK_Pos)
985#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
986#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3u << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
987#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))
988#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
989#define SERCOM_I2CM_STATUS_LOWTOUT (0x1u << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
990#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
991#define SERCOM_I2CM_STATUS_CLKHOLD (0x1u << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
992#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
993#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1u << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
994#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
995#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1u << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
996#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
997#define SERCOM_I2CM_STATUS_LENERR (0x1u << SERCOM_I2CM_STATUS_LENERR_Pos)
998#define SERCOM_I2CM_STATUS_MASK 0x07F7u /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
999
1000/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
1001#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1002typedef union {
1003 struct {
1004 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
1005 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
1006 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
1007 uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
1008 uint16_t SR:1; /*!< bit: 4 Repeated Start */
1009 uint16_t :1; /*!< bit: 5 Reserved */
1010 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
1011 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
1012 uint16_t :1; /*!< bit: 8 Reserved */
1013 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
1014 uint16_t HS:1; /*!< bit: 10 High Speed */
1015 uint16_t :5; /*!< bit: 11..15 Reserved */
1016 } bit; /*!< Structure used for bit access */
1017 uint16_t reg; /*!< Type used for register access */
1018} SERCOM_I2CS_STATUS_Type;
1019#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1020
1021#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
1022#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
1023
1024#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
1025#define SERCOM_I2CS_STATUS_BUSERR (0x1u << SERCOM_I2CS_STATUS_BUSERR_Pos)
1026#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
1027#define SERCOM_I2CS_STATUS_COLL (0x1u << SERCOM_I2CS_STATUS_COLL_Pos)
1028#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
1029#define SERCOM_I2CS_STATUS_RXNACK (0x1u << SERCOM_I2CS_STATUS_RXNACK_Pos)
1030#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
1031#define SERCOM_I2CS_STATUS_DIR (0x1u << SERCOM_I2CS_STATUS_DIR_Pos)
1032#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
1033#define SERCOM_I2CS_STATUS_SR (0x1u << SERCOM_I2CS_STATUS_SR_Pos)
1034#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
1035#define SERCOM_I2CS_STATUS_LOWTOUT (0x1u << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
1036#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
1037#define SERCOM_I2CS_STATUS_CLKHOLD (0x1u << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
1038#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
1039#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1u << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
1040#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
1041#define SERCOM_I2CS_STATUS_HS (0x1u << SERCOM_I2CS_STATUS_HS_Pos)
1042#define SERCOM_I2CS_STATUS_MASK 0x06DFu /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
1043
1044/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
1045#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1046typedef union {
1047 struct {
1048 uint16_t :2; /*!< bit: 0.. 1 Reserved */
1049 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
1050 uint16_t :13; /*!< bit: 3..15 Reserved */
1051 } bit; /*!< Structure used for bit access */
1052 uint16_t reg; /*!< Type used for register access */
1053} SERCOM_SPI_STATUS_Type;
1054#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1055
1056#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
1057#define SERCOM_SPI_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
1058
1059#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
1060#define SERCOM_SPI_STATUS_BUFOVF (0x1u << SERCOM_SPI_STATUS_BUFOVF_Pos)
1061#define SERCOM_SPI_STATUS_MASK 0x0004u /**< \brief (SERCOM_SPI_STATUS) MASK Register */
1062
1063/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
1064#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1065typedef union {
1066 struct {
1067 uint16_t PERR:1; /*!< bit: 0 Parity Error */
1068 uint16_t FERR:1; /*!< bit: 1 Frame Error */
1069 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
1070 uint16_t CTS:1; /*!< bit: 3 Clear To Send */
1071 uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
1072 uint16_t COLL:1; /*!< bit: 5 Collision Detected */
1073 uint16_t :10; /*!< bit: 6..15 Reserved */
1074 } bit; /*!< Structure used for bit access */
1075 uint16_t reg; /*!< Type used for register access */
1076} SERCOM_USART_STATUS_Type;
1077#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1078
1079#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
1080#define SERCOM_USART_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
1081
1082#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
1083#define SERCOM_USART_STATUS_PERR (0x1u << SERCOM_USART_STATUS_PERR_Pos)
1084#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
1085#define SERCOM_USART_STATUS_FERR (0x1u << SERCOM_USART_STATUS_FERR_Pos)
1086#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
1087#define SERCOM_USART_STATUS_BUFOVF (0x1u << SERCOM_USART_STATUS_BUFOVF_Pos)
1088#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
1089#define SERCOM_USART_STATUS_CTS (0x1u << SERCOM_USART_STATUS_CTS_Pos)
1090#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
1091#define SERCOM_USART_STATUS_ISF (0x1u << SERCOM_USART_STATUS_ISF_Pos)
1092#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
1093#define SERCOM_USART_STATUS_COLL (0x1u << SERCOM_USART_STATUS_COLL_Pos)
1094#define SERCOM_USART_STATUS_MASK 0x003Fu /**< \brief (SERCOM_USART_STATUS) MASK Register */
1095
1096/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
1097#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1098typedef union {
1099 struct {
1100 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
1101 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
1102 uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
1103 uint32_t :29; /*!< bit: 3..31 Reserved */
1104 } bit; /*!< Structure used for bit access */
1105 uint32_t reg; /*!< Type used for register access */
1106} SERCOM_I2CM_SYNCBUSY_Type;
1107#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1108
1109#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
1110#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
1111
1112#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
1113#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1u << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
1114#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
1115#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1u << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
1116#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
1117#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1u << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
1118#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007u /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
1119
1120/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
1121#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1122typedef union {
1123 struct {
1124 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
1125 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
1126 uint32_t :30; /*!< bit: 2..31 Reserved */
1127 } bit; /*!< Structure used for bit access */
1128 uint32_t reg; /*!< Type used for register access */
1129} SERCOM_I2CS_SYNCBUSY_Type;
1130#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1131
1132#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
1133#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
1134
1135#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
1136#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1u << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
1137#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
1138#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1u << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
1139#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003u /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
1140
1141/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
1142#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1143typedef union {
1144 struct {
1145 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
1146 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
1147 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
1148 uint32_t :29; /*!< bit: 3..31 Reserved */
1149 } bit; /*!< Structure used for bit access */
1150 uint32_t reg; /*!< Type used for register access */
1151} SERCOM_SPI_SYNCBUSY_Type;
1152#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1153
1154#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
1155#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
1156
1157#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
1158#define SERCOM_SPI_SYNCBUSY_SWRST (0x1u << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
1159#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
1160#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1u << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
1161#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
1162#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1u << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
1163#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007u /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
1164
1165/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
1166#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1167typedef union {
1168 struct {
1169 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
1170 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
1171 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
1172 uint32_t :29; /*!< bit: 3..31 Reserved */
1173 } bit; /*!< Structure used for bit access */
1174 uint32_t reg; /*!< Type used for register access */
1175} SERCOM_USART_SYNCBUSY_Type;
1176#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1177
1178#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
1179#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
1180
1181#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
1182#define SERCOM_USART_SYNCBUSY_SWRST (0x1u << SERCOM_USART_SYNCBUSY_SWRST_Pos)
1183#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
1184#define SERCOM_USART_SYNCBUSY_ENABLE (0x1u << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
1185#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
1186#define SERCOM_USART_SYNCBUSY_CTRLB (0x1u << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
1187#define SERCOM_USART_SYNCBUSY_MASK 0x00000007u /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
1188
1189/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
1190#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1191typedef union {
1192 struct {
1193 uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
1194 uint32_t :2; /*!< bit: 11..12 Reserved */
1195 uint32_t LENEN:1; /*!< bit: 13 Length Enable */
1196 uint32_t HS:1; /*!< bit: 14 High Speed Mode */
1197 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
1198 uint32_t LEN:8; /*!< bit: 16..23 Length */
1199 uint32_t :8; /*!< bit: 24..31 Reserved */
1200 } bit; /*!< Structure used for bit access */
1201 uint32_t reg; /*!< Type used for register access */
1202} SERCOM_I2CM_ADDR_Type;
1203#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1204
1205#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
1206#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
1207
1208#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
1209#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFu << SERCOM_I2CM_ADDR_ADDR_Pos)
1210#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))
1211#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
1212#define SERCOM_I2CM_ADDR_LENEN (0x1u << SERCOM_I2CM_ADDR_LENEN_Pos)
1213#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
1214#define SERCOM_I2CM_ADDR_HS (0x1u << SERCOM_I2CM_ADDR_HS_Pos)
1215#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
1216#define SERCOM_I2CM_ADDR_TENBITEN (0x1u << SERCOM_I2CM_ADDR_TENBITEN_Pos)
1217#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
1218#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFu << SERCOM_I2CM_ADDR_LEN_Pos)
1219#define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)))
1220#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFu /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
1221
1222/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
1223#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1224typedef union {
1225 struct {
1226 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
1227 uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
1228 uint32_t :4; /*!< bit: 11..14 Reserved */
1229 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
1230 uint32_t :1; /*!< bit: 16 Reserved */
1231 uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
1232 uint32_t :5; /*!< bit: 27..31 Reserved */
1233 } bit; /*!< Structure used for bit access */
1234 uint32_t reg; /*!< Type used for register access */
1235} SERCOM_I2CS_ADDR_Type;
1236#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1237
1238#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
1239#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
1240
1241#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
1242#define SERCOM_I2CS_ADDR_GENCEN (0x1u << SERCOM_I2CS_ADDR_GENCEN_Pos)
1243#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
1244#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFu << SERCOM_I2CS_ADDR_ADDR_Pos)
1245#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))
1246#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
1247#define SERCOM_I2CS_ADDR_TENBITEN (0x1u << SERCOM_I2CS_ADDR_TENBITEN_Pos)
1248#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
1249#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFu << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
1250#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))
1251#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFu /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
1252
1253/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
1254#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1255typedef union {
1256 struct {
1257 uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
1258 uint32_t :8; /*!< bit: 8..15 Reserved */
1259 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
1260 uint32_t :8; /*!< bit: 24..31 Reserved */
1261 } bit; /*!< Structure used for bit access */
1262 uint32_t reg; /*!< Type used for register access */
1263} SERCOM_SPI_ADDR_Type;
1264#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1265
1266#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
1267#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
1268
1269#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
1270#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFu << SERCOM_SPI_ADDR_ADDR_Pos)
1271#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))
1272#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
1273#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFu << SERCOM_SPI_ADDR_ADDRMASK_Pos)
1274#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))
1275#define SERCOM_SPI_ADDR_MASK 0x00FF00FFu /**< \brief (SERCOM_SPI_ADDR) MASK Register */
1276
1277/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
1278#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1279typedef union {
1280 struct {
1281 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
1282 } bit; /*!< Structure used for bit access */
1283 uint8_t reg; /*!< Type used for register access */
1284} SERCOM_I2CM_DATA_Type;
1285#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1286
1287#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
1288#define SERCOM_I2CM_DATA_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
1289
1290#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
1291#define SERCOM_I2CM_DATA_DATA_Msk (0xFFu << SERCOM_I2CM_DATA_DATA_Pos)
1292#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))
1293#define SERCOM_I2CM_DATA_MASK 0xFFu /**< \brief (SERCOM_I2CM_DATA) MASK Register */
1294
1295/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
1296#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1297typedef union {
1298 struct {
1299 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
1300 } bit; /*!< Structure used for bit access */
1301 uint8_t reg; /*!< Type used for register access */
1302} SERCOM_I2CS_DATA_Type;
1303#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1304
1305#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
1306#define SERCOM_I2CS_DATA_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
1307
1308#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
1309#define SERCOM_I2CS_DATA_DATA_Msk (0xFFu << SERCOM_I2CS_DATA_DATA_Pos)
1310#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))
1311#define SERCOM_I2CS_DATA_MASK 0xFFu /**< \brief (SERCOM_I2CS_DATA) MASK Register */
1312
1313/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
1314#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1315typedef union {
1316 struct {
1317 uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
1318 uint32_t :23; /*!< bit: 9..31 Reserved */
1319 } bit; /*!< Structure used for bit access */
1320 uint32_t reg; /*!< Type used for register access */
1321} SERCOM_SPI_DATA_Type;
1322#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1323
1324#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
1325#define SERCOM_SPI_DATA_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
1326
1327#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
1328#define SERCOM_SPI_DATA_DATA_Msk (0x1FFu << SERCOM_SPI_DATA_DATA_Pos)
1329#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))
1330#define SERCOM_SPI_DATA_MASK 0x000001FFu /**< \brief (SERCOM_SPI_DATA) MASK Register */
1331
1332/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
1333#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1334typedef union {
1335 struct {
1336 uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
1337 uint16_t :7; /*!< bit: 9..15 Reserved */
1338 } bit; /*!< Structure used for bit access */
1339 uint16_t reg; /*!< Type used for register access */
1340} SERCOM_USART_DATA_Type;
1341#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1342
1343#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
1344#define SERCOM_USART_DATA_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
1345
1346#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
1347#define SERCOM_USART_DATA_DATA_Msk (0x1FFu << SERCOM_USART_DATA_DATA_Pos)
1348#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))
1349#define SERCOM_USART_DATA_MASK 0x01FFu /**< \brief (SERCOM_USART_DATA) MASK Register */
1350
1351/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
1352#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1353typedef union {
1354 struct {
1355 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
1356 uint8_t :7; /*!< bit: 1.. 7 Reserved */
1357 } bit; /*!< Structure used for bit access */
1358 uint8_t reg; /*!< Type used for register access */
1359} SERCOM_I2CM_DBGCTRL_Type;
1360#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1361
1362#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
1363#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
1364
1365#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
1366#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1u << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
1367#define SERCOM_I2CM_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
1368
1369/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
1370#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1371typedef union {
1372 struct {
1373 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
1374 uint8_t :7; /*!< bit: 1.. 7 Reserved */
1375 } bit; /*!< Structure used for bit access */
1376 uint8_t reg; /*!< Type used for register access */
1377} SERCOM_SPI_DBGCTRL_Type;
1378#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1379
1380#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
1381#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
1382
1383#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
1384#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1u << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
1385#define SERCOM_SPI_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
1386
1387/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
1388#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1389typedef union {
1390 struct {
1391 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
1392 uint8_t :7; /*!< bit: 1.. 7 Reserved */
1393 } bit; /*!< Structure used for bit access */
1394 uint8_t reg; /*!< Type used for register access */
1395} SERCOM_USART_DBGCTRL_Type;
1396#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1397
1398#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
1399#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
1400
1401#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
1402#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1u << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
1403#define SERCOM_USART_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
1404
1405/** \brief SERCOM_I2CM hardware registers */
1406#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1407typedef struct { /* I2C Master Mode */
1408 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
1409 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
1410 RoReg8 Reserved1[0x4];
1411 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
1412 RoReg8 Reserved2[0x4];
1413 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
1414 RoReg8 Reserved3[0x1];
1415 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
1416 RoReg8 Reserved4[0x1];
1417 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
1418 RoReg8 Reserved5[0x1];
1419 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
1420 __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
1421 RoReg8 Reserved6[0x4];
1422 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
1423 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
1424 RoReg8 Reserved7[0x7];
1425 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
1426} SercomI2cm;
1427#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1428
1429/** \brief SERCOM_I2CS hardware registers */
1430#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1431typedef struct { /* I2C Slave Mode */
1432 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
1433 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
1434 RoReg8 Reserved1[0xC];
1435 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
1436 RoReg8 Reserved2[0x1];
1437 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
1438 RoReg8 Reserved3[0x1];
1439 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
1440 RoReg8 Reserved4[0x1];
1441 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
1442 __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
1443 RoReg8 Reserved5[0x4];
1444 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
1445 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
1446} SercomI2cs;
1447#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1448
1449/** \brief SERCOM_SPI hardware registers */
1450#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1451typedef struct { /* SPI Mode */
1452 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
1453 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
1454 RoReg8 Reserved1[0x4];
1455 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
1456 RoReg8 Reserved2[0x7];
1457 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
1458 RoReg8 Reserved3[0x1];
1459 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
1460 RoReg8 Reserved4[0x1];
1461 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
1462 RoReg8 Reserved5[0x1];
1463 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
1464 __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
1465 RoReg8 Reserved6[0x4];
1466 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
1467 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
1468 RoReg8 Reserved7[0x4];
1469 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
1470} SercomSpi;
1471#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1472
1473/** \brief SERCOM_USART hardware registers */
1474#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1475typedef struct { /* USART Mode */
1476 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
1477 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
1478 RoReg8 Reserved1[0x4];
1479 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
1480 __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
1481 RoReg8 Reserved2[0x5];
1482 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
1483 RoReg8 Reserved3[0x1];
1484 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
1485 RoReg8 Reserved4[0x1];
1486 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
1487 RoReg8 Reserved5[0x1];
1488 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
1489 __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
1490 RoReg8 Reserved6[0x8];
1491 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
1492 RoReg8 Reserved7[0x6];
1493 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
1494} SercomUsart;
1495#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1496
1497#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1498typedef union {
1499 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
1500 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
1501 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
1502 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
1503} Sercom;
1504#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1505
1506/*@}*/
1507
1508#endif /* _SAMD21_SERCOM_COMPONENT_ */
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