[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for RTC
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_RTC_COMPONENT_
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| 45 | #define _SAMD21_RTC_COMPONENT_
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| 46 |
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| 47 | /* ========================================================================== */
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| 48 | /** SOFTWARE API DEFINITION FOR RTC */
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| 49 | /* ========================================================================== */
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| 50 | /** \addtogroup SAMD21_RTC Real-Time Counter */
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| 51 | /*@{*/
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| 52 |
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| 53 | #define RTC_U2202
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| 54 | #define REV_RTC 0x101
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| 55 |
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| 56 | /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
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| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 58 | typedef union {
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| 59 | struct {
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| 60 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 61 | uint16_t ENABLE:1; /*!< bit: 1 Enable */
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| 62 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
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| 63 | uint16_t :3; /*!< bit: 4.. 6 Reserved */
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| 64 | uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
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| 65 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
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| 66 | uint16_t :4; /*!< bit: 12..15 Reserved */
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| 67 | } bit; /*!< Structure used for bit access */
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| 68 | uint16_t reg; /*!< Type used for register access */
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| 69 | } RTC_MODE0_CTRL_Type;
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| 70 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 71 |
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| 72 | #define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
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| 73 | #define RTC_MODE0_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
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| 74 |
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| 75 | #define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */
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| 76 | #define RTC_MODE0_CTRL_SWRST (0x1u << RTC_MODE0_CTRL_SWRST_Pos)
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| 77 | #define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */
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| 78 | #define RTC_MODE0_CTRL_ENABLE (0x1u << RTC_MODE0_CTRL_ENABLE_Pos)
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| 79 | #define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
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| 80 | #define RTC_MODE0_CTRL_MODE_Msk (0x3u << RTC_MODE0_CTRL_MODE_Pos)
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| 81 | #define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)))
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| 82 | #define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0u /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
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| 83 | #define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1u /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
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| 84 | #define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2u /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
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| 85 | #define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
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| 86 | #define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
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| 87 | #define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
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| 88 | #define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */
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| 89 | #define RTC_MODE0_CTRL_MATCHCLR (0x1u << RTC_MODE0_CTRL_MATCHCLR_Pos)
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| 90 | #define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
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| 91 | #define RTC_MODE0_CTRL_PRESCALER_Msk (0xFu << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 92 | #define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)))
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| 93 | #define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
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| 94 | #define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
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| 95 | #define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
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| 96 | #define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
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| 97 | #define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
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| 98 | #define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
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| 99 | #define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
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| 100 | #define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
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| 101 | #define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
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| 102 | #define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
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| 103 | #define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAu /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
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| 104 | #define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 105 | #define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 106 | #define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 107 | #define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 108 | #define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 109 | #define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 110 | #define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 111 | #define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 112 | #define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 113 | #define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 114 | #define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
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| 115 | #define RTC_MODE0_CTRL_MASK 0x0F8Fu /**< \brief (RTC_MODE0_CTRL) MASK Register */
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| 116 |
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| 117 | /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
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| 118 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 119 | typedef union {
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| 120 | struct {
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| 121 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 122 | uint16_t ENABLE:1; /*!< bit: 1 Enable */
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| 123 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
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| 124 | uint16_t :4; /*!< bit: 4.. 7 Reserved */
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| 125 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
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| 126 | uint16_t :4; /*!< bit: 12..15 Reserved */
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| 127 | } bit; /*!< Structure used for bit access */
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| 128 | uint16_t reg; /*!< Type used for register access */
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| 129 | } RTC_MODE1_CTRL_Type;
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| 130 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 131 |
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| 132 | #define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
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| 133 | #define RTC_MODE1_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
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| 134 |
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| 135 | #define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */
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| 136 | #define RTC_MODE1_CTRL_SWRST (0x1u << RTC_MODE1_CTRL_SWRST_Pos)
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| 137 | #define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */
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| 138 | #define RTC_MODE1_CTRL_ENABLE (0x1u << RTC_MODE1_CTRL_ENABLE_Pos)
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| 139 | #define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
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| 140 | #define RTC_MODE1_CTRL_MODE_Msk (0x3u << RTC_MODE1_CTRL_MODE_Pos)
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| 141 | #define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)))
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| 142 | #define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0u /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
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| 143 | #define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1u /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
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| 144 | #define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2u /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
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| 145 | #define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
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| 146 | #define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
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| 147 | #define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
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| 148 | #define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
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| 149 | #define RTC_MODE1_CTRL_PRESCALER_Msk (0xFu << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 150 | #define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)))
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| 151 | #define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
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| 152 | #define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
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| 153 | #define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
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| 154 | #define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
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| 155 | #define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
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| 156 | #define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
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| 157 | #define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
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| 158 | #define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
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| 159 | #define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
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| 160 | #define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
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| 161 | #define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAu /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
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| 162 | #define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 163 | #define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 164 | #define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 165 | #define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 166 | #define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 167 | #define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 168 | #define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 169 | #define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 170 | #define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 171 | #define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 172 | #define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
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| 173 | #define RTC_MODE1_CTRL_MASK 0x0F0Fu /**< \brief (RTC_MODE1_CTRL) MASK Register */
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| 174 |
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| 175 | /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
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| 176 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 177 | typedef union {
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| 178 | struct {
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| 179 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 180 | uint16_t ENABLE:1; /*!< bit: 1 Enable */
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| 181 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
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| 182 | uint16_t :2; /*!< bit: 4.. 5 Reserved */
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| 183 | uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
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| 184 | uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
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| 185 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
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| 186 | uint16_t :4; /*!< bit: 12..15 Reserved */
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| 187 | } bit; /*!< Structure used for bit access */
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| 188 | uint16_t reg; /*!< Type used for register access */
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| 189 | } RTC_MODE2_CTRL_Type;
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| 190 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 191 |
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| 192 | #define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
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| 193 | #define RTC_MODE2_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
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| 194 |
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| 195 | #define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */
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| 196 | #define RTC_MODE2_CTRL_SWRST (0x1u << RTC_MODE2_CTRL_SWRST_Pos)
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| 197 | #define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */
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| 198 | #define RTC_MODE2_CTRL_ENABLE (0x1u << RTC_MODE2_CTRL_ENABLE_Pos)
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| 199 | #define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
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| 200 | #define RTC_MODE2_CTRL_MODE_Msk (0x3u << RTC_MODE2_CTRL_MODE_Pos)
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| 201 | #define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)))
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| 202 | #define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0u /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
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| 203 | #define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1u /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
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| 204 | #define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2u /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
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| 205 | #define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
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| 206 | #define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
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| 207 | #define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
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| 208 | #define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */
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| 209 | #define RTC_MODE2_CTRL_CLKREP (0x1u << RTC_MODE2_CTRL_CLKREP_Pos)
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| 210 | #define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */
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| 211 | #define RTC_MODE2_CTRL_MATCHCLR (0x1u << RTC_MODE2_CTRL_MATCHCLR_Pos)
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| 212 | #define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
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| 213 | #define RTC_MODE2_CTRL_PRESCALER_Msk (0xFu << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 214 | #define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)))
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| 215 | #define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
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| 216 | #define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
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| 217 | #define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
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| 218 | #define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
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| 219 | #define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
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| 220 | #define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
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| 221 | #define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
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| 222 | #define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
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| 223 | #define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
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| 224 | #define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
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| 225 | #define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAu /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
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| 226 | #define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 227 | #define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 228 | #define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 229 | #define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 230 | #define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 231 | #define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 232 | #define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 233 | #define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 234 | #define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 235 | #define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 236 | #define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
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| 237 | #define RTC_MODE2_CTRL_MASK 0x0FCFu /**< \brief (RTC_MODE2_CTRL) MASK Register */
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| 238 |
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| 239 | /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
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| 240 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 241 | typedef union {
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| 242 | struct {
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| 243 | uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
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| 244 | uint16_t :8; /*!< bit: 6..13 Reserved */
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| 245 | uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
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| 246 | uint16_t RREQ:1; /*!< bit: 15 Read Request */
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| 247 | } bit; /*!< Structure used for bit access */
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| 248 | uint16_t reg; /*!< Type used for register access */
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| 249 | } RTC_READREQ_Type;
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| 250 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 251 |
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| 252 | #define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */
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| 253 | #define RTC_READREQ_RESETVALUE 0x0010 /**< \brief (RTC_READREQ reset_value) Read Request */
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| 254 |
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| 255 | #define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
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| 256 | #define RTC_READREQ_ADDR_Msk (0x3Fu << RTC_READREQ_ADDR_Pos)
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| 257 | #define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)))
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| 258 | #define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
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| 259 | #define RTC_READREQ_RCONT (0x1u << RTC_READREQ_RCONT_Pos)
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| 260 | #define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
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| 261 | #define RTC_READREQ_RREQ (0x1u << RTC_READREQ_RREQ_Pos)
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| 262 | #define RTC_READREQ_MASK 0xC03Fu /**< \brief (RTC_READREQ) MASK Register */
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| 263 |
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| 264 | /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
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| 265 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 266 | typedef union {
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| 267 | struct {
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| 268 | uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
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| 269 | uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
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| 270 | uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
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| 271 | uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
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| 272 | uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
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| 273 | uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
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| 274 | uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
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| 275 | uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
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| 276 | uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
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| 277 | uint16_t :6; /*!< bit: 9..14 Reserved */
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| 278 | uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
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| 279 | } bit; /*!< Structure used for bit access */
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| 280 | struct {
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| 281 | uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
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| 282 | uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
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| 283 | uint16_t :7; /*!< bit: 9..15 Reserved */
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| 284 | } vec; /*!< Structure used for vec access */
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| 285 | uint16_t reg; /*!< Type used for register access */
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| 286 | } RTC_MODE0_EVCTRL_Type;
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| 287 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 288 |
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| 289 | #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
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| 290 | #define RTC_MODE0_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
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| 291 |
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| 292 | #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
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| 293 | #define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
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| 294 | #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
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| 295 | #define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
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| 296 | #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
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| 297 | #define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
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| 298 | #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
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| 299 | #define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
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| 300 | #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
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| 301 | #define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
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| 302 | #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
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| 303 | #define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
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| 304 | #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
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| 305 | #define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
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| 306 | #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
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| 307 | #define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
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| 308 | #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
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| 309 | #define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE0_EVCTRL_PEREO_Pos)
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| 310 | #define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)))
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| 311 | #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
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| 312 | #define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
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| 313 | #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
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| 314 | #define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1u << RTC_MODE0_EVCTRL_CMPEO_Pos)
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| 315 | #define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)))
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| 316 | #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
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| 317 | #define RTC_MODE0_EVCTRL_OVFEO (0x1u << RTC_MODE0_EVCTRL_OVFEO_Pos)
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| 318 | #define RTC_MODE0_EVCTRL_MASK 0x81FFu /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
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| 319 |
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| 320 | /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
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| 321 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 322 | typedef union {
|
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| 323 | struct {
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| 324 | uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
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| 325 | uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
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| 326 | uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
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| 327 | uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
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| 328 | uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
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| 329 | uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
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| 330 | uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
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| 331 | uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
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| 332 | uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
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| 333 | uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
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| 334 | uint16_t :5; /*!< bit: 10..14 Reserved */
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| 335 | uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
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| 336 | } bit; /*!< Structure used for bit access */
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| 337 | struct {
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| 338 | uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
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| 339 | uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
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| 340 | uint16_t :6; /*!< bit: 10..15 Reserved */
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| 341 | } vec; /*!< Structure used for vec access */
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| 342 | uint16_t reg; /*!< Type used for register access */
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| 343 | } RTC_MODE1_EVCTRL_Type;
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| 344 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 345 |
|
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| 346 | #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
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| 347 | #define RTC_MODE1_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
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| 348 |
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| 349 | #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
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| 350 | #define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
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| 351 | #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
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| 352 | #define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
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| 353 | #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
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| 354 | #define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
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| 355 | #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
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| 356 | #define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
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| 357 | #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
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| 358 | #define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
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| 359 | #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
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| 360 | #define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
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| 361 | #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
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| 362 | #define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
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| 363 | #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
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| 364 | #define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
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| 365 | #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
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| 366 | #define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE1_EVCTRL_PEREO_Pos)
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| 367 | #define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)))
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| 368 | #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
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| 369 | #define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
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| 370 | #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
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| 371 | #define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
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| 372 | #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
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| 373 | #define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3u << RTC_MODE1_EVCTRL_CMPEO_Pos)
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| 374 | #define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)))
|
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| 375 | #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
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| 376 | #define RTC_MODE1_EVCTRL_OVFEO (0x1u << RTC_MODE1_EVCTRL_OVFEO_Pos)
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| 377 | #define RTC_MODE1_EVCTRL_MASK 0x83FFu /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
|
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| 378 |
|
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| 379 | /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
|
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| 380 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 381 | typedef union {
|
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| 382 | struct {
|
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| 383 | uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
|
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| 384 | uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
|
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| 385 | uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
|
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| 386 | uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
|
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| 387 | uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
|
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| 388 | uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
|
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| 389 | uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
|
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| 390 | uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
|
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| 391 | uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
|
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| 392 | uint16_t :6; /*!< bit: 9..14 Reserved */
|
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| 393 | uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
|
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| 394 | } bit; /*!< Structure used for bit access */
|
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| 395 | struct {
|
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| 396 | uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
|
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| 397 | uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
|
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| 398 | uint16_t :7; /*!< bit: 9..15 Reserved */
|
---|
| 399 | } vec; /*!< Structure used for vec access */
|
---|
| 400 | uint16_t reg; /*!< Type used for register access */
|
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| 401 | } RTC_MODE2_EVCTRL_Type;
|
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| 402 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 403 |
|
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| 404 | #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
|
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| 405 | #define RTC_MODE2_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
|
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| 406 |
|
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| 407 | #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
|
---|
| 408 | #define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
|
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| 409 | #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
|
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| 410 | #define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
|
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| 411 | #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
|
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| 412 | #define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
|
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| 413 | #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
|
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| 414 | #define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
|
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| 415 | #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
|
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| 416 | #define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
|
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| 417 | #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
|
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| 418 | #define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
|
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| 419 | #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
|
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| 420 | #define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
|
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| 421 | #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
|
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| 422 | #define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
|
---|
| 423 | #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
|
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| 424 | #define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE2_EVCTRL_PEREO_Pos)
|
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| 425 | #define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)))
|
---|
| 426 | #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
|
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| 427 | #define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
|
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| 428 | #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
|
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| 429 | #define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1u << RTC_MODE2_EVCTRL_ALARMEO_Pos)
|
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| 430 | #define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)))
|
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| 431 | #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
|
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| 432 | #define RTC_MODE2_EVCTRL_OVFEO (0x1u << RTC_MODE2_EVCTRL_OVFEO_Pos)
|
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| 433 | #define RTC_MODE2_EVCTRL_MASK 0x81FFu /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
|
---|
| 434 |
|
---|
| 435 | /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
|
---|
| 436 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 437 | typedef union {
|
---|
| 438 | struct {
|
---|
| 439 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
|
---|
| 440 | uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
---|
| 441 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
|
---|
| 442 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
|
---|
| 443 | } bit; /*!< Structure used for bit access */
|
---|
| 444 | struct {
|
---|
| 445 | uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
|
---|
| 446 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
| 447 | } vec; /*!< Structure used for vec access */
|
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| 448 | uint8_t reg; /*!< Type used for register access */
|
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| 449 | } RTC_MODE0_INTENCLR_Type;
|
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| 450 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 451 |
|
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| 452 | #define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
|
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| 453 | #define RTC_MODE0_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
|
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| 454 |
|
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| 455 | #define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
|
---|
| 456 | #define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
|
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| 457 | #define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
|
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| 458 | #define RTC_MODE0_INTENCLR_CMP_Msk (0x1u << RTC_MODE0_INTENCLR_CMP_Pos)
|
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| 459 | #define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)))
|
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| 460 | #define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
|
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| 461 | #define RTC_MODE0_INTENCLR_SYNCRDY (0x1u << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
|
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| 462 | #define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
|
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| 463 | #define RTC_MODE0_INTENCLR_OVF (0x1u << RTC_MODE0_INTENCLR_OVF_Pos)
|
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| 464 | #define RTC_MODE0_INTENCLR_MASK 0xC1u /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
|
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| 465 |
|
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| 466 | /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
|
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| 467 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 468 | typedef union {
|
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| 469 | struct {
|
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| 470 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
|
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| 471 | uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
|
---|
| 472 | uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
---|
| 473 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
|
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| 474 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
|
---|
| 475 | } bit; /*!< Structure used for bit access */
|
---|
| 476 | struct {
|
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| 477 | uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
|
---|
| 478 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
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| 479 | } vec; /*!< Structure used for vec access */
|
---|
| 480 | uint8_t reg; /*!< Type used for register access */
|
---|
| 481 | } RTC_MODE1_INTENCLR_Type;
|
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| 482 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 483 |
|
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| 484 | #define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
|
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| 485 | #define RTC_MODE1_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
|
---|
| 486 |
|
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| 487 | #define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
|
---|
| 488 | #define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
|
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| 489 | #define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
|
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| 490 | #define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
|
---|
| 491 | #define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
|
---|
| 492 | #define RTC_MODE1_INTENCLR_CMP_Msk (0x3u << RTC_MODE1_INTENCLR_CMP_Pos)
|
---|
| 493 | #define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)))
|
---|
| 494 | #define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
|
---|
| 495 | #define RTC_MODE1_INTENCLR_SYNCRDY (0x1u << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
|
---|
| 496 | #define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
|
---|
| 497 | #define RTC_MODE1_INTENCLR_OVF (0x1u << RTC_MODE1_INTENCLR_OVF_Pos)
|
---|
| 498 | #define RTC_MODE1_INTENCLR_MASK 0xC3u /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
|
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| 499 |
|
---|
| 500 | /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
|
---|
| 501 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 502 | typedef union {
|
---|
| 503 | struct {
|
---|
| 504 | uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
|
---|
| 505 | uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
---|
| 506 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
|
---|
| 507 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
|
---|
| 508 | } bit; /*!< Structure used for bit access */
|
---|
| 509 | struct {
|
---|
| 510 | uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
|
---|
| 511 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
| 512 | } vec; /*!< Structure used for vec access */
|
---|
| 513 | uint8_t reg; /*!< Type used for register access */
|
---|
| 514 | } RTC_MODE2_INTENCLR_Type;
|
---|
| 515 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 516 |
|
---|
| 517 | #define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
|
---|
| 518 | #define RTC_MODE2_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
|
---|
| 519 |
|
---|
| 520 | #define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
|
---|
| 521 | #define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
|
---|
| 522 | #define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
|
---|
| 523 | #define RTC_MODE2_INTENCLR_ALARM_Msk (0x1u << RTC_MODE2_INTENCLR_ALARM_Pos)
|
---|
| 524 | #define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)))
|
---|
| 525 | #define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
|
---|
| 526 | #define RTC_MODE2_INTENCLR_SYNCRDY (0x1u << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
|
---|
| 527 | #define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
|
---|
| 528 | #define RTC_MODE2_INTENCLR_OVF (0x1u << RTC_MODE2_INTENCLR_OVF_Pos)
|
---|
| 529 | #define RTC_MODE2_INTENCLR_MASK 0xC1u /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
|
---|
| 530 |
|
---|
| 531 | /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
|
---|
| 532 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 533 | typedef union {
|
---|
| 534 | struct {
|
---|
| 535 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
|
---|
| 536 | uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
---|
| 537 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
|
---|
| 538 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
|
---|
| 539 | } bit; /*!< Structure used for bit access */
|
---|
| 540 | struct {
|
---|
| 541 | uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
|
---|
| 542 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
| 543 | } vec; /*!< Structure used for vec access */
|
---|
| 544 | uint8_t reg; /*!< Type used for register access */
|
---|
| 545 | } RTC_MODE0_INTENSET_Type;
|
---|
| 546 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 547 |
|
---|
| 548 | #define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
|
---|
| 549 | #define RTC_MODE0_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
|
---|
| 550 |
|
---|
| 551 | #define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
|
---|
| 552 | #define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
|
---|
| 553 | #define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
|
---|
| 554 | #define RTC_MODE0_INTENSET_CMP_Msk (0x1u << RTC_MODE0_INTENSET_CMP_Pos)
|
---|
| 555 | #define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)))
|
---|
| 556 | #define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
|
---|
| 557 | #define RTC_MODE0_INTENSET_SYNCRDY (0x1u << RTC_MODE0_INTENSET_SYNCRDY_Pos)
|
---|
| 558 | #define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
|
---|
| 559 | #define RTC_MODE0_INTENSET_OVF (0x1u << RTC_MODE0_INTENSET_OVF_Pos)
|
---|
| 560 | #define RTC_MODE0_INTENSET_MASK 0xC1u /**< \brief (RTC_MODE0_INTENSET) MASK Register */
|
---|
| 561 |
|
---|
| 562 | /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
|
---|
| 563 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 564 | typedef union {
|
---|
| 565 | struct {
|
---|
| 566 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
|
---|
| 567 | uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
|
---|
| 568 | uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
---|
| 569 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
|
---|
| 570 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
|
---|
| 571 | } bit; /*!< Structure used for bit access */
|
---|
| 572 | struct {
|
---|
| 573 | uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
|
---|
| 574 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
| 575 | } vec; /*!< Structure used for vec access */
|
---|
| 576 | uint8_t reg; /*!< Type used for register access */
|
---|
| 577 | } RTC_MODE1_INTENSET_Type;
|
---|
| 578 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 579 |
|
---|
| 580 | #define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
|
---|
| 581 | #define RTC_MODE1_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
|
---|
| 582 |
|
---|
| 583 | #define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
|
---|
| 584 | #define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos)
|
---|
| 585 | #define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
|
---|
| 586 | #define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
|
---|
| 587 | #define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
|
---|
| 588 | #define RTC_MODE1_INTENSET_CMP_Msk (0x3u << RTC_MODE1_INTENSET_CMP_Pos)
|
---|
| 589 | #define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)))
|
---|
| 590 | #define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
|
---|
| 591 | #define RTC_MODE1_INTENSET_SYNCRDY (0x1u << RTC_MODE1_INTENSET_SYNCRDY_Pos)
|
---|
| 592 | #define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
|
---|
| 593 | #define RTC_MODE1_INTENSET_OVF (0x1u << RTC_MODE1_INTENSET_OVF_Pos)
|
---|
| 594 | #define RTC_MODE1_INTENSET_MASK 0xC3u /**< \brief (RTC_MODE1_INTENSET) MASK Register */
|
---|
| 595 |
|
---|
| 596 | /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
|
---|
| 597 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 598 | typedef union {
|
---|
| 599 | struct {
|
---|
| 600 | uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
|
---|
| 601 | uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
---|
| 602 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
|
---|
| 603 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
|
---|
| 604 | } bit; /*!< Structure used for bit access */
|
---|
| 605 | struct {
|
---|
| 606 | uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
|
---|
| 607 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
| 608 | } vec; /*!< Structure used for vec access */
|
---|
| 609 | uint8_t reg; /*!< Type used for register access */
|
---|
| 610 | } RTC_MODE2_INTENSET_Type;
|
---|
| 611 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 612 |
|
---|
| 613 | #define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
|
---|
| 614 | #define RTC_MODE2_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
|
---|
| 615 |
|
---|
| 616 | #define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
|
---|
| 617 | #define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
|
---|
| 618 | #define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
|
---|
| 619 | #define RTC_MODE2_INTENSET_ALARM_Msk (0x1u << RTC_MODE2_INTENSET_ALARM_Pos)
|
---|
| 620 | #define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)))
|
---|
| 621 | #define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
|
---|
| 622 | #define RTC_MODE2_INTENSET_SYNCRDY (0x1u << RTC_MODE2_INTENSET_SYNCRDY_Pos)
|
---|
| 623 | #define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
|
---|
| 624 | #define RTC_MODE2_INTENSET_OVF (0x1u << RTC_MODE2_INTENSET_OVF_Pos)
|
---|
| 625 | #define RTC_MODE2_INTENSET_MASK 0xC1u /**< \brief (RTC_MODE2_INTENSET) MASK Register */
|
---|
| 626 |
|
---|
| 627 | /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
|
---|
| 628 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 629 | typedef union {
|
---|
| 630 | struct {
|
---|
| 631 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
---|
| 632 | uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
---|
| 633 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
---|
| 634 | uint8_t OVF:1; /*!< bit: 7 Overflow */
|
---|
| 635 | } bit; /*!< Structure used for bit access */
|
---|
| 636 | struct {
|
---|
| 637 | uint8_t CMP:1; /*!< bit: 0 Compare x */
|
---|
| 638 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
| 639 | } vec; /*!< Structure used for vec access */
|
---|
| 640 | uint8_t reg; /*!< Type used for register access */
|
---|
| 641 | } RTC_MODE0_INTFLAG_Type;
|
---|
| 642 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 643 |
|
---|
| 644 | #define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
|
---|
| 645 | #define RTC_MODE0_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
|
---|
| 646 |
|
---|
| 647 | #define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
|
---|
| 648 | #define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
|
---|
| 649 | #define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
|
---|
| 650 | #define RTC_MODE0_INTFLAG_CMP_Msk (0x1u << RTC_MODE0_INTFLAG_CMP_Pos)
|
---|
| 651 | #define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)))
|
---|
| 652 | #define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
|
---|
| 653 | #define RTC_MODE0_INTFLAG_SYNCRDY (0x1u << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
|
---|
| 654 | #define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
|
---|
| 655 | #define RTC_MODE0_INTFLAG_OVF (0x1u << RTC_MODE0_INTFLAG_OVF_Pos)
|
---|
| 656 | #define RTC_MODE0_INTFLAG_MASK 0xC1u /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
|
---|
| 657 |
|
---|
| 658 | /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
|
---|
| 659 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 660 | typedef union {
|
---|
| 661 | struct {
|
---|
| 662 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
---|
| 663 | uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
|
---|
| 664 | uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
---|
| 665 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
---|
| 666 | uint8_t OVF:1; /*!< bit: 7 Overflow */
|
---|
| 667 | } bit; /*!< Structure used for bit access */
|
---|
| 668 | struct {
|
---|
| 669 | uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
|
---|
| 670 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
| 671 | } vec; /*!< Structure used for vec access */
|
---|
| 672 | uint8_t reg; /*!< Type used for register access */
|
---|
| 673 | } RTC_MODE1_INTFLAG_Type;
|
---|
| 674 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 675 |
|
---|
| 676 | #define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
|
---|
| 677 | #define RTC_MODE1_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
|
---|
| 678 |
|
---|
| 679 | #define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
|
---|
| 680 | #define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
|
---|
| 681 | #define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
|
---|
| 682 | #define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
|
---|
| 683 | #define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
|
---|
| 684 | #define RTC_MODE1_INTFLAG_CMP_Msk (0x3u << RTC_MODE1_INTFLAG_CMP_Pos)
|
---|
| 685 | #define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)))
|
---|
| 686 | #define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
|
---|
| 687 | #define RTC_MODE1_INTFLAG_SYNCRDY (0x1u << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
|
---|
| 688 | #define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
|
---|
| 689 | #define RTC_MODE1_INTFLAG_OVF (0x1u << RTC_MODE1_INTFLAG_OVF_Pos)
|
---|
| 690 | #define RTC_MODE1_INTFLAG_MASK 0xC3u /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
|
---|
| 691 |
|
---|
| 692 | /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
|
---|
| 693 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 694 | typedef union {
|
---|
| 695 | struct {
|
---|
| 696 | uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
|
---|
| 697 | uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
---|
| 698 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
---|
| 699 | uint8_t OVF:1; /*!< bit: 7 Overflow */
|
---|
| 700 | } bit; /*!< Structure used for bit access */
|
---|
| 701 | struct {
|
---|
| 702 | uint8_t ALARM:1; /*!< bit: 0 Alarm x */
|
---|
| 703 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
| 704 | } vec; /*!< Structure used for vec access */
|
---|
| 705 | uint8_t reg; /*!< Type used for register access */
|
---|
| 706 | } RTC_MODE2_INTFLAG_Type;
|
---|
| 707 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 708 |
|
---|
| 709 | #define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
|
---|
| 710 | #define RTC_MODE2_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
|
---|
| 711 |
|
---|
| 712 | #define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
|
---|
| 713 | #define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
|
---|
| 714 | #define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
|
---|
| 715 | #define RTC_MODE2_INTFLAG_ALARM_Msk (0x1u << RTC_MODE2_INTFLAG_ALARM_Pos)
|
---|
| 716 | #define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)))
|
---|
| 717 | #define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
|
---|
| 718 | #define RTC_MODE2_INTFLAG_SYNCRDY (0x1u << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
|
---|
| 719 | #define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
|
---|
| 720 | #define RTC_MODE2_INTFLAG_OVF (0x1u << RTC_MODE2_INTFLAG_OVF_Pos)
|
---|
| 721 | #define RTC_MODE2_INTFLAG_MASK 0xC1u /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
|
---|
| 722 |
|
---|
| 723 | /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
|
---|
| 724 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 725 | typedef union {
|
---|
| 726 | struct {
|
---|
| 727 | uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
---|
| 728 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
|
---|
| 729 | } bit; /*!< Structure used for bit access */
|
---|
| 730 | uint8_t reg; /*!< Type used for register access */
|
---|
| 731 | } RTC_STATUS_Type;
|
---|
| 732 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 733 |
|
---|
| 734 | #define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */
|
---|
| 735 | #define RTC_STATUS_RESETVALUE 0x00 /**< \brief (RTC_STATUS reset_value) Status */
|
---|
| 736 |
|
---|
| 737 | #define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */
|
---|
| 738 | #define RTC_STATUS_SYNCBUSY (0x1u << RTC_STATUS_SYNCBUSY_Pos)
|
---|
| 739 | #define RTC_STATUS_MASK 0x80u /**< \brief (RTC_STATUS) MASK Register */
|
---|
| 740 |
|
---|
| 741 | /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
|
---|
| 742 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 743 | typedef union {
|
---|
| 744 | struct {
|
---|
| 745 | uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
|
---|
| 746 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
| 747 | } bit; /*!< Structure used for bit access */
|
---|
| 748 | uint8_t reg; /*!< Type used for register access */
|
---|
| 749 | } RTC_DBGCTRL_Type;
|
---|
| 750 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 751 |
|
---|
| 752 | #define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */
|
---|
| 753 | #define RTC_DBGCTRL_RESETVALUE 0x00 /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
|
---|
| 754 |
|
---|
| 755 | #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
|
---|
| 756 | #define RTC_DBGCTRL_DBGRUN (0x1u << RTC_DBGCTRL_DBGRUN_Pos)
|
---|
| 757 | #define RTC_DBGCTRL_MASK 0x01u /**< \brief (RTC_DBGCTRL) MASK Register */
|
---|
| 758 |
|
---|
| 759 | /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
|
---|
| 760 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 761 | typedef union {
|
---|
| 762 | struct {
|
---|
| 763 | uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
|
---|
| 764 | uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
|
---|
| 765 | } bit; /*!< Structure used for bit access */
|
---|
| 766 | uint8_t reg; /*!< Type used for register access */
|
---|
| 767 | } RTC_FREQCORR_Type;
|
---|
| 768 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 769 |
|
---|
| 770 | #define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */
|
---|
| 771 | #define RTC_FREQCORR_RESETVALUE 0x00 /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
|
---|
| 772 |
|
---|
| 773 | #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
|
---|
| 774 | #define RTC_FREQCORR_VALUE_Msk (0x7Fu << RTC_FREQCORR_VALUE_Pos)
|
---|
| 775 | #define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)))
|
---|
| 776 | #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
|
---|
| 777 | #define RTC_FREQCORR_SIGN (0x1u << RTC_FREQCORR_SIGN_Pos)
|
---|
| 778 | #define RTC_FREQCORR_MASK 0xFFu /**< \brief (RTC_FREQCORR) MASK Register */
|
---|
| 779 |
|
---|
| 780 | /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
|
---|
| 781 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 782 | typedef union {
|
---|
| 783 | struct {
|
---|
| 784 | uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
|
---|
| 785 | } bit; /*!< Structure used for bit access */
|
---|
| 786 | uint32_t reg; /*!< Type used for register access */
|
---|
| 787 | } RTC_MODE0_COUNT_Type;
|
---|
| 788 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 789 |
|
---|
| 790 | #define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
|
---|
| 791 | #define RTC_MODE0_COUNT_RESETVALUE 0x00000000 /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
|
---|
| 792 |
|
---|
| 793 | #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
|
---|
| 794 | #define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFu << RTC_MODE0_COUNT_COUNT_Pos)
|
---|
| 795 | #define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)))
|
---|
| 796 | #define RTC_MODE0_COUNT_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE0_COUNT) MASK Register */
|
---|
| 797 |
|
---|
| 798 | /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
|
---|
| 799 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 800 | typedef union {
|
---|
| 801 | struct {
|
---|
| 802 | uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
|
---|
| 803 | } bit; /*!< Structure used for bit access */
|
---|
| 804 | uint16_t reg; /*!< Type used for register access */
|
---|
| 805 | } RTC_MODE1_COUNT_Type;
|
---|
| 806 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 807 |
|
---|
| 808 | #define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
|
---|
| 809 | #define RTC_MODE1_COUNT_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
|
---|
| 810 |
|
---|
| 811 | #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
|
---|
| 812 | #define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFu << RTC_MODE1_COUNT_COUNT_Pos)
|
---|
| 813 | #define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)))
|
---|
| 814 | #define RTC_MODE1_COUNT_MASK 0xFFFFu /**< \brief (RTC_MODE1_COUNT) MASK Register */
|
---|
| 815 |
|
---|
| 816 | /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
|
---|
| 817 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 818 | typedef union {
|
---|
| 819 | struct {
|
---|
| 820 | uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
|
---|
| 821 | uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
|
---|
| 822 | uint32_t HOUR:5; /*!< bit: 12..16 Hour */
|
---|
| 823 | uint32_t DAY:5; /*!< bit: 17..21 Day */
|
---|
| 824 | uint32_t MONTH:4; /*!< bit: 22..25 Month */
|
---|
| 825 | uint32_t YEAR:6; /*!< bit: 26..31 Year */
|
---|
| 826 | } bit; /*!< Structure used for bit access */
|
---|
| 827 | uint32_t reg; /*!< Type used for register access */
|
---|
| 828 | } RTC_MODE2_CLOCK_Type;
|
---|
| 829 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 830 |
|
---|
| 831 | #define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
|
---|
| 832 | #define RTC_MODE2_CLOCK_RESETVALUE 0x00000000 /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
|
---|
| 833 |
|
---|
| 834 | #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
|
---|
| 835 | #define RTC_MODE2_CLOCK_SECOND_Msk (0x3Fu << RTC_MODE2_CLOCK_SECOND_Pos)
|
---|
| 836 | #define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)))
|
---|
| 837 | #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
|
---|
| 838 | #define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Fu << RTC_MODE2_CLOCK_MINUTE_Pos)
|
---|
| 839 | #define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)))
|
---|
| 840 | #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
|
---|
| 841 | #define RTC_MODE2_CLOCK_HOUR_Msk (0x1Fu << RTC_MODE2_CLOCK_HOUR_Pos)
|
---|
| 842 | #define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)))
|
---|
| 843 | #define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10u /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
|
---|
| 844 | #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
|
---|
| 845 | #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
|
---|
| 846 | #define RTC_MODE2_CLOCK_DAY_Msk (0x1Fu << RTC_MODE2_CLOCK_DAY_Pos)
|
---|
| 847 | #define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)))
|
---|
| 848 | #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
|
---|
| 849 | #define RTC_MODE2_CLOCK_MONTH_Msk (0xFu << RTC_MODE2_CLOCK_MONTH_Pos)
|
---|
| 850 | #define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)))
|
---|
| 851 | #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
|
---|
| 852 | #define RTC_MODE2_CLOCK_YEAR_Msk (0x3Fu << RTC_MODE2_CLOCK_YEAR_Pos)
|
---|
| 853 | #define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)))
|
---|
| 854 | #define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE2_CLOCK) MASK Register */
|
---|
| 855 |
|
---|
| 856 | /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
|
---|
| 857 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 858 | typedef union {
|
---|
| 859 | struct {
|
---|
| 860 | uint16_t PER:16; /*!< bit: 0..15 Counter Period */
|
---|
| 861 | } bit; /*!< Structure used for bit access */
|
---|
| 862 | uint16_t reg; /*!< Type used for register access */
|
---|
| 863 | } RTC_MODE1_PER_Type;
|
---|
| 864 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 865 |
|
---|
| 866 | #define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
|
---|
| 867 | #define RTC_MODE1_PER_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
|
---|
| 868 |
|
---|
| 869 | #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
|
---|
| 870 | #define RTC_MODE1_PER_PER_Msk (0xFFFFu << RTC_MODE1_PER_PER_Pos)
|
---|
| 871 | #define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)))
|
---|
| 872 | #define RTC_MODE1_PER_MASK 0xFFFFu /**< \brief (RTC_MODE1_PER) MASK Register */
|
---|
| 873 |
|
---|
| 874 | /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
|
---|
| 875 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 876 | typedef union {
|
---|
| 877 | struct {
|
---|
| 878 | uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
|
---|
| 879 | } bit; /*!< Structure used for bit access */
|
---|
| 880 | uint32_t reg; /*!< Type used for register access */
|
---|
| 881 | } RTC_MODE0_COMP_Type;
|
---|
| 882 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 883 |
|
---|
| 884 | #define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
|
---|
| 885 | #define RTC_MODE0_COMP_RESETVALUE 0x00000000 /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
|
---|
| 886 |
|
---|
| 887 | #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
|
---|
| 888 | #define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFu << RTC_MODE0_COMP_COMP_Pos)
|
---|
| 889 | #define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)))
|
---|
| 890 | #define RTC_MODE0_COMP_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE0_COMP) MASK Register */
|
---|
| 891 |
|
---|
| 892 | /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
|
---|
| 893 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 894 | typedef union {
|
---|
| 895 | struct {
|
---|
| 896 | uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
|
---|
| 897 | } bit; /*!< Structure used for bit access */
|
---|
| 898 | uint16_t reg; /*!< Type used for register access */
|
---|
| 899 | } RTC_MODE1_COMP_Type;
|
---|
| 900 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 901 |
|
---|
| 902 | #define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
|
---|
| 903 | #define RTC_MODE1_COMP_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
|
---|
| 904 |
|
---|
| 905 | #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
|
---|
| 906 | #define RTC_MODE1_COMP_COMP_Msk (0xFFFFu << RTC_MODE1_COMP_COMP_Pos)
|
---|
| 907 | #define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)))
|
---|
| 908 | #define RTC_MODE1_COMP_MASK 0xFFFFu /**< \brief (RTC_MODE1_COMP) MASK Register */
|
---|
| 909 |
|
---|
| 910 | /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
|
---|
| 911 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 912 | typedef union {
|
---|
| 913 | struct {
|
---|
| 914 | uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
|
---|
| 915 | uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
|
---|
| 916 | uint32_t HOUR:5; /*!< bit: 12..16 Hour */
|
---|
| 917 | uint32_t DAY:5; /*!< bit: 17..21 Day */
|
---|
| 918 | uint32_t MONTH:4; /*!< bit: 22..25 Month */
|
---|
| 919 | uint32_t YEAR:6; /*!< bit: 26..31 Year */
|
---|
| 920 | } bit; /*!< Structure used for bit access */
|
---|
| 921 | uint32_t reg; /*!< Type used for register access */
|
---|
| 922 | } RTC_MODE2_ALARM_Type;
|
---|
| 923 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 924 |
|
---|
| 925 | #define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
|
---|
| 926 | #define RTC_MODE2_ALARM_RESETVALUE 0x00000000 /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
|
---|
| 927 |
|
---|
| 928 | #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
|
---|
| 929 | #define RTC_MODE2_ALARM_SECOND_Msk (0x3Fu << RTC_MODE2_ALARM_SECOND_Pos)
|
---|
| 930 | #define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)))
|
---|
| 931 | #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
|
---|
| 932 | #define RTC_MODE2_ALARM_MINUTE_Msk (0x3Fu << RTC_MODE2_ALARM_MINUTE_Pos)
|
---|
| 933 | #define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)))
|
---|
| 934 | #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
|
---|
| 935 | #define RTC_MODE2_ALARM_HOUR_Msk (0x1Fu << RTC_MODE2_ALARM_HOUR_Pos)
|
---|
| 936 | #define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)))
|
---|
| 937 | #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
|
---|
| 938 | #define RTC_MODE2_ALARM_DAY_Msk (0x1Fu << RTC_MODE2_ALARM_DAY_Pos)
|
---|
| 939 | #define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)))
|
---|
| 940 | #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
|
---|
| 941 | #define RTC_MODE2_ALARM_MONTH_Msk (0xFu << RTC_MODE2_ALARM_MONTH_Pos)
|
---|
| 942 | #define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)))
|
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| 943 | #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
|
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| 944 | #define RTC_MODE2_ALARM_YEAR_Msk (0x3Fu << RTC_MODE2_ALARM_YEAR_Pos)
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| 945 | #define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)))
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| 946 | #define RTC_MODE2_ALARM_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE2_ALARM) MASK Register */
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| 947 |
|
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| 948 | /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
|
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| 949 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 950 | typedef union {
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| 951 | struct {
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| 952 | uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
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| 953 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 954 | } bit; /*!< Structure used for bit access */
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| 955 | uint8_t reg; /*!< Type used for register access */
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| 956 | } RTC_MODE2_MASK_Type;
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| 957 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 958 |
|
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| 959 | #define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
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| 960 | #define RTC_MODE2_MASK_RESETVALUE 0x00 /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
|
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| 961 |
|
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| 962 | #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
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| 963 | #define RTC_MODE2_MASK_SEL_Msk (0x7u << RTC_MODE2_MASK_SEL_Pos)
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| 964 | #define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)))
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| 965 | #define RTC_MODE2_MASK_SEL_OFF_Val 0x0u /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
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| 966 | #define RTC_MODE2_MASK_SEL_SS_Val 0x1u /**< \brief (RTC_MODE2_MASK) Match seconds only */
|
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| 967 | #define RTC_MODE2_MASK_SEL_MMSS_Val 0x2u /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
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| 968 | #define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3u /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
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| 969 | #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4u /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
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| 970 | #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5u /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
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| 971 | #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6u /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
|
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| 972 | #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
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| 973 | #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
|
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| 974 | #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
|
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| 975 | #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
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| 976 | #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
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| 977 | #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
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| 978 | #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
|
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| 979 | #define RTC_MODE2_MASK_MASK 0x07u /**< \brief (RTC_MODE2_MASK) MASK Register */
|
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| 980 |
|
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| 981 | /** \brief RtcMode2Alarm hardware registers */
|
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| 982 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 983 | typedef struct {
|
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| 984 | __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
|
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| 985 | __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
|
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| 986 | RoReg8 Reserved1[0x3];
|
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| 987 | } RtcMode2Alarm;
|
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| 988 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 989 |
|
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| 990 | /** \brief RTC_MODE0 hardware registers */
|
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| 991 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 992 | typedef struct { /* 32-bit Counter with Single 32-bit Compare */
|
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| 993 | __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
|
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| 994 | __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
|
---|
| 995 | __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
|
---|
| 996 | __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
|
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| 997 | __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
|
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| 998 | __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
|
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| 999 | RoReg8 Reserved1[0x1];
|
---|
| 1000 | __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
|
---|
| 1001 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
|
---|
| 1002 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
|
---|
| 1003 | RoReg8 Reserved2[0x3];
|
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| 1004 | __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
|
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| 1005 | RoReg8 Reserved3[0x4];
|
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| 1006 | __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
|
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| 1007 | } RtcMode0;
|
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| 1008 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 1009 |
|
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| 1010 | /** \brief RTC_MODE1 hardware registers */
|
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| 1011 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 1012 | typedef struct { /* 16-bit Counter with Two 16-bit Compares */
|
---|
| 1013 | __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
|
---|
| 1014 | __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
|
---|
| 1015 | __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
|
---|
| 1016 | __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
|
---|
| 1017 | __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
|
---|
| 1018 | __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
|
---|
| 1019 | RoReg8 Reserved1[0x1];
|
---|
| 1020 | __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
|
---|
| 1021 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
|
---|
| 1022 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
|
---|
| 1023 | RoReg8 Reserved2[0x3];
|
---|
| 1024 | __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
|
---|
| 1025 | RoReg8 Reserved3[0x2];
|
---|
| 1026 | __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
|
---|
| 1027 | RoReg8 Reserved4[0x2];
|
---|
| 1028 | __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
|
---|
| 1029 | } RtcMode1;
|
---|
| 1030 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 1031 |
|
---|
| 1032 | /** \brief RTC_MODE2 hardware registers */
|
---|
| 1033 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 1034 | typedef struct { /* Clock/Calendar with Alarm */
|
---|
| 1035 | __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
|
---|
| 1036 | __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
|
---|
| 1037 | __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
|
---|
| 1038 | __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
|
---|
| 1039 | __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
|
---|
| 1040 | __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
|
---|
| 1041 | RoReg8 Reserved1[0x1];
|
---|
| 1042 | __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
|
---|
| 1043 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
|
---|
| 1044 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
|
---|
| 1045 | RoReg8 Reserved2[0x3];
|
---|
| 1046 | __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
|
---|
| 1047 | RoReg8 Reserved3[0x4];
|
---|
| 1048 | RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
|
---|
| 1049 | } RtcMode2;
|
---|
| 1050 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 1051 |
|
---|
| 1052 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 1053 | typedef union {
|
---|
| 1054 | RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
|
---|
| 1055 | RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
|
---|
| 1056 | RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
|
---|
| 1057 | } Rtc;
|
---|
| 1058 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 1059 |
|
---|
| 1060 | /*@}*/
|
---|
| 1061 |
|
---|
| 1062 | #endif /* _SAMD21_RTC_COMPONENT_ */
|
---|