source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/pm.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Component description for PM
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_PM_COMPONENT_
45#define _SAMD21_PM_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR PM */
49/* ========================================================================== */
50/** \addtogroup SAMD21_PM Power Manager */
51/*@{*/
52
53#define PM_U2206
54#define REV_PM 0x201
55
56/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 uint8_t reg; /*!< Type used for register access */
60} PM_CTRL_Type;
61#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
62
63#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
64#define PM_CTRL_RESETVALUE 0x00 /**< \brief (PM_CTRL reset_value) Control */
65
66#define PM_CTRL_MASK 0x00u /**< \brief (PM_CTRL) MASK Register */
67
68/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
69#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
70typedef union {
71 struct {
72 uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
73 uint8_t :6; /*!< bit: 2.. 7 Reserved */
74 } bit; /*!< Structure used for bit access */
75 uint8_t reg; /*!< Type used for register access */
76} PM_SLEEP_Type;
77#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
78
79#define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
80#define PM_SLEEP_RESETVALUE 0x00 /**< \brief (PM_SLEEP reset_value) Sleep Mode */
81
82#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
83#define PM_SLEEP_IDLE_Msk (0x3u << PM_SLEEP_IDLE_Pos)
84#define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
85#define PM_SLEEP_IDLE_CPU_Val 0x0u /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
86#define PM_SLEEP_IDLE_AHB_Val 0x1u /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
87#define PM_SLEEP_IDLE_APB_Val 0x2u /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
88#define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
89#define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
90#define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
91#define PM_SLEEP_MASK 0x03u /**< \brief (PM_SLEEP) MASK Register */
92
93/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
94#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
95typedef union {
96 struct {
97 uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
98 uint8_t :5; /*!< bit: 3.. 7 Reserved */
99 } bit; /*!< Structure used for bit access */
100 uint8_t reg; /*!< Type used for register access */
101} PM_CPUSEL_Type;
102#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
103
104#define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
105#define PM_CPUSEL_RESETVALUE 0x00 /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
106
107#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
108#define PM_CPUSEL_CPUDIV_Msk (0x7u << PM_CPUSEL_CPUDIV_Pos)
109#define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
110#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0u /**< \brief (PM_CPUSEL) Divide by 1 */
111#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1u /**< \brief (PM_CPUSEL) Divide by 2 */
112#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2u /**< \brief (PM_CPUSEL) Divide by 4 */
113#define PM_CPUSEL_CPUDIV_DIV8_Val 0x3u /**< \brief (PM_CPUSEL) Divide by 8 */
114#define PM_CPUSEL_CPUDIV_DIV16_Val 0x4u /**< \brief (PM_CPUSEL) Divide by 16 */
115#define PM_CPUSEL_CPUDIV_DIV32_Val 0x5u /**< \brief (PM_CPUSEL) Divide by 32 */
116#define PM_CPUSEL_CPUDIV_DIV64_Val 0x6u /**< \brief (PM_CPUSEL) Divide by 64 */
117#define PM_CPUSEL_CPUDIV_DIV128_Val 0x7u /**< \brief (PM_CPUSEL) Divide by 128 */
118#define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
119#define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
120#define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
121#define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
122#define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
123#define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
124#define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
125#define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
126#define PM_CPUSEL_MASK 0x07u /**< \brief (PM_CPUSEL) MASK Register */
127
128/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
129#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
130typedef union {
131 struct {
132 uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
133 uint8_t :5; /*!< bit: 3.. 7 Reserved */
134 } bit; /*!< Structure used for bit access */
135 uint8_t reg; /*!< Type used for register access */
136} PM_APBASEL_Type;
137#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
138
139#define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
140#define PM_APBASEL_RESETVALUE 0x00 /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
141
142#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
143#define PM_APBASEL_APBADIV_Msk (0x7u << PM_APBASEL_APBADIV_Pos)
144#define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
145#define PM_APBASEL_APBADIV_DIV1_Val 0x0u /**< \brief (PM_APBASEL) Divide by 1 */
146#define PM_APBASEL_APBADIV_DIV2_Val 0x1u /**< \brief (PM_APBASEL) Divide by 2 */
147#define PM_APBASEL_APBADIV_DIV4_Val 0x2u /**< \brief (PM_APBASEL) Divide by 4 */
148#define PM_APBASEL_APBADIV_DIV8_Val 0x3u /**< \brief (PM_APBASEL) Divide by 8 */
149#define PM_APBASEL_APBADIV_DIV16_Val 0x4u /**< \brief (PM_APBASEL) Divide by 16 */
150#define PM_APBASEL_APBADIV_DIV32_Val 0x5u /**< \brief (PM_APBASEL) Divide by 32 */
151#define PM_APBASEL_APBADIV_DIV64_Val 0x6u /**< \brief (PM_APBASEL) Divide by 64 */
152#define PM_APBASEL_APBADIV_DIV128_Val 0x7u /**< \brief (PM_APBASEL) Divide by 128 */
153#define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
154#define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
155#define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
156#define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
157#define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
158#define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
159#define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
160#define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
161#define PM_APBASEL_MASK 0x07u /**< \brief (PM_APBASEL) MASK Register */
162
163/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
164#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
165typedef union {
166 struct {
167 uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
168 uint8_t :5; /*!< bit: 3.. 7 Reserved */
169 } bit; /*!< Structure used for bit access */
170 uint8_t reg; /*!< Type used for register access */
171} PM_APBBSEL_Type;
172#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
173
174#define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
175#define PM_APBBSEL_RESETVALUE 0x00 /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
176
177#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
178#define PM_APBBSEL_APBBDIV_Msk (0x7u << PM_APBBSEL_APBBDIV_Pos)
179#define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
180#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0u /**< \brief (PM_APBBSEL) Divide by 1 */
181#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1u /**< \brief (PM_APBBSEL) Divide by 2 */
182#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2u /**< \brief (PM_APBBSEL) Divide by 4 */
183#define PM_APBBSEL_APBBDIV_DIV8_Val 0x3u /**< \brief (PM_APBBSEL) Divide by 8 */
184#define PM_APBBSEL_APBBDIV_DIV16_Val 0x4u /**< \brief (PM_APBBSEL) Divide by 16 */
185#define PM_APBBSEL_APBBDIV_DIV32_Val 0x5u /**< \brief (PM_APBBSEL) Divide by 32 */
186#define PM_APBBSEL_APBBDIV_DIV64_Val 0x6u /**< \brief (PM_APBBSEL) Divide by 64 */
187#define PM_APBBSEL_APBBDIV_DIV128_Val 0x7u /**< \brief (PM_APBBSEL) Divide by 128 */
188#define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
189#define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
190#define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
191#define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
192#define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
193#define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
194#define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
195#define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
196#define PM_APBBSEL_MASK 0x07u /**< \brief (PM_APBBSEL) MASK Register */
197
198/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
199#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
200typedef union {
201 struct {
202 uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
203 uint8_t :5; /*!< bit: 3.. 7 Reserved */
204 } bit; /*!< Structure used for bit access */
205 uint8_t reg; /*!< Type used for register access */
206} PM_APBCSEL_Type;
207#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
208
209#define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
210#define PM_APBCSEL_RESETVALUE 0x00 /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
211
212#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
213#define PM_APBCSEL_APBCDIV_Msk (0x7u << PM_APBCSEL_APBCDIV_Pos)
214#define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
215#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0u /**< \brief (PM_APBCSEL) Divide by 1 */
216#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1u /**< \brief (PM_APBCSEL) Divide by 2 */
217#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2u /**< \brief (PM_APBCSEL) Divide by 4 */
218#define PM_APBCSEL_APBCDIV_DIV8_Val 0x3u /**< \brief (PM_APBCSEL) Divide by 8 */
219#define PM_APBCSEL_APBCDIV_DIV16_Val 0x4u /**< \brief (PM_APBCSEL) Divide by 16 */
220#define PM_APBCSEL_APBCDIV_DIV32_Val 0x5u /**< \brief (PM_APBCSEL) Divide by 32 */
221#define PM_APBCSEL_APBCDIV_DIV64_Val 0x6u /**< \brief (PM_APBCSEL) Divide by 64 */
222#define PM_APBCSEL_APBCDIV_DIV128_Val 0x7u /**< \brief (PM_APBCSEL) Divide by 128 */
223#define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
224#define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
225#define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
226#define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
227#define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
228#define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
229#define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
230#define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
231#define PM_APBCSEL_MASK 0x07u /**< \brief (PM_APBCSEL) MASK Register */
232
233/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
234#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
235typedef union {
236 struct {
237 uint32_t HPB0:1; /*!< bit: 0 HPB0 AHB Clock Enable */
238 uint32_t HPB1:1; /*!< bit: 1 HPB1 AHB Clock Enable */
239 uint32_t HPB2:1; /*!< bit: 2 HPB2 AHB Clock Enable */
240 uint32_t DSU:1; /*!< bit: 3 DSU AHB Clock Enable */
241 uint32_t NVMCTRL:1; /*!< bit: 4 NVMCTRL AHB Clock Enable */
242 uint32_t DMAC:1; /*!< bit: 5 DMAC AHB Clock Enable */
243 uint32_t USB:1; /*!< bit: 6 USB AHB Clock Enable */
244 uint32_t :25; /*!< bit: 7..31 Reserved */
245 } bit; /*!< Structure used for bit access */
246 uint32_t reg; /*!< Type used for register access */
247} PM_AHBMASK_Type;
248#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
249
250#define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
251#define PM_AHBMASK_RESETVALUE 0x0000007F /**< \brief (PM_AHBMASK reset_value) AHB Mask */
252
253#define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Enable */
254#define PM_AHBMASK_HPB0 (0x1u << PM_AHBMASK_HPB0_Pos)
255#define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Enable */
256#define PM_AHBMASK_HPB1 (0x1u << PM_AHBMASK_HPB1_Pos)
257#define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Enable */
258#define PM_AHBMASK_HPB2 (0x1u << PM_AHBMASK_HPB2_Pos)
259#define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Enable */
260#define PM_AHBMASK_DSU (0x1u << PM_AHBMASK_DSU_Pos)
261#define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Enable */
262#define PM_AHBMASK_NVMCTRL (0x1u << PM_AHBMASK_NVMCTRL_Pos)
263#define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Enable */
264#define PM_AHBMASK_DMAC (0x1u << PM_AHBMASK_DMAC_Pos)
265#define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Enable */
266#define PM_AHBMASK_USB (0x1u << PM_AHBMASK_USB_Pos)
267#define PM_AHBMASK_MASK 0x0000007Fu /**< \brief (PM_AHBMASK) MASK Register */
268
269/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
270#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
271typedef union {
272 struct {
273 uint32_t PAC0:1; /*!< bit: 0 PAC0 APB Clock Enable */
274 uint32_t PM:1; /*!< bit: 1 PM APB Clock Enable */
275 uint32_t SYSCTRL:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
276 uint32_t GCLK:1; /*!< bit: 3 GCLK APB Clock Enable */
277 uint32_t WDT:1; /*!< bit: 4 WDT APB Clock Enable */
278 uint32_t RTC:1; /*!< bit: 5 RTC APB Clock Enable */
279 uint32_t EIC:1; /*!< bit: 6 EIC APB Clock Enable */
280 uint32_t :25; /*!< bit: 7..31 Reserved */
281 } bit; /*!< Structure used for bit access */
282 uint32_t reg; /*!< Type used for register access */
283} PM_APBAMASK_Type;
284#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
285
286#define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
287#define PM_APBAMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBAMASK reset_value) APBA Mask */
288
289#define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
290#define PM_APBAMASK_PAC0 (0x1u << PM_APBAMASK_PAC0_Pos)
291#define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
292#define PM_APBAMASK_PM (0x1u << PM_APBAMASK_PM_Pos)
293#define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
294#define PM_APBAMASK_SYSCTRL (0x1u << PM_APBAMASK_SYSCTRL_Pos)
295#define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
296#define PM_APBAMASK_GCLK (0x1u << PM_APBAMASK_GCLK_Pos)
297#define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
298#define PM_APBAMASK_WDT (0x1u << PM_APBAMASK_WDT_Pos)
299#define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
300#define PM_APBAMASK_RTC (0x1u << PM_APBAMASK_RTC_Pos)
301#define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
302#define PM_APBAMASK_EIC (0x1u << PM_APBAMASK_EIC_Pos)
303#define PM_APBAMASK_MASK 0x0000007Fu /**< \brief (PM_APBAMASK) MASK Register */
304
305/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
306#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
307typedef union {
308 struct {
309 uint32_t PAC1:1; /*!< bit: 0 PAC1 APB Clock Enable */
310 uint32_t DSU:1; /*!< bit: 1 DSU APB Clock Enable */
311 uint32_t NVMCTRL:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
312 uint32_t PORT:1; /*!< bit: 3 PORT APB Clock Enable */
313 uint32_t DMAC:1; /*!< bit: 4 DMAC APB Clock Enable */
314 uint32_t USB:1; /*!< bit: 5 USB APB Clock Enable */
315 uint32_t :26; /*!< bit: 6..31 Reserved */
316 } bit; /*!< Structure used for bit access */
317 uint32_t reg; /*!< Type used for register access */
318} PM_APBBMASK_Type;
319#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
320
321#define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
322#define PM_APBBMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBBMASK reset_value) APBB Mask */
323
324#define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
325#define PM_APBBMASK_PAC1 (0x1u << PM_APBBMASK_PAC1_Pos)
326#define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
327#define PM_APBBMASK_DSU (0x1u << PM_APBBMASK_DSU_Pos)
328#define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
329#define PM_APBBMASK_NVMCTRL (0x1u << PM_APBBMASK_NVMCTRL_Pos)
330#define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
331#define PM_APBBMASK_PORT (0x1u << PM_APBBMASK_PORT_Pos)
332#define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
333#define PM_APBBMASK_DMAC (0x1u << PM_APBBMASK_DMAC_Pos)
334#define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
335#define PM_APBBMASK_USB (0x1u << PM_APBBMASK_USB_Pos)
336#define PM_APBBMASK_MASK 0x0000003Fu /**< \brief (PM_APBBMASK) MASK Register */
337
338/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
339#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
340typedef union {
341 struct {
342 uint32_t PAC2:1; /*!< bit: 0 PAC2 APB Clock Enable */
343 uint32_t EVSYS:1; /*!< bit: 1 EVSYS APB Clock Enable */
344 uint32_t SERCOM0:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
345 uint32_t SERCOM1:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
346 uint32_t SERCOM2:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
347 uint32_t SERCOM3:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
348 uint32_t SERCOM4:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
349 uint32_t SERCOM5:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
350 uint32_t TCC0:1; /*!< bit: 8 TCC0 APB Clock Enable */
351 uint32_t TCC1:1; /*!< bit: 9 TCC1 APB Clock Enable */
352 uint32_t TCC2:1; /*!< bit: 10 TCC2 APB Clock Enable */
353 uint32_t TC3:1; /*!< bit: 11 TC3 APB Clock Enable */
354 uint32_t TC4:1; /*!< bit: 12 TC4 APB Clock Enable */
355 uint32_t TC5:1; /*!< bit: 13 TC5 APB Clock Enable */
356 uint32_t TC6:1; /*!< bit: 14 TC6 APB Clock Enable */
357 uint32_t TC7:1; /*!< bit: 15 TC7 APB Clock Enable */
358 uint32_t ADC:1; /*!< bit: 16 ADC APB Clock Enable */
359 uint32_t AC:1; /*!< bit: 17 AC APB Clock Enable */
360 uint32_t DAC:1; /*!< bit: 18 DAC APB Clock Enable */
361 uint32_t PTC:1; /*!< bit: 19 PTC APB Clock Enable */
362 uint32_t I2S:1; /*!< bit: 20 I2S APB Clock Enable */
363 uint32_t :11; /*!< bit: 21..31 Reserved */
364 } bit; /*!< Structure used for bit access */
365 uint32_t reg; /*!< Type used for register access */
366} PM_APBCMASK_Type;
367#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
368
369#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
370#define PM_APBCMASK_RESETVALUE 0x00010000 /**< \brief (PM_APBCMASK reset_value) APBC Mask */
371
372#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
373#define PM_APBCMASK_PAC2 (0x1u << PM_APBCMASK_PAC2_Pos)
374#define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
375#define PM_APBCMASK_EVSYS (0x1u << PM_APBCMASK_EVSYS_Pos)
376#define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
377#define PM_APBCMASK_SERCOM0 (0x1u << PM_APBCMASK_SERCOM0_Pos)
378#define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
379#define PM_APBCMASK_SERCOM1 (0x1u << PM_APBCMASK_SERCOM1_Pos)
380#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
381#define PM_APBCMASK_SERCOM2 (0x1u << PM_APBCMASK_SERCOM2_Pos)
382#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
383#define PM_APBCMASK_SERCOM3 (0x1u << PM_APBCMASK_SERCOM3_Pos)
384#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
385#define PM_APBCMASK_SERCOM4 (0x1u << PM_APBCMASK_SERCOM4_Pos)
386#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
387#define PM_APBCMASK_SERCOM5 (0x1u << PM_APBCMASK_SERCOM5_Pos)
388#define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
389#define PM_APBCMASK_TCC0 (0x1u << PM_APBCMASK_TCC0_Pos)
390#define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
391#define PM_APBCMASK_TCC1 (0x1u << PM_APBCMASK_TCC1_Pos)
392#define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
393#define PM_APBCMASK_TCC2 (0x1u << PM_APBCMASK_TCC2_Pos)
394#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
395#define PM_APBCMASK_TC3 (0x1u << PM_APBCMASK_TC3_Pos)
396#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
397#define PM_APBCMASK_TC4 (0x1u << PM_APBCMASK_TC4_Pos)
398#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
399#define PM_APBCMASK_TC5 (0x1u << PM_APBCMASK_TC5_Pos)
400#define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
401#define PM_APBCMASK_TC6 (0x1u << PM_APBCMASK_TC6_Pos)
402#define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
403#define PM_APBCMASK_TC7 (0x1u << PM_APBCMASK_TC7_Pos)
404#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
405#define PM_APBCMASK_ADC (0x1u << PM_APBCMASK_ADC_Pos)
406#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
407#define PM_APBCMASK_AC (0x1u << PM_APBCMASK_AC_Pos)
408#define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
409#define PM_APBCMASK_DAC (0x1u << PM_APBCMASK_DAC_Pos)
410#define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
411#define PM_APBCMASK_PTC (0x1u << PM_APBCMASK_PTC_Pos)
412#define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
413#define PM_APBCMASK_I2S (0x1u << PM_APBCMASK_I2S_Pos)
414#define PM_APBCMASK_MASK 0x001FFFFFu /**< \brief (PM_APBCMASK) MASK Register */
415
416/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
417#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
418typedef union {
419 struct {
420 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
421 uint8_t :7; /*!< bit: 1.. 7 Reserved */
422 } bit; /*!< Structure used for bit access */
423 uint8_t reg; /*!< Type used for register access */
424} PM_INTENCLR_Type;
425#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
426
427#define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
428#define PM_INTENCLR_RESETVALUE 0x00 /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
429
430#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
431#define PM_INTENCLR_CKRDY (0x1u << PM_INTENCLR_CKRDY_Pos)
432#define PM_INTENCLR_MASK 0x01u /**< \brief (PM_INTENCLR) MASK Register */
433
434/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
435#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
436typedef union {
437 struct {
438 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
439 uint8_t :7; /*!< bit: 1.. 7 Reserved */
440 } bit; /*!< Structure used for bit access */
441 uint8_t reg; /*!< Type used for register access */
442} PM_INTENSET_Type;
443#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
444
445#define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
446#define PM_INTENSET_RESETVALUE 0x00 /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
447
448#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
449#define PM_INTENSET_CKRDY (0x1u << PM_INTENSET_CKRDY_Pos)
450#define PM_INTENSET_MASK 0x01u /**< \brief (PM_INTENSET) MASK Register */
451
452/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
453#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
454typedef union {
455 struct {
456 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
457 uint8_t :7; /*!< bit: 1.. 7 Reserved */
458 } bit; /*!< Structure used for bit access */
459 uint8_t reg; /*!< Type used for register access */
460} PM_INTFLAG_Type;
461#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
462
463#define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
464#define PM_INTFLAG_RESETVALUE 0x00 /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
465
466#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
467#define PM_INTFLAG_CKRDY (0x1u << PM_INTFLAG_CKRDY_Pos)
468#define PM_INTFLAG_MASK 0x01u /**< \brief (PM_INTFLAG) MASK Register */
469
470/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
471#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
472typedef union {
473 struct {
474 uint8_t POR:1; /*!< bit: 0 Power On Reset */
475 uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
476 uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
477 uint8_t :1; /*!< bit: 3 Reserved */
478 uint8_t EXT:1; /*!< bit: 4 External Reset */
479 uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
480 uint8_t SYST:1; /*!< bit: 6 System Reset Request */
481 uint8_t :1; /*!< bit: 7 Reserved */
482 } bit; /*!< Structure used for bit access */
483 uint8_t reg; /*!< Type used for register access */
484} PM_RCAUSE_Type;
485#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
486
487#define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
488#define PM_RCAUSE_RESETVALUE 0x01 /**< \brief (PM_RCAUSE reset_value) Reset Cause */
489
490#define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
491#define PM_RCAUSE_POR (0x1u << PM_RCAUSE_POR_Pos)
492#define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
493#define PM_RCAUSE_BOD12 (0x1u << PM_RCAUSE_BOD12_Pos)
494#define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
495#define PM_RCAUSE_BOD33 (0x1u << PM_RCAUSE_BOD33_Pos)
496#define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
497#define PM_RCAUSE_EXT (0x1u << PM_RCAUSE_EXT_Pos)
498#define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
499#define PM_RCAUSE_WDT (0x1u << PM_RCAUSE_WDT_Pos)
500#define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
501#define PM_RCAUSE_SYST (0x1u << PM_RCAUSE_SYST_Pos)
502#define PM_RCAUSE_MASK 0x77u /**< \brief (PM_RCAUSE) MASK Register */
503
504/** \brief PM hardware registers */
505#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
506typedef struct {
507 __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
508 __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
509 RoReg8 Reserved1[0x6];
510 __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
511 __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
512 __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
513 __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
514 RoReg8 Reserved2[0x8];
515 __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
516 __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
517 __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
518 __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
519 RoReg8 Reserved3[0x10];
520 __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
521 __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
522 __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
523 RoReg8 Reserved4[0x1];
524 __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
525} Pm;
526#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
527
528/*@}*/
529
530#endif /* _SAMD21_PM_COMPONENT_ */
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