1 | /**
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2 | * \file
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3 | *
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4 | * \brief Component description for MTB
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_MTB_COMPONENT_
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45 | #define _SAMD21_MTB_COMPONENT_
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46 |
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47 | /* ========================================================================== */
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48 | /** SOFTWARE API DEFINITION FOR MTB */
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49 | /* ========================================================================== */
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50 | /** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
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51 | /*@{*/
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52 |
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53 | #define MTB_U2002
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54 | #define REV_MTB 0x100
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55 |
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56 | /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
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57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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58 | typedef union {
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59 | struct {
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60 | uint32_t :2; /*!< bit: 0.. 1 Reserved */
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61 | uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
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62 | uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
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63 | } bit; /*!< Structure used for bit access */
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64 | uint32_t reg; /*!< Type used for register access */
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65 | } MTB_POSITION_Type;
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66 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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67 |
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68 | #define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
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69 |
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70 | #define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
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71 | #define MTB_POSITION_WRAP (0x1u << MTB_POSITION_WRAP_Pos)
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72 | #define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
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73 | #define MTB_POSITION_POINTER_Msk (0x1FFFFFFFu << MTB_POSITION_POINTER_Pos)
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74 | #define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
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75 | #define MTB_POSITION_MASK 0xFFFFFFFCu /**< \brief (MTB_POSITION) MASK Register */
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76 |
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77 | /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
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78 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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79 | typedef union {
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80 | struct {
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81 | uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
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82 | uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
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83 | uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
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84 | uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
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85 | uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
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86 | uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
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87 | uint32_t :21; /*!< bit: 10..30 Reserved */
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88 | uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
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89 | } bit; /*!< Structure used for bit access */
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90 | uint32_t reg; /*!< Type used for register access */
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91 | } MTB_MASTER_Type;
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92 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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93 |
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94 | #define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
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95 | #define MTB_MASTER_RESETVALUE 0x00000000 /**< \brief (MTB_MASTER reset_value) MTB Master */
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96 |
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97 | #define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
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98 | #define MTB_MASTER_MASK_Msk (0x1Fu << MTB_MASTER_MASK_Pos)
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99 | #define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
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100 | #define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
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101 | #define MTB_MASTER_TSTARTEN (0x1u << MTB_MASTER_TSTARTEN_Pos)
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102 | #define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
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103 | #define MTB_MASTER_TSTOPEN (0x1u << MTB_MASTER_TSTOPEN_Pos)
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104 | #define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
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105 | #define MTB_MASTER_SFRWPRIV (0x1u << MTB_MASTER_SFRWPRIV_Pos)
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106 | #define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
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107 | #define MTB_MASTER_RAMPRIV (0x1u << MTB_MASTER_RAMPRIV_Pos)
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108 | #define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
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109 | #define MTB_MASTER_HALTREQ (0x1u << MTB_MASTER_HALTREQ_Pos)
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110 | #define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
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111 | #define MTB_MASTER_EN (0x1u << MTB_MASTER_EN_Pos)
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112 | #define MTB_MASTER_MASK_ 0x800003FFu /**< \brief (MTB_MASTER) MASK Register */
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113 |
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114 | /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
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115 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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116 | typedef union {
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117 | struct {
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118 | uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
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119 | uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
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120 | uint32_t :1; /*!< bit: 2 Reserved */
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121 | uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
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122 | } bit; /*!< Structure used for bit access */
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123 | uint32_t reg; /*!< Type used for register access */
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124 | } MTB_FLOW_Type;
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125 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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126 |
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127 | #define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
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128 | #define MTB_FLOW_RESETVALUE 0x00000000 /**< \brief (MTB_FLOW reset_value) MTB Flow */
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129 |
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130 | #define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
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131 | #define MTB_FLOW_AUTOSTOP (0x1u << MTB_FLOW_AUTOSTOP_Pos)
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132 | #define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
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133 | #define MTB_FLOW_AUTOHALT (0x1u << MTB_FLOW_AUTOHALT_Pos)
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134 | #define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
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135 | #define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFu << MTB_FLOW_WATERMARK_Pos)
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136 | #define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
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137 | #define MTB_FLOW_MASK 0xFFFFFFFBu /**< \brief (MTB_FLOW) MASK Register */
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138 |
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139 | /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
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140 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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141 | typedef union {
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142 | uint32_t reg; /*!< Type used for register access */
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143 | } MTB_BASE_Type;
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144 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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145 |
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146 | #define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
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147 | #define MTB_BASE_MASK 0xFFFFFFFFu /**< \brief (MTB_BASE) MASK Register */
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148 |
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149 | /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
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150 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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151 | typedef union {
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152 | uint32_t reg; /*!< Type used for register access */
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153 | } MTB_ITCTRL_Type;
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154 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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155 |
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156 | #define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
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157 | #define MTB_ITCTRL_MASK 0xFFFFFFFFu /**< \brief (MTB_ITCTRL) MASK Register */
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158 |
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159 | /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
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160 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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161 | typedef union {
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162 | uint32_t reg; /*!< Type used for register access */
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163 | } MTB_CLAIMSET_Type;
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164 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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165 |
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166 | #define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
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167 | #define MTB_CLAIMSET_MASK 0xFFFFFFFFu /**< \brief (MTB_CLAIMSET) MASK Register */
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168 |
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169 | /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
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170 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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171 | typedef union {
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172 | uint32_t reg; /*!< Type used for register access */
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173 | } MTB_CLAIMCLR_Type;
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174 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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175 |
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176 | #define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
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177 | #define MTB_CLAIMCLR_MASK 0xFFFFFFFFu /**< \brief (MTB_CLAIMCLR) MASK Register */
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178 |
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179 | /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
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180 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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181 | typedef union {
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182 | uint32_t reg; /*!< Type used for register access */
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183 | } MTB_LOCKACCESS_Type;
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184 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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185 |
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186 | #define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
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187 | #define MTB_LOCKACCESS_MASK 0xFFFFFFFFu /**< \brief (MTB_LOCKACCESS) MASK Register */
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188 |
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189 | /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
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190 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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191 | typedef union {
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192 | uint32_t reg; /*!< Type used for register access */
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193 | } MTB_LOCKSTATUS_Type;
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194 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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195 |
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196 | #define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
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197 | #define MTB_LOCKSTATUS_MASK 0xFFFFFFFFu /**< \brief (MTB_LOCKSTATUS) MASK Register */
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198 |
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199 | /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
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200 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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201 | typedef union {
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202 | uint32_t reg; /*!< Type used for register access */
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203 | } MTB_AUTHSTATUS_Type;
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204 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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205 |
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206 | #define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
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207 | #define MTB_AUTHSTATUS_MASK 0xFFFFFFFFu /**< \brief (MTB_AUTHSTATUS) MASK Register */
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208 |
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209 | /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
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210 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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211 | typedef union {
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212 | uint32_t reg; /*!< Type used for register access */
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213 | } MTB_DEVARCH_Type;
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214 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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215 |
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216 | #define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
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217 | #define MTB_DEVARCH_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVARCH) MASK Register */
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218 |
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219 | /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
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220 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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221 | typedef union {
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222 | uint32_t reg; /*!< Type used for register access */
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223 | } MTB_DEVID_Type;
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224 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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225 |
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226 | #define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
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227 | #define MTB_DEVID_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVID) MASK Register */
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228 |
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229 | /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
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230 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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231 | typedef union {
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232 | uint32_t reg; /*!< Type used for register access */
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233 | } MTB_DEVTYPE_Type;
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234 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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235 |
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236 | #define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
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237 | #define MTB_DEVTYPE_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVTYPE) MASK Register */
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238 |
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239 | /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
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240 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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241 | typedef union {
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242 | uint32_t reg; /*!< Type used for register access */
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243 | } MTB_PID4_Type;
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244 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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245 |
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246 | #define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
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247 | #define MTB_PID4_MASK 0xFFFFFFFFu /**< \brief (MTB_PID4) MASK Register */
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248 |
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249 | /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
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250 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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251 | typedef union {
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252 | uint32_t reg; /*!< Type used for register access */
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253 | } MTB_PID5_Type;
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254 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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255 |
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256 | #define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
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257 | #define MTB_PID5_MASK 0xFFFFFFFFu /**< \brief (MTB_PID5) MASK Register */
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258 |
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259 | /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
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260 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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261 | typedef union {
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262 | uint32_t reg; /*!< Type used for register access */
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263 | } MTB_PID6_Type;
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264 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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265 |
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266 | #define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
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267 | #define MTB_PID6_MASK 0xFFFFFFFFu /**< \brief (MTB_PID6) MASK Register */
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268 |
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269 | /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
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270 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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271 | typedef union {
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272 | uint32_t reg; /*!< Type used for register access */
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273 | } MTB_PID7_Type;
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274 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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275 |
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276 | #define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
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277 | #define MTB_PID7_MASK 0xFFFFFFFFu /**< \brief (MTB_PID7) MASK Register */
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278 |
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279 | /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
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280 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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281 | typedef union {
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282 | uint32_t reg; /*!< Type used for register access */
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283 | } MTB_PID0_Type;
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284 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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285 |
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286 | #define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
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287 | #define MTB_PID0_MASK 0xFFFFFFFFu /**< \brief (MTB_PID0) MASK Register */
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288 |
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289 | /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
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290 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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291 | typedef union {
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292 | uint32_t reg; /*!< Type used for register access */
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293 | } MTB_PID1_Type;
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294 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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295 |
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296 | #define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
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297 | #define MTB_PID1_MASK 0xFFFFFFFFu /**< \brief (MTB_PID1) MASK Register */
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298 |
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299 | /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
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300 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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301 | typedef union {
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302 | uint32_t reg; /*!< Type used for register access */
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303 | } MTB_PID2_Type;
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304 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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305 |
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306 | #define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
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307 | #define MTB_PID2_MASK 0xFFFFFFFFu /**< \brief (MTB_PID2) MASK Register */
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308 |
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309 | /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
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310 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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311 | typedef union {
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312 | uint32_t reg; /*!< Type used for register access */
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313 | } MTB_PID3_Type;
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314 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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315 |
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316 | #define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
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317 | #define MTB_PID3_MASK 0xFFFFFFFFu /**< \brief (MTB_PID3) MASK Register */
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318 |
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319 | /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
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320 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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321 | typedef union {
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322 | uint32_t reg; /*!< Type used for register access */
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323 | } MTB_CID0_Type;
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324 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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325 |
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326 | #define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
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327 | #define MTB_CID0_MASK 0xFFFFFFFFu /**< \brief (MTB_CID0) MASK Register */
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328 |
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329 | /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
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330 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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331 | typedef union {
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332 | uint32_t reg; /*!< Type used for register access */
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333 | } MTB_CID1_Type;
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334 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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335 |
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336 | #define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
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337 | #define MTB_CID1_MASK 0xFFFFFFFFu /**< \brief (MTB_CID1) MASK Register */
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338 |
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339 | /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
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340 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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341 | typedef union {
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342 | uint32_t reg; /*!< Type used for register access */
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343 | } MTB_CID2_Type;
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344 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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345 |
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346 | #define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
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347 | #define MTB_CID2_MASK 0xFFFFFFFFu /**< \brief (MTB_CID2) MASK Register */
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348 |
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349 | /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
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350 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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351 | typedef union {
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352 | uint32_t reg; /*!< Type used for register access */
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353 | } MTB_CID3_Type;
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354 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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355 |
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356 | #define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
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357 | #define MTB_CID3_MASK 0xFFFFFFFFu /**< \brief (MTB_CID3) MASK Register */
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358 |
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359 | /** \brief MTB hardware registers */
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360 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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361 | typedef struct {
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362 | __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
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363 | __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
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364 | __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
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365 | __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
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366 | RoReg8 Reserved1[0xEF0];
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367 | __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
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368 | RoReg8 Reserved2[0x9C];
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369 | __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
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370 | __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
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371 | RoReg8 Reserved3[0x8];
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372 | __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
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373 | __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
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374 | __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
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375 | __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
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376 | RoReg8 Reserved4[0x8];
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377 | __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
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378 | __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
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379 | __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
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380 | __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
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381 | __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
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382 | __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
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383 | __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
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384 | __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
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385 | __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
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386 | __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
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387 | __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
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388 | __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
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389 | __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
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390 | __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
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391 | } Mtb;
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392 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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393 |
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394 | /*@}*/
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395 |
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396 | #endif /* _SAMD21_MTB_COMPONENT_ */
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