[136] | 1 | /**
|
---|
| 2 | * \file
|
---|
| 3 | *
|
---|
| 4 | * \brief Component description for MTB
|
---|
| 5 | *
|
---|
| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
|
---|
| 7 | *
|
---|
| 8 | * \asf_license_start
|
---|
| 9 | *
|
---|
| 10 | * \page License
|
---|
| 11 | *
|
---|
| 12 | * Redistribution and use in source and binary forms, with or without
|
---|
| 13 | * modification, are permitted provided that the following conditions are met:
|
---|
| 14 | *
|
---|
| 15 | * 1. Redistributions of source code must retain the above copyright notice,
|
---|
| 16 | * this list of conditions and the following disclaimer.
|
---|
| 17 | *
|
---|
| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
|
---|
| 19 | * this list of conditions and the following disclaimer in the documentation
|
---|
| 20 | * and/or other materials provided with the distribution.
|
---|
| 21 | *
|
---|
| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
|
---|
| 23 | * from this software without specific prior written permission.
|
---|
| 24 | *
|
---|
| 25 | * 4. This software may only be redistributed and used in connection with an
|
---|
| 26 | * Atmel microcontroller product.
|
---|
| 27 | *
|
---|
| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
---|
| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
---|
| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
---|
| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
---|
| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
---|
| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
---|
| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
---|
| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
---|
| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
---|
| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
---|
| 38 | * POSSIBILITY OF SUCH DAMAGE.
|
---|
| 39 | *
|
---|
| 40 | * \asf_license_stop
|
---|
| 41 | *
|
---|
| 42 | */
|
---|
| 43 |
|
---|
| 44 | #ifndef _SAMD21_MTB_COMPONENT_
|
---|
| 45 | #define _SAMD21_MTB_COMPONENT_
|
---|
| 46 |
|
---|
| 47 | /* ========================================================================== */
|
---|
| 48 | /** SOFTWARE API DEFINITION FOR MTB */
|
---|
| 49 | /* ========================================================================== */
|
---|
| 50 | /** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
|
---|
| 51 | /*@{*/
|
---|
| 52 |
|
---|
| 53 | #define MTB_U2002
|
---|
| 54 | #define REV_MTB 0x100
|
---|
| 55 |
|
---|
| 56 | /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
|
---|
| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 58 | typedef union {
|
---|
| 59 | struct {
|
---|
| 60 | uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
---|
| 61 | uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
|
---|
| 62 | uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
|
---|
| 63 | } bit; /*!< Structure used for bit access */
|
---|
| 64 | uint32_t reg; /*!< Type used for register access */
|
---|
| 65 | } MTB_POSITION_Type;
|
---|
| 66 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 67 |
|
---|
| 68 | #define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
|
---|
| 69 |
|
---|
| 70 | #define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
|
---|
| 71 | #define MTB_POSITION_WRAP (0x1u << MTB_POSITION_WRAP_Pos)
|
---|
| 72 | #define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
|
---|
| 73 | #define MTB_POSITION_POINTER_Msk (0x1FFFFFFFu << MTB_POSITION_POINTER_Pos)
|
---|
| 74 | #define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
|
---|
| 75 | #define MTB_POSITION_MASK 0xFFFFFFFCu /**< \brief (MTB_POSITION) MASK Register */
|
---|
| 76 |
|
---|
| 77 | /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
|
---|
| 78 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 79 | typedef union {
|
---|
| 80 | struct {
|
---|
| 81 | uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
|
---|
| 82 | uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
|
---|
| 83 | uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
|
---|
| 84 | uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
|
---|
| 85 | uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
|
---|
| 86 | uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
|
---|
| 87 | uint32_t :21; /*!< bit: 10..30 Reserved */
|
---|
| 88 | uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
|
---|
| 89 | } bit; /*!< Structure used for bit access */
|
---|
| 90 | uint32_t reg; /*!< Type used for register access */
|
---|
| 91 | } MTB_MASTER_Type;
|
---|
| 92 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 93 |
|
---|
| 94 | #define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
|
---|
| 95 | #define MTB_MASTER_RESETVALUE 0x00000000 /**< \brief (MTB_MASTER reset_value) MTB Master */
|
---|
| 96 |
|
---|
| 97 | #define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
|
---|
| 98 | #define MTB_MASTER_MASK_Msk (0x1Fu << MTB_MASTER_MASK_Pos)
|
---|
| 99 | #define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
|
---|
| 100 | #define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
|
---|
| 101 | #define MTB_MASTER_TSTARTEN (0x1u << MTB_MASTER_TSTARTEN_Pos)
|
---|
| 102 | #define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
|
---|
| 103 | #define MTB_MASTER_TSTOPEN (0x1u << MTB_MASTER_TSTOPEN_Pos)
|
---|
| 104 | #define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
|
---|
| 105 | #define MTB_MASTER_SFRWPRIV (0x1u << MTB_MASTER_SFRWPRIV_Pos)
|
---|
| 106 | #define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
|
---|
| 107 | #define MTB_MASTER_RAMPRIV (0x1u << MTB_MASTER_RAMPRIV_Pos)
|
---|
| 108 | #define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
|
---|
| 109 | #define MTB_MASTER_HALTREQ (0x1u << MTB_MASTER_HALTREQ_Pos)
|
---|
| 110 | #define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
|
---|
| 111 | #define MTB_MASTER_EN (0x1u << MTB_MASTER_EN_Pos)
|
---|
| 112 | #define MTB_MASTER_MASK_ 0x800003FFu /**< \brief (MTB_MASTER) MASK Register */
|
---|
| 113 |
|
---|
| 114 | /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
|
---|
| 115 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 116 | typedef union {
|
---|
| 117 | struct {
|
---|
| 118 | uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
|
---|
| 119 | uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
|
---|
| 120 | uint32_t :1; /*!< bit: 2 Reserved */
|
---|
| 121 | uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
|
---|
| 122 | } bit; /*!< Structure used for bit access */
|
---|
| 123 | uint32_t reg; /*!< Type used for register access */
|
---|
| 124 | } MTB_FLOW_Type;
|
---|
| 125 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 126 |
|
---|
| 127 | #define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
|
---|
| 128 | #define MTB_FLOW_RESETVALUE 0x00000000 /**< \brief (MTB_FLOW reset_value) MTB Flow */
|
---|
| 129 |
|
---|
| 130 | #define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
|
---|
| 131 | #define MTB_FLOW_AUTOSTOP (0x1u << MTB_FLOW_AUTOSTOP_Pos)
|
---|
| 132 | #define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
|
---|
| 133 | #define MTB_FLOW_AUTOHALT (0x1u << MTB_FLOW_AUTOHALT_Pos)
|
---|
| 134 | #define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
|
---|
| 135 | #define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFu << MTB_FLOW_WATERMARK_Pos)
|
---|
| 136 | #define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
|
---|
| 137 | #define MTB_FLOW_MASK 0xFFFFFFFBu /**< \brief (MTB_FLOW) MASK Register */
|
---|
| 138 |
|
---|
| 139 | /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
|
---|
| 140 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 141 | typedef union {
|
---|
| 142 | uint32_t reg; /*!< Type used for register access */
|
---|
| 143 | } MTB_BASE_Type;
|
---|
| 144 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 145 |
|
---|
| 146 | #define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
|
---|
| 147 | #define MTB_BASE_MASK 0xFFFFFFFFu /**< \brief (MTB_BASE) MASK Register */
|
---|
| 148 |
|
---|
| 149 | /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
|
---|
| 150 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 151 | typedef union {
|
---|
| 152 | uint32_t reg; /*!< Type used for register access */
|
---|
| 153 | } MTB_ITCTRL_Type;
|
---|
| 154 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 155 |
|
---|
| 156 | #define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
|
---|
| 157 | #define MTB_ITCTRL_MASK 0xFFFFFFFFu /**< \brief (MTB_ITCTRL) MASK Register */
|
---|
| 158 |
|
---|
| 159 | /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
|
---|
| 160 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 161 | typedef union {
|
---|
| 162 | uint32_t reg; /*!< Type used for register access */
|
---|
| 163 | } MTB_CLAIMSET_Type;
|
---|
| 164 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 165 |
|
---|
| 166 | #define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
|
---|
| 167 | #define MTB_CLAIMSET_MASK 0xFFFFFFFFu /**< \brief (MTB_CLAIMSET) MASK Register */
|
---|
| 168 |
|
---|
| 169 | /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
|
---|
| 170 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 171 | typedef union {
|
---|
| 172 | uint32_t reg; /*!< Type used for register access */
|
---|
| 173 | } MTB_CLAIMCLR_Type;
|
---|
| 174 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 175 |
|
---|
| 176 | #define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
|
---|
| 177 | #define MTB_CLAIMCLR_MASK 0xFFFFFFFFu /**< \brief (MTB_CLAIMCLR) MASK Register */
|
---|
| 178 |
|
---|
| 179 | /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
|
---|
| 180 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 181 | typedef union {
|
---|
| 182 | uint32_t reg; /*!< Type used for register access */
|
---|
| 183 | } MTB_LOCKACCESS_Type;
|
---|
| 184 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 185 |
|
---|
| 186 | #define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
|
---|
| 187 | #define MTB_LOCKACCESS_MASK 0xFFFFFFFFu /**< \brief (MTB_LOCKACCESS) MASK Register */
|
---|
| 188 |
|
---|
| 189 | /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
|
---|
| 190 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 191 | typedef union {
|
---|
| 192 | uint32_t reg; /*!< Type used for register access */
|
---|
| 193 | } MTB_LOCKSTATUS_Type;
|
---|
| 194 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 195 |
|
---|
| 196 | #define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
|
---|
| 197 | #define MTB_LOCKSTATUS_MASK 0xFFFFFFFFu /**< \brief (MTB_LOCKSTATUS) MASK Register */
|
---|
| 198 |
|
---|
| 199 | /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
|
---|
| 200 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 201 | typedef union {
|
---|
| 202 | uint32_t reg; /*!< Type used for register access */
|
---|
| 203 | } MTB_AUTHSTATUS_Type;
|
---|
| 204 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 205 |
|
---|
| 206 | #define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
|
---|
| 207 | #define MTB_AUTHSTATUS_MASK 0xFFFFFFFFu /**< \brief (MTB_AUTHSTATUS) MASK Register */
|
---|
| 208 |
|
---|
| 209 | /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
|
---|
| 210 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 211 | typedef union {
|
---|
| 212 | uint32_t reg; /*!< Type used for register access */
|
---|
| 213 | } MTB_DEVARCH_Type;
|
---|
| 214 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 215 |
|
---|
| 216 | #define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
|
---|
| 217 | #define MTB_DEVARCH_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVARCH) MASK Register */
|
---|
| 218 |
|
---|
| 219 | /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
|
---|
| 220 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 221 | typedef union {
|
---|
| 222 | uint32_t reg; /*!< Type used for register access */
|
---|
| 223 | } MTB_DEVID_Type;
|
---|
| 224 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 225 |
|
---|
| 226 | #define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
|
---|
| 227 | #define MTB_DEVID_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVID) MASK Register */
|
---|
| 228 |
|
---|
| 229 | /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
|
---|
| 230 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 231 | typedef union {
|
---|
| 232 | uint32_t reg; /*!< Type used for register access */
|
---|
| 233 | } MTB_DEVTYPE_Type;
|
---|
| 234 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 235 |
|
---|
| 236 | #define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
|
---|
| 237 | #define MTB_DEVTYPE_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVTYPE) MASK Register */
|
---|
| 238 |
|
---|
| 239 | /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
|
---|
| 240 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 241 | typedef union {
|
---|
| 242 | uint32_t reg; /*!< Type used for register access */
|
---|
| 243 | } MTB_PID4_Type;
|
---|
| 244 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 245 |
|
---|
| 246 | #define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
|
---|
| 247 | #define MTB_PID4_MASK 0xFFFFFFFFu /**< \brief (MTB_PID4) MASK Register */
|
---|
| 248 |
|
---|
| 249 | /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
|
---|
| 250 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 251 | typedef union {
|
---|
| 252 | uint32_t reg; /*!< Type used for register access */
|
---|
| 253 | } MTB_PID5_Type;
|
---|
| 254 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 255 |
|
---|
| 256 | #define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
|
---|
| 257 | #define MTB_PID5_MASK 0xFFFFFFFFu /**< \brief (MTB_PID5) MASK Register */
|
---|
| 258 |
|
---|
| 259 | /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
|
---|
| 260 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 261 | typedef union {
|
---|
| 262 | uint32_t reg; /*!< Type used for register access */
|
---|
| 263 | } MTB_PID6_Type;
|
---|
| 264 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 265 |
|
---|
| 266 | #define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
|
---|
| 267 | #define MTB_PID6_MASK 0xFFFFFFFFu /**< \brief (MTB_PID6) MASK Register */
|
---|
| 268 |
|
---|
| 269 | /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
|
---|
| 270 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 271 | typedef union {
|
---|
| 272 | uint32_t reg; /*!< Type used for register access */
|
---|
| 273 | } MTB_PID7_Type;
|
---|
| 274 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 275 |
|
---|
| 276 | #define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
|
---|
| 277 | #define MTB_PID7_MASK 0xFFFFFFFFu /**< \brief (MTB_PID7) MASK Register */
|
---|
| 278 |
|
---|
| 279 | /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
|
---|
| 280 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 281 | typedef union {
|
---|
| 282 | uint32_t reg; /*!< Type used for register access */
|
---|
| 283 | } MTB_PID0_Type;
|
---|
| 284 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 285 |
|
---|
| 286 | #define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
|
---|
| 287 | #define MTB_PID0_MASK 0xFFFFFFFFu /**< \brief (MTB_PID0) MASK Register */
|
---|
| 288 |
|
---|
| 289 | /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
|
---|
| 290 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 291 | typedef union {
|
---|
| 292 | uint32_t reg; /*!< Type used for register access */
|
---|
| 293 | } MTB_PID1_Type;
|
---|
| 294 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 295 |
|
---|
| 296 | #define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
|
---|
| 297 | #define MTB_PID1_MASK 0xFFFFFFFFu /**< \brief (MTB_PID1) MASK Register */
|
---|
| 298 |
|
---|
| 299 | /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
|
---|
| 300 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 301 | typedef union {
|
---|
| 302 | uint32_t reg; /*!< Type used for register access */
|
---|
| 303 | } MTB_PID2_Type;
|
---|
| 304 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 305 |
|
---|
| 306 | #define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
|
---|
| 307 | #define MTB_PID2_MASK 0xFFFFFFFFu /**< \brief (MTB_PID2) MASK Register */
|
---|
| 308 |
|
---|
| 309 | /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
|
---|
| 310 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 311 | typedef union {
|
---|
| 312 | uint32_t reg; /*!< Type used for register access */
|
---|
| 313 | } MTB_PID3_Type;
|
---|
| 314 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 315 |
|
---|
| 316 | #define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
|
---|
| 317 | #define MTB_PID3_MASK 0xFFFFFFFFu /**< \brief (MTB_PID3) MASK Register */
|
---|
| 318 |
|
---|
| 319 | /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
|
---|
| 320 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 321 | typedef union {
|
---|
| 322 | uint32_t reg; /*!< Type used for register access */
|
---|
| 323 | } MTB_CID0_Type;
|
---|
| 324 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 325 |
|
---|
| 326 | #define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
|
---|
| 327 | #define MTB_CID0_MASK 0xFFFFFFFFu /**< \brief (MTB_CID0) MASK Register */
|
---|
| 328 |
|
---|
| 329 | /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
|
---|
| 330 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 331 | typedef union {
|
---|
| 332 | uint32_t reg; /*!< Type used for register access */
|
---|
| 333 | } MTB_CID1_Type;
|
---|
| 334 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 335 |
|
---|
| 336 | #define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
|
---|
| 337 | #define MTB_CID1_MASK 0xFFFFFFFFu /**< \brief (MTB_CID1) MASK Register */
|
---|
| 338 |
|
---|
| 339 | /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
|
---|
| 340 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 341 | typedef union {
|
---|
| 342 | uint32_t reg; /*!< Type used for register access */
|
---|
| 343 | } MTB_CID2_Type;
|
---|
| 344 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 345 |
|
---|
| 346 | #define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
|
---|
| 347 | #define MTB_CID2_MASK 0xFFFFFFFFu /**< \brief (MTB_CID2) MASK Register */
|
---|
| 348 |
|
---|
| 349 | /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
|
---|
| 350 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 351 | typedef union {
|
---|
| 352 | uint32_t reg; /*!< Type used for register access */
|
---|
| 353 | } MTB_CID3_Type;
|
---|
| 354 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 355 |
|
---|
| 356 | #define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
|
---|
| 357 | #define MTB_CID3_MASK 0xFFFFFFFFu /**< \brief (MTB_CID3) MASK Register */
|
---|
| 358 |
|
---|
| 359 | /** \brief MTB hardware registers */
|
---|
| 360 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 361 | typedef struct {
|
---|
| 362 | __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
|
---|
| 363 | __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
|
---|
| 364 | __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
|
---|
| 365 | __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
|
---|
| 366 | RoReg8 Reserved1[0xEF0];
|
---|
| 367 | __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
|
---|
| 368 | RoReg8 Reserved2[0x9C];
|
---|
| 369 | __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
|
---|
| 370 | __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
|
---|
| 371 | RoReg8 Reserved3[0x8];
|
---|
| 372 | __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
|
---|
| 373 | __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
|
---|
| 374 | __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
|
---|
| 375 | __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
|
---|
| 376 | RoReg8 Reserved4[0x8];
|
---|
| 377 | __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
|
---|
| 378 | __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
|
---|
| 379 | __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
|
---|
| 380 | __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
|
---|
| 381 | __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
|
---|
| 382 | __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
|
---|
| 383 | __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
|
---|
| 384 | __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
|
---|
| 385 | __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
|
---|
| 386 | __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
|
---|
| 387 | __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
|
---|
| 388 | __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
|
---|
| 389 | __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
|
---|
| 390 | __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
|
---|
| 391 | } Mtb;
|
---|
| 392 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 393 |
|
---|
| 394 | /*@}*/
|
---|
| 395 |
|
---|
| 396 | #endif /* _SAMD21_MTB_COMPONENT_ */
|
---|