1 | /**
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2 | * \file
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3 | *
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4 | * \brief Component description for EVSYS
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_EVSYS_COMPONENT_
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45 | #define _SAMD21_EVSYS_COMPONENT_
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46 |
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47 | /* ========================================================================== */
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48 | /** SOFTWARE API DEFINITION FOR EVSYS */
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49 | /* ========================================================================== */
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50 | /** \addtogroup SAMD21_EVSYS Event System Interface */
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51 | /*@{*/
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52 |
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53 | #define EVSYS_U2208
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54 | #define REV_EVSYS 0x101
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55 |
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56 | /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
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57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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58 | typedef union {
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59 | struct {
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60 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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61 | uint8_t :3; /*!< bit: 1.. 3 Reserved */
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62 | uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
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63 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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64 | } bit; /*!< Structure used for bit access */
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65 | uint8_t reg; /*!< Type used for register access */
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66 | } EVSYS_CTRL_Type;
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67 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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68 |
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69 | #define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
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70 | #define EVSYS_CTRL_RESETVALUE 0x00 /**< \brief (EVSYS_CTRL reset_value) Control */
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71 |
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72 | #define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
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73 | #define EVSYS_CTRL_SWRST (0x1u << EVSYS_CTRL_SWRST_Pos)
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74 | #define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
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75 | #define EVSYS_CTRL_GCLKREQ (0x1u << EVSYS_CTRL_GCLKREQ_Pos)
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76 | #define EVSYS_CTRL_MASK 0x11u /**< \brief (EVSYS_CTRL) MASK Register */
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77 |
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78 | /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
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79 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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80 | typedef union {
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81 | struct {
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82 | uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
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83 | uint32_t :4; /*!< bit: 4.. 7 Reserved */
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84 | uint32_t SWEVT:1; /*!< bit: 8 Software Event */
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85 | uint32_t :7; /*!< bit: 9..15 Reserved */
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86 | uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
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87 | uint32_t :1; /*!< bit: 23 Reserved */
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88 | uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
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89 | uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
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90 | uint32_t :4; /*!< bit: 28..31 Reserved */
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91 | } bit; /*!< Structure used for bit access */
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92 | uint32_t reg; /*!< Type used for register access */
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93 | } EVSYS_CHANNEL_Type;
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94 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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95 |
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96 | #define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
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97 | #define EVSYS_CHANNEL_RESETVALUE 0x00000000 /**< \brief (EVSYS_CHANNEL reset_value) Channel */
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98 |
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99 | #define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
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100 | #define EVSYS_CHANNEL_CHANNEL_Msk (0xFu << EVSYS_CHANNEL_CHANNEL_Pos)
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101 | #define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
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102 | #define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
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103 | #define EVSYS_CHANNEL_SWEVT (0x1u << EVSYS_CHANNEL_SWEVT_Pos)
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104 | #define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
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105 | #define EVSYS_CHANNEL_EVGEN_Msk (0x7Fu << EVSYS_CHANNEL_EVGEN_Pos)
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106 | #define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
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107 | #define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
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108 | #define EVSYS_CHANNEL_PATH_Msk (0x3u << EVSYS_CHANNEL_PATH_Pos)
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109 | #define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
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110 | #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0u /**< \brief (EVSYS_CHANNEL) Synchronous path */
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111 | #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1u /**< \brief (EVSYS_CHANNEL) Resynchronized path */
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112 | #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2u /**< \brief (EVSYS_CHANNEL) Asynchronous path */
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113 | #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
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114 | #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
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115 | #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
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116 | #define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
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117 | #define EVSYS_CHANNEL_EDGSEL_Msk (0x3u << EVSYS_CHANNEL_EDGSEL_Pos)
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118 | #define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
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119 | #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0u /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
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120 | #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1u /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
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121 | #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2u /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
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122 | #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3u /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
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123 | #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
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124 | #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
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125 | #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
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126 | #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
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127 | #define EVSYS_CHANNEL_MASK 0x0F7F010Fu /**< \brief (EVSYS_CHANNEL) MASK Register */
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128 |
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129 | /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
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130 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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131 | typedef union {
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132 | struct {
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133 | uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
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134 | uint16_t :3; /*!< bit: 5.. 7 Reserved */
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135 | uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
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136 | uint16_t :3; /*!< bit: 13..15 Reserved */
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137 | } bit; /*!< Structure used for bit access */
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138 | uint16_t reg; /*!< Type used for register access */
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139 | } EVSYS_USER_Type;
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140 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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141 |
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142 | #define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
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143 | #define EVSYS_USER_RESETVALUE 0x0000 /**< \brief (EVSYS_USER reset_value) User Multiplexer */
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144 |
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145 | #define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
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146 | #define EVSYS_USER_USER_Msk (0x1Fu << EVSYS_USER_USER_Pos)
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147 | #define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
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148 | #define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
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149 | #define EVSYS_USER_CHANNEL_Msk (0x1Fu << EVSYS_USER_CHANNEL_Pos)
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150 | #define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
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151 | #define EVSYS_USER_CHANNEL_0_Val 0x0u /**< \brief (EVSYS_USER) No Channel Output Selected */
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152 | #define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
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153 | #define EVSYS_USER_MASK 0x1F1Fu /**< \brief (EVSYS_USER) MASK Register */
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154 |
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155 | /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
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156 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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157 | typedef union {
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158 | struct {
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159 | uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
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160 | uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
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161 | uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
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162 | uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
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163 | uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
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164 | uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
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165 | uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
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166 | uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
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167 | uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
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168 | uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
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169 | uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
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170 | uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
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171 | uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
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172 | uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
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173 | uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
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174 | uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
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175 | uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
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176 | uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
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177 | uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
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178 | uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
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179 | uint32_t :4; /*!< bit: 20..23 Reserved */
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180 | uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
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181 | uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
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182 | uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
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183 | uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
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184 | uint32_t :4; /*!< bit: 28..31 Reserved */
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185 | } bit; /*!< Structure used for bit access */
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186 | struct {
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187 | uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
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188 | uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
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189 | uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
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190 | uint32_t :4; /*!< bit: 20..23 Reserved */
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191 | uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
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192 | uint32_t :4; /*!< bit: 28..31 Reserved */
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193 | } vec; /*!< Structure used for vec access */
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194 | uint32_t reg; /*!< Type used for register access */
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195 | } EVSYS_CHSTATUS_Type;
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196 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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197 |
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198 | #define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
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199 | #define EVSYS_CHSTATUS_RESETVALUE 0x000F00FF /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
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200 |
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201 | #define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
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202 | #define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
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203 | #define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
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204 | #define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
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205 | #define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
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206 | #define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
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207 | #define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
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208 | #define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
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209 | #define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
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210 | #define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
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211 | #define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
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212 | #define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
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213 | #define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
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214 | #define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
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215 | #define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
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216 | #define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
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217 | #define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
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218 | #define EVSYS_CHSTATUS_USRRDY_Msk (0xFFu << EVSYS_CHSTATUS_USRRDY_Pos)
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219 | #define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
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220 | #define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
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221 | #define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
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222 | #define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
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223 | #define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
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224 | #define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
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225 | #define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
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226 | #define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
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227 | #define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
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228 | #define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
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229 | #define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
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230 | #define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
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231 | #define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
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232 | #define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
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233 | #define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
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234 | #define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
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235 | #define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
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236 | #define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
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237 | #define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFu << EVSYS_CHSTATUS_CHBUSY_Pos)
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238 | #define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
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239 | #define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
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240 | #define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
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241 | #define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
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242 | #define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
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243 | #define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
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244 | #define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
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245 | #define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
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246 | #define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
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247 | #define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
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248 | #define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFu << EVSYS_CHSTATUS_USRRDYp8_Pos)
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249 | #define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)))
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250 | #define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
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251 | #define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
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252 | #define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
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253 | #define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
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254 | #define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
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255 | #define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
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256 | #define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
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257 | #define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
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258 | #define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
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259 | #define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFu << EVSYS_CHSTATUS_CHBUSYp8_Pos)
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260 | #define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)))
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261 | #define EVSYS_CHSTATUS_MASK 0x0F0FFFFFu /**< \brief (EVSYS_CHSTATUS) MASK Register */
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262 |
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263 | /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
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264 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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265 | typedef union {
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266 | struct {
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267 | uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
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268 | uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
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269 | uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
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270 | uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
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271 | uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
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272 | uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
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273 | uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
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274 | uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
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275 | uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
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276 | uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
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277 | uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
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278 | uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
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279 | uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
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280 | uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
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281 | uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
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282 | uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
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283 | uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
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284 | uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
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285 | uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
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286 | uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
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287 | uint32_t :4; /*!< bit: 20..23 Reserved */
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288 | uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
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289 | uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
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290 | uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
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291 | uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
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292 | uint32_t :4; /*!< bit: 28..31 Reserved */
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293 | } bit; /*!< Structure used for bit access */
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294 | struct {
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295 | uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
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296 | uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
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297 | uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
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298 | uint32_t :4; /*!< bit: 20..23 Reserved */
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299 | uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
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300 | uint32_t :4; /*!< bit: 28..31 Reserved */
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301 | } vec; /*!< Structure used for vec access */
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302 | uint32_t reg; /*!< Type used for register access */
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303 | } EVSYS_INTENCLR_Type;
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304 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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305 |
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306 | #define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
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307 | #define EVSYS_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
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308 |
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309 | #define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
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310 | #define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
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311 | #define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
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312 | #define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
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313 | #define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
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314 | #define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
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315 | #define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
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316 | #define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
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317 | #define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
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318 | #define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
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319 | #define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
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320 | #define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
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321 | #define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
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322 | #define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
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323 | #define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
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324 | #define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
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325 | #define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
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326 | #define EVSYS_INTENCLR_OVR_Msk (0xFFu << EVSYS_INTENCLR_OVR_Pos)
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327 | #define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
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328 | #define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
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329 | #define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
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330 | #define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
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331 | #define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
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332 | #define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
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333 | #define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
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334 | #define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
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335 | #define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
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336 | #define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
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337 | #define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
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338 | #define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
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339 | #define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
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340 | #define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
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341 | #define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
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342 | #define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
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343 | #define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
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344 | #define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
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345 | #define EVSYS_INTENCLR_EVD_Msk (0xFFu << EVSYS_INTENCLR_EVD_Pos)
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346 | #define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
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347 | #define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
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348 | #define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
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349 | #define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
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350 | #define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
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351 | #define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
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352 | #define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
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353 | #define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
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354 | #define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
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355 | #define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
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356 | #define EVSYS_INTENCLR_OVRp8_Msk (0xFu << EVSYS_INTENCLR_OVRp8_Pos)
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357 | #define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)))
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358 | #define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
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359 | #define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
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360 | #define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
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361 | #define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
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362 | #define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
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363 | #define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
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364 | #define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
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365 | #define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
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366 | #define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
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367 | #define EVSYS_INTENCLR_EVDp8_Msk (0xFu << EVSYS_INTENCLR_EVDp8_Pos)
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368 | #define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)))
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369 | #define EVSYS_INTENCLR_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTENCLR) MASK Register */
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370 |
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371 | /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
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372 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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373 | typedef union {
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374 | struct {
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375 | uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
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376 | uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
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377 | uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
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378 | uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
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379 | uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
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380 | uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
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381 | uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
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382 | uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
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383 | uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
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384 | uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
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385 | uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
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386 | uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
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387 | uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
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388 | uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
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389 | uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
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390 | uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
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391 | uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
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392 | uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
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393 | uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
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394 | uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
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395 | uint32_t :4; /*!< bit: 20..23 Reserved */
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396 | uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
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397 | uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
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398 | uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
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399 | uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
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400 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
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401 | } bit; /*!< Structure used for bit access */
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402 | struct {
|
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403 | uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
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404 | uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
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405 | uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
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406 | uint32_t :4; /*!< bit: 20..23 Reserved */
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407 | uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
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408 | uint32_t :4; /*!< bit: 28..31 Reserved */
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409 | } vec; /*!< Structure used for vec access */
|
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410 | uint32_t reg; /*!< Type used for register access */
|
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411 | } EVSYS_INTENSET_Type;
|
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412 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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413 |
|
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414 | #define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
|
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415 | #define EVSYS_INTENSET_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
|
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416 |
|
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417 | #define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
|
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418 | #define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
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419 | #define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
|
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420 | #define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
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421 | #define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
|
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422 | #define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
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423 | #define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
|
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424 | #define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
|
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425 | #define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
|
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426 | #define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
|
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427 | #define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
|
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428 | #define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
|
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429 | #define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
|
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430 | #define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
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431 | #define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
|
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432 | #define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
|
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433 | #define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
|
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434 | #define EVSYS_INTENSET_OVR_Msk (0xFFu << EVSYS_INTENSET_OVR_Pos)
|
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435 | #define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
|
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436 | #define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
|
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437 | #define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
|
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438 | #define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
|
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439 | #define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
|
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440 | #define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
|
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441 | #define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
|
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442 | #define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
|
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443 | #define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
|
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444 | #define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
|
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445 | #define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
|
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446 | #define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
|
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447 | #define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
|
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448 | #define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
|
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449 | #define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
|
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450 | #define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
|
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451 | #define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
|
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452 | #define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
|
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453 | #define EVSYS_INTENSET_EVD_Msk (0xFFu << EVSYS_INTENSET_EVD_Pos)
|
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454 | #define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
|
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455 | #define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
|
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456 | #define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
|
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457 | #define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
|
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458 | #define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
|
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459 | #define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
|
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460 | #define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
|
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461 | #define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
|
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462 | #define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
|
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463 | #define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
|
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464 | #define EVSYS_INTENSET_OVRp8_Msk (0xFu << EVSYS_INTENSET_OVRp8_Pos)
|
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465 | #define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)))
|
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466 | #define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
|
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467 | #define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
|
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468 | #define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
|
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469 | #define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
|
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470 | #define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
|
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471 | #define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
|
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472 | #define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
|
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473 | #define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
|
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474 | #define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
|
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475 | #define EVSYS_INTENSET_EVDp8_Msk (0xFu << EVSYS_INTENSET_EVDp8_Pos)
|
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476 | #define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)))
|
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477 | #define EVSYS_INTENSET_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTENSET) MASK Register */
|
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478 |
|
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479 | /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
|
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480 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
481 | typedef union {
|
---|
482 | struct {
|
---|
483 | uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
|
---|
484 | uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
|
---|
485 | uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
|
---|
486 | uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
|
---|
487 | uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
|
---|
488 | uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
|
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489 | uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
|
---|
490 | uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
|
---|
491 | uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
|
---|
492 | uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
|
---|
493 | uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
|
---|
494 | uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
|
---|
495 | uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
|
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496 | uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
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497 | uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
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498 | uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
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499 | uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
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500 | uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
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501 | uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
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502 | uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
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503 | uint32_t :4; /*!< bit: 20..23 Reserved */
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504 | uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
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505 | uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
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506 | uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
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507 | uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
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508 | uint32_t :4; /*!< bit: 28..31 Reserved */
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509 | } bit; /*!< Structure used for bit access */
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510 | struct {
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511 | uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
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512 | uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
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513 | uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
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514 | uint32_t :4; /*!< bit: 20..23 Reserved */
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515 | uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
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516 | uint32_t :4; /*!< bit: 28..31 Reserved */
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517 | } vec; /*!< Structure used for vec access */
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518 | uint32_t reg; /*!< Type used for register access */
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519 | } EVSYS_INTFLAG_Type;
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520 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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521 |
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522 | #define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
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523 | #define EVSYS_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
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524 |
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525 | #define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
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526 | #define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
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527 | #define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
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528 | #define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
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529 | #define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
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530 | #define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
|
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531 | #define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
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532 | #define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
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533 | #define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
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534 | #define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
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535 | #define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
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536 | #define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
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537 | #define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
|
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538 | #define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
|
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539 | #define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
|
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540 | #define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
|
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541 | #define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
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542 | #define EVSYS_INTFLAG_OVR_Msk (0xFFu << EVSYS_INTFLAG_OVR_Pos)
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543 | #define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
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544 | #define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
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545 | #define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
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546 | #define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
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547 | #define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
|
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548 | #define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
|
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549 | #define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
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550 | #define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
|
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551 | #define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
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552 | #define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
|
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553 | #define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
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554 | #define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
|
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555 | #define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
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556 | #define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
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557 | #define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
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558 | #define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
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559 | #define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
|
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560 | #define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
|
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561 | #define EVSYS_INTFLAG_EVD_Msk (0xFFu << EVSYS_INTFLAG_EVD_Pos)
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562 | #define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
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563 | #define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
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564 | #define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
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565 | #define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
|
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566 | #define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
|
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567 | #define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
|
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568 | #define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
|
---|
569 | #define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
|
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570 | #define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
|
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571 | #define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
|
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572 | #define EVSYS_INTFLAG_OVRp8_Msk (0xFu << EVSYS_INTFLAG_OVRp8_Pos)
|
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573 | #define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)))
|
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574 | #define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
|
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575 | #define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
|
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576 | #define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
|
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577 | #define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
|
---|
578 | #define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
|
---|
579 | #define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
|
---|
580 | #define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
|
---|
581 | #define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
|
---|
582 | #define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
|
---|
583 | #define EVSYS_INTFLAG_EVDp8_Msk (0xFu << EVSYS_INTFLAG_EVDp8_Pos)
|
---|
584 | #define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)))
|
---|
585 | #define EVSYS_INTFLAG_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTFLAG) MASK Register */
|
---|
586 |
|
---|
587 | /** \brief EVSYS hardware registers */
|
---|
588 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
589 | typedef struct {
|
---|
590 | __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
|
---|
591 | RoReg8 Reserved1[0x3];
|
---|
592 | __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
|
---|
593 | __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
|
---|
594 | RoReg8 Reserved2[0x2];
|
---|
595 | __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
|
---|
596 | __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
|
---|
597 | __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
|
---|
598 | __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
|
---|
599 | } Evsys;
|
---|
600 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
601 |
|
---|
602 | /*@}*/
|
---|
603 |
|
---|
604 | #endif /* _SAMD21_EVSYS_COMPONENT_ */
|
---|