source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/dsu.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Component description for DSU
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_DSU_COMPONENT_
45#define _SAMD21_DSU_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR DSU */
49/* ========================================================================== */
50/** \addtogroup SAMD21_DSU Device Service Unit */
51/*@{*/
52
53#define DSU_U2209
54#define REV_DSU 0x200
55
56/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
61 uint8_t :1; /*!< bit: 1 Reserved */
62 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
63 uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
64 uint8_t CE:1; /*!< bit: 4 Chip Erase */
65 uint8_t :3; /*!< bit: 5.. 7 Reserved */
66 } bit; /*!< Structure used for bit access */
67 uint8_t reg; /*!< Type used for register access */
68} DSU_CTRL_Type;
69#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
70
71#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
72#define DSU_CTRL_RESETVALUE 0x00 /**< \brief (DSU_CTRL reset_value) Control */
73
74#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
75#define DSU_CTRL_SWRST (0x1u << DSU_CTRL_SWRST_Pos)
76#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
77#define DSU_CTRL_CRC (0x1u << DSU_CTRL_CRC_Pos)
78#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
79#define DSU_CTRL_MBIST (0x1u << DSU_CTRL_MBIST_Pos)
80#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
81#define DSU_CTRL_CE (0x1u << DSU_CTRL_CE_Pos)
82#define DSU_CTRL_MASK 0x1Du /**< \brief (DSU_CTRL) MASK Register */
83
84/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
85#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
86typedef union {
87 struct {
88 uint8_t DONE:1; /*!< bit: 0 Done */
89 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
90 uint8_t BERR:1; /*!< bit: 2 Bus Error */
91 uint8_t FAIL:1; /*!< bit: 3 Failure */
92 uint8_t PERR:1; /*!< bit: 4 Protection Error */
93 uint8_t :3; /*!< bit: 5.. 7 Reserved */
94 } bit; /*!< Structure used for bit access */
95 uint8_t reg; /*!< Type used for register access */
96} DSU_STATUSA_Type;
97#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
98
99#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
100#define DSU_STATUSA_RESETVALUE 0x00 /**< \brief (DSU_STATUSA reset_value) Status A */
101
102#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
103#define DSU_STATUSA_DONE (0x1u << DSU_STATUSA_DONE_Pos)
104#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
105#define DSU_STATUSA_CRSTEXT (0x1u << DSU_STATUSA_CRSTEXT_Pos)
106#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
107#define DSU_STATUSA_BERR (0x1u << DSU_STATUSA_BERR_Pos)
108#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
109#define DSU_STATUSA_FAIL (0x1u << DSU_STATUSA_FAIL_Pos)
110#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
111#define DSU_STATUSA_PERR (0x1u << DSU_STATUSA_PERR_Pos)
112#define DSU_STATUSA_MASK 0x1Fu /**< \brief (DSU_STATUSA) MASK Register */
113
114/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
115#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
116typedef union {
117 struct {
118 uint8_t PROT:1; /*!< bit: 0 Protected */
119 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
120 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
121 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
122 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
123 uint8_t :3; /*!< bit: 5.. 7 Reserved */
124 } bit; /*!< Structure used for bit access */
125 struct {
126 uint8_t :2; /*!< bit: 0.. 1 Reserved */
127 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
128 uint8_t :4; /*!< bit: 4.. 7 Reserved */
129 } vec; /*!< Structure used for vec access */
130 uint8_t reg; /*!< Type used for register access */
131} DSU_STATUSB_Type;
132#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
133
134#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
135#define DSU_STATUSB_RESETVALUE 0x10 /**< \brief (DSU_STATUSB reset_value) Status B */
136
137#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
138#define DSU_STATUSB_PROT (0x1u << DSU_STATUSB_PROT_Pos)
139#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
140#define DSU_STATUSB_DBGPRES (0x1u << DSU_STATUSB_DBGPRES_Pos)
141#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
142#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
143#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
144#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
145#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
146#define DSU_STATUSB_DCCD_Msk (0x3u << DSU_STATUSB_DCCD_Pos)
147#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
148#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
149#define DSU_STATUSB_HPE (0x1u << DSU_STATUSB_HPE_Pos)
150#define DSU_STATUSB_MASK 0x1Fu /**< \brief (DSU_STATUSB) MASK Register */
151
152/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
153#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
154typedef union {
155 struct {
156 uint32_t :2; /*!< bit: 0.. 1 Reserved */
157 uint32_t ADDR:30; /*!< bit: 2..31 Address */
158 } bit; /*!< Structure used for bit access */
159 uint32_t reg; /*!< Type used for register access */
160} DSU_ADDR_Type;
161#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
162
163#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
164#define DSU_ADDR_RESETVALUE 0x00000000 /**< \brief (DSU_ADDR reset_value) Address */
165
166#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
167#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFu << DSU_ADDR_ADDR_Pos)
168#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
169#define DSU_ADDR_MASK 0xFFFFFFFCu /**< \brief (DSU_ADDR) MASK Register */
170
171/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
172#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
173typedef union {
174 struct {
175 uint32_t :2; /*!< bit: 0.. 1 Reserved */
176 uint32_t LENGTH:30; /*!< bit: 2..31 Length */
177 } bit; /*!< Structure used for bit access */
178 uint32_t reg; /*!< Type used for register access */
179} DSU_LENGTH_Type;
180#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
181
182#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
183#define DSU_LENGTH_RESETVALUE 0x00000000 /**< \brief (DSU_LENGTH reset_value) Length */
184
185#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
186#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFu << DSU_LENGTH_LENGTH_Pos)
187#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
188#define DSU_LENGTH_MASK 0xFFFFFFFCu /**< \brief (DSU_LENGTH) MASK Register */
189
190/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
191#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
192typedef union {
193 struct {
194 uint32_t DATA:32; /*!< bit: 0..31 Data */
195 } bit; /*!< Structure used for bit access */
196 uint32_t reg; /*!< Type used for register access */
197} DSU_DATA_Type;
198#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
199
200#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
201#define DSU_DATA_RESETVALUE 0x00000000 /**< \brief (DSU_DATA reset_value) Data */
202
203#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
204#define DSU_DATA_DATA_Msk (0xFFFFFFFFu << DSU_DATA_DATA_Pos)
205#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
206#define DSU_DATA_MASK 0xFFFFFFFFu /**< \brief (DSU_DATA) MASK Register */
207
208/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
209#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
210typedef union {
211 struct {
212 uint32_t DATA:32; /*!< bit: 0..31 Data */
213 } bit; /*!< Structure used for bit access */
214 uint32_t reg; /*!< Type used for register access */
215} DSU_DCC_Type;
216#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
217
218#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
219#define DSU_DCC_RESETVALUE 0x00000000 /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
220
221#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
222#define DSU_DCC_DATA_Msk (0xFFFFFFFFu << DSU_DCC_DATA_Pos)
223#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
224#define DSU_DCC_MASK 0xFFFFFFFFu /**< \brief (DSU_DCC) MASK Register */
225
226/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
227#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
228typedef union {
229 struct {
230 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
231 uint32_t REVISION:4; /*!< bit: 8..11 Revision */
232 uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
233 uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
234 uint32_t :1; /*!< bit: 22 Reserved */
235 uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
236 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
237 } bit; /*!< Structure used for bit access */
238 uint32_t reg; /*!< Type used for register access */
239} DSU_DID_Type;
240#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
241
242#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
243
244#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
245#define DSU_DID_DEVSEL_Msk (0xFFu << DSU_DID_DEVSEL_Pos)
246#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
247#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
248#define DSU_DID_REVISION_Msk (0xFu << DSU_DID_REVISION_Pos)
249#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
250#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
251#define DSU_DID_DIE_Msk (0xFu << DSU_DID_DIE_Pos)
252#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
253#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
254#define DSU_DID_SERIES_Msk (0x3Fu << DSU_DID_SERIES_Pos)
255#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
256#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
257#define DSU_DID_FAMILY_Msk (0x1Fu << DSU_DID_FAMILY_Pos)
258#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
259#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
260#define DSU_DID_PROCESSOR_Msk (0xFu << DSU_DID_PROCESSOR_Pos)
261#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
262#define DSU_DID_MASK 0xFFBFFFFFu /**< \brief (DSU_DID) MASK Register */
263
264/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
265#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
266typedef union {
267 struct {
268 uint32_t EPRES:1; /*!< bit: 0 Entry Present */
269 uint32_t FMT:1; /*!< bit: 1 Format */
270 uint32_t :10; /*!< bit: 2..11 Reserved */
271 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
272 } bit; /*!< Structure used for bit access */
273 uint32_t reg; /*!< Type used for register access */
274} DSU_ENTRY_Type;
275#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
276
277#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
278#define DSU_ENTRY_RESETVALUE 0x00000002 /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
279
280#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
281#define DSU_ENTRY_EPRES (0x1u << DSU_ENTRY_EPRES_Pos)
282#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
283#define DSU_ENTRY_FMT (0x1u << DSU_ENTRY_FMT_Pos)
284#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
285#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFu << DSU_ENTRY_ADDOFF_Pos)
286#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
287#define DSU_ENTRY_MASK 0xFFFFF003u /**< \brief (DSU_ENTRY) MASK Register */
288
289/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
290#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
291typedef union {
292 struct {
293 uint32_t END:32; /*!< bit: 0..31 End Marker */
294 } bit; /*!< Structure used for bit access */
295 uint32_t reg; /*!< Type used for register access */
296} DSU_END_Type;
297#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
298
299#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
300#define DSU_END_RESETVALUE 0x00000000 /**< \brief (DSU_END reset_value) Coresight ROM Table End */
301
302#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
303#define DSU_END_END_Msk (0xFFFFFFFFu << DSU_END_END_Pos)
304#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
305#define DSU_END_MASK 0xFFFFFFFFu /**< \brief (DSU_END) MASK Register */
306
307/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
308#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
309typedef union {
310 struct {
311 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
312 uint32_t :31; /*!< bit: 1..31 Reserved */
313 } bit; /*!< Structure used for bit access */
314 uint32_t reg; /*!< Type used for register access */
315} DSU_MEMTYPE_Type;
316#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
317
318#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
319#define DSU_MEMTYPE_RESETVALUE 0x00000000 /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
320
321#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
322#define DSU_MEMTYPE_SMEMP (0x1u << DSU_MEMTYPE_SMEMP_Pos)
323#define DSU_MEMTYPE_MASK 0x00000001u /**< \brief (DSU_MEMTYPE) MASK Register */
324
325/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
326#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
327typedef union {
328 struct {
329 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
330 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
331 uint32_t :24; /*!< bit: 8..31 Reserved */
332 } bit; /*!< Structure used for bit access */
333 uint32_t reg; /*!< Type used for register access */
334} DSU_PID4_Type;
335#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
336
337#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
338#define DSU_PID4_RESETVALUE 0x00000000 /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
339
340#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
341#define DSU_PID4_JEPCC_Msk (0xFu << DSU_PID4_JEPCC_Pos)
342#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
343#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
344#define DSU_PID4_FKBC_Msk (0xFu << DSU_PID4_FKBC_Pos)
345#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
346#define DSU_PID4_MASK 0x000000FFu /**< \brief (DSU_PID4) MASK Register */
347
348/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
349#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
350typedef union {
351 struct {
352 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
353 uint32_t :24; /*!< bit: 8..31 Reserved */
354 } bit; /*!< Structure used for bit access */
355 uint32_t reg; /*!< Type used for register access */
356} DSU_PID0_Type;
357#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
358
359#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
360#define DSU_PID0_RESETVALUE 0x000000D0 /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
361
362#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
363#define DSU_PID0_PARTNBL_Msk (0xFFu << DSU_PID0_PARTNBL_Pos)
364#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
365#define DSU_PID0_MASK 0x000000FFu /**< \brief (DSU_PID0) MASK Register */
366
367/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
368#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
369typedef union {
370 struct {
371 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
372 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
373 uint32_t :24; /*!< bit: 8..31 Reserved */
374 } bit; /*!< Structure used for bit access */
375 uint32_t reg; /*!< Type used for register access */
376} DSU_PID1_Type;
377#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
378
379#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
380#define DSU_PID1_RESETVALUE 0x000000FC /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
381
382#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
383#define DSU_PID1_PARTNBH_Msk (0xFu << DSU_PID1_PARTNBH_Pos)
384#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
385#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
386#define DSU_PID1_JEPIDCL_Msk (0xFu << DSU_PID1_JEPIDCL_Pos)
387#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
388#define DSU_PID1_MASK 0x000000FFu /**< \brief (DSU_PID1) MASK Register */
389
390/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
391#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
392typedef union {
393 struct {
394 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
395 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
396 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
397 uint32_t :24; /*!< bit: 8..31 Reserved */
398 } bit; /*!< Structure used for bit access */
399 uint32_t reg; /*!< Type used for register access */
400} DSU_PID2_Type;
401#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
402
403#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
404#define DSU_PID2_RESETVALUE 0x00000009 /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
405
406#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
407#define DSU_PID2_JEPIDCH_Msk (0x7u << DSU_PID2_JEPIDCH_Pos)
408#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
409#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
410#define DSU_PID2_JEPU (0x1u << DSU_PID2_JEPU_Pos)
411#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
412#define DSU_PID2_REVISION_Msk (0xFu << DSU_PID2_REVISION_Pos)
413#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
414#define DSU_PID2_MASK 0x000000FFu /**< \brief (DSU_PID2) MASK Register */
415
416/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
417#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
418typedef union {
419 struct {
420 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
421 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
422 uint32_t :24; /*!< bit: 8..31 Reserved */
423 } bit; /*!< Structure used for bit access */
424 uint32_t reg; /*!< Type used for register access */
425} DSU_PID3_Type;
426#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
427
428#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
429#define DSU_PID3_RESETVALUE 0x00000000 /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
430
431#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
432#define DSU_PID3_CUSMOD_Msk (0xFu << DSU_PID3_CUSMOD_Pos)
433#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
434#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
435#define DSU_PID3_REVAND_Msk (0xFu << DSU_PID3_REVAND_Pos)
436#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
437#define DSU_PID3_MASK 0x000000FFu /**< \brief (DSU_PID3) MASK Register */
438
439/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
440#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
441typedef union {
442 struct {
443 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
444 uint32_t :24; /*!< bit: 8..31 Reserved */
445 } bit; /*!< Structure used for bit access */
446 uint32_t reg; /*!< Type used for register access */
447} DSU_CID0_Type;
448#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
449
450#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
451#define DSU_CID0_RESETVALUE 0x0000000D /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
452
453#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
454#define DSU_CID0_PREAMBLEB0_Msk (0xFFu << DSU_CID0_PREAMBLEB0_Pos)
455#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
456#define DSU_CID0_MASK 0x000000FFu /**< \brief (DSU_CID0) MASK Register */
457
458/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
459#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
460typedef union {
461 struct {
462 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
463 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
464 uint32_t :24; /*!< bit: 8..31 Reserved */
465 } bit; /*!< Structure used for bit access */
466 uint32_t reg; /*!< Type used for register access */
467} DSU_CID1_Type;
468#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
469
470#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
471#define DSU_CID1_RESETVALUE 0x00000010 /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
472
473#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
474#define DSU_CID1_PREAMBLE_Msk (0xFu << DSU_CID1_PREAMBLE_Pos)
475#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
476#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
477#define DSU_CID1_CCLASS_Msk (0xFu << DSU_CID1_CCLASS_Pos)
478#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
479#define DSU_CID1_MASK 0x000000FFu /**< \brief (DSU_CID1) MASK Register */
480
481/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
482#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
483typedef union {
484 struct {
485 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
486 uint32_t :24; /*!< bit: 8..31 Reserved */
487 } bit; /*!< Structure used for bit access */
488 uint32_t reg; /*!< Type used for register access */
489} DSU_CID2_Type;
490#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
491
492#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
493#define DSU_CID2_RESETVALUE 0x00000005 /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
494
495#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
496#define DSU_CID2_PREAMBLEB2_Msk (0xFFu << DSU_CID2_PREAMBLEB2_Pos)
497#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
498#define DSU_CID2_MASK 0x000000FFu /**< \brief (DSU_CID2) MASK Register */
499
500/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
501#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
502typedef union {
503 struct {
504 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
505 uint32_t :24; /*!< bit: 8..31 Reserved */
506 } bit; /*!< Structure used for bit access */
507 uint32_t reg; /*!< Type used for register access */
508} DSU_CID3_Type;
509#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
510
511#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
512#define DSU_CID3_RESETVALUE 0x000000B1 /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
513
514#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
515#define DSU_CID3_PREAMBLEB3_Msk (0xFFu << DSU_CID3_PREAMBLEB3_Pos)
516#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
517#define DSU_CID3_MASK 0x000000FFu /**< \brief (DSU_CID3) MASK Register */
518
519/** \brief DSU hardware registers */
520#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
521typedef struct {
522 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
523 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
524 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
525 RoReg8 Reserved1[0x1];
526 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
527 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
528 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
529 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
530 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
531 RoReg8 Reserved2[0xFE4];
532 __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
533 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
534 RoReg8 Reserved3[0xFC0];
535 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
536 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
537 RoReg8 Reserved4[0xC];
538 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
539 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
540 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
541 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
542 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
543 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
544 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
545 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
546} Dsu;
547#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
548
549/*@}*/
550
551#endif /* _SAMD21_DSU_COMPONENT_ */
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