1 | /**
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2 | * \file
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3 | *
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4 | * \brief Component description for ADC
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_ADC_COMPONENT_
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45 | #define _SAMD21_ADC_COMPONENT_
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46 |
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47 | /* ========================================================================== */
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48 | /** SOFTWARE API DEFINITION FOR ADC */
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49 | /* ========================================================================== */
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50 | /** \addtogroup SAMD21_ADC Analog Digital Converter */
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51 | /*@{*/
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52 |
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53 | #define ADC_U2204
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54 | #define REV_ADC 0x120
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55 |
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56 | /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
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57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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58 | typedef union {
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59 | struct {
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60 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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61 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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62 | uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
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63 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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64 | } bit; /*!< Structure used for bit access */
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65 | uint8_t reg; /*!< Type used for register access */
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66 | } ADC_CTRLA_Type;
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67 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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68 |
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69 | #define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
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70 | #define ADC_CTRLA_RESETVALUE 0x00 /**< \brief (ADC_CTRLA reset_value) Control A */
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71 |
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72 | #define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
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73 | #define ADC_CTRLA_SWRST (0x1u << ADC_CTRLA_SWRST_Pos)
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74 | #define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
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75 | #define ADC_CTRLA_ENABLE (0x1u << ADC_CTRLA_ENABLE_Pos)
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76 | #define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
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77 | #define ADC_CTRLA_RUNSTDBY (0x1u << ADC_CTRLA_RUNSTDBY_Pos)
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78 | #define ADC_CTRLA_MASK 0x07u /**< \brief (ADC_CTRLA) MASK Register */
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79 |
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80 | /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
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81 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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82 | typedef union {
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83 | struct {
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84 | uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
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85 | uint8_t :3; /*!< bit: 4.. 6 Reserved */
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86 | uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
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87 | } bit; /*!< Structure used for bit access */
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88 | uint8_t reg; /*!< Type used for register access */
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89 | } ADC_REFCTRL_Type;
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90 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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91 |
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92 | #define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
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93 | #define ADC_REFCTRL_RESETVALUE 0x00 /**< \brief (ADC_REFCTRL reset_value) Reference Control */
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94 |
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95 | #define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
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96 | #define ADC_REFCTRL_REFSEL_Msk (0xFu << ADC_REFCTRL_REFSEL_Pos)
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97 | #define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))
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98 | #define ADC_REFCTRL_REFSEL_INT1V_Val 0x0u /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
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99 | #define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1u /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
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100 | #define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2u /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
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101 | #define ADC_REFCTRL_REFSEL_AREFA_Val 0x3u /**< \brief (ADC_REFCTRL) External reference */
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102 | #define ADC_REFCTRL_REFSEL_AREFB_Val 0x4u /**< \brief (ADC_REFCTRL) External reference */
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103 | #define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
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104 | #define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
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105 | #define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
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106 | #define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
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107 | #define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
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108 | #define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
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109 | #define ADC_REFCTRL_REFCOMP (0x1u << ADC_REFCTRL_REFCOMP_Pos)
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110 | #define ADC_REFCTRL_MASK 0x8Fu /**< \brief (ADC_REFCTRL) MASK Register */
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111 |
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112 | /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
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113 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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114 | typedef union {
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115 | struct {
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116 | uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
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117 | uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
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118 | uint8_t :1; /*!< bit: 7 Reserved */
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119 | } bit; /*!< Structure used for bit access */
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120 | uint8_t reg; /*!< Type used for register access */
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121 | } ADC_AVGCTRL_Type;
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122 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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123 |
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124 | #define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
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125 | #define ADC_AVGCTRL_RESETVALUE 0x00 /**< \brief (ADC_AVGCTRL reset_value) Average Control */
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126 |
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127 | #define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
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128 | #define ADC_AVGCTRL_SAMPLENUM_Msk (0xFu << ADC_AVGCTRL_SAMPLENUM_Pos)
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129 | #define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))
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130 | #define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0u /**< \brief (ADC_AVGCTRL) 1 sample */
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131 | #define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1u /**< \brief (ADC_AVGCTRL) 2 samples */
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132 | #define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2u /**< \brief (ADC_AVGCTRL) 4 samples */
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133 | #define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3u /**< \brief (ADC_AVGCTRL) 8 samples */
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134 | #define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4u /**< \brief (ADC_AVGCTRL) 16 samples */
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135 | #define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5u /**< \brief (ADC_AVGCTRL) 32 samples */
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136 | #define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6u /**< \brief (ADC_AVGCTRL) 64 samples */
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137 | #define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7u /**< \brief (ADC_AVGCTRL) 128 samples */
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138 | #define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8u /**< \brief (ADC_AVGCTRL) 256 samples */
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139 | #define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9u /**< \brief (ADC_AVGCTRL) 512 samples */
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140 | #define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAu /**< \brief (ADC_AVGCTRL) 1024 samples */
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141 | #define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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142 | #define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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143 | #define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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144 | #define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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145 | #define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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146 | #define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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147 | #define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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148 | #define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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149 | #define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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150 | #define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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151 | #define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
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152 | #define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
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153 | #define ADC_AVGCTRL_ADJRES_Msk (0x7u << ADC_AVGCTRL_ADJRES_Pos)
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154 | #define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))
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155 | #define ADC_AVGCTRL_MASK 0x7Fu /**< \brief (ADC_AVGCTRL) MASK Register */
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156 |
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157 | /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
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158 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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159 | typedef union {
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160 | struct {
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161 | uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
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162 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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163 | } bit; /*!< Structure used for bit access */
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164 | uint8_t reg; /*!< Type used for register access */
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165 | } ADC_SAMPCTRL_Type;
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166 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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167 |
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168 | #define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
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169 | #define ADC_SAMPCTRL_RESETVALUE 0x00 /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
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170 |
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171 | #define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
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172 | #define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Fu << ADC_SAMPCTRL_SAMPLEN_Pos)
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173 | #define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))
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174 | #define ADC_SAMPCTRL_MASK 0x3Fu /**< \brief (ADC_SAMPCTRL) MASK Register */
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175 |
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176 | /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
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177 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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178 | typedef union {
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179 | struct {
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180 | uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
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181 | uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
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182 | uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
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183 | uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
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184 | uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
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185 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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186 | uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
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187 | uint16_t :5; /*!< bit: 11..15 Reserved */
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188 | } bit; /*!< Structure used for bit access */
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189 | uint16_t reg; /*!< Type used for register access */
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190 | } ADC_CTRLB_Type;
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191 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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192 |
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193 | #define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
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194 | #define ADC_CTRLB_RESETVALUE 0x0000 /**< \brief (ADC_CTRLB reset_value) Control B */
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195 |
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196 | #define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
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197 | #define ADC_CTRLB_DIFFMODE (0x1u << ADC_CTRLB_DIFFMODE_Pos)
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198 | #define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
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199 | #define ADC_CTRLB_LEFTADJ (0x1u << ADC_CTRLB_LEFTADJ_Pos)
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200 | #define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
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201 | #define ADC_CTRLB_FREERUN (0x1u << ADC_CTRLB_FREERUN_Pos)
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202 | #define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
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203 | #define ADC_CTRLB_CORREN (0x1u << ADC_CTRLB_CORREN_Pos)
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204 | #define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
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205 | #define ADC_CTRLB_RESSEL_Msk (0x3u << ADC_CTRLB_RESSEL_Pos)
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206 | #define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))
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207 | #define ADC_CTRLB_RESSEL_12BIT_Val 0x0u /**< \brief (ADC_CTRLB) 12-bit result */
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208 | #define ADC_CTRLB_RESSEL_16BIT_Val 0x1u /**< \brief (ADC_CTRLB) For averaging mode output */
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209 | #define ADC_CTRLB_RESSEL_10BIT_Val 0x2u /**< \brief (ADC_CTRLB) 10-bit result */
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210 | #define ADC_CTRLB_RESSEL_8BIT_Val 0x3u /**< \brief (ADC_CTRLB) 8-bit result */
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211 | #define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
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212 | #define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
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213 | #define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
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214 | #define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
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215 | #define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
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216 | #define ADC_CTRLB_PRESCALER_Msk (0x7u << ADC_CTRLB_PRESCALER_Pos)
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217 | #define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))
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218 | #define ADC_CTRLB_PRESCALER_DIV4_Val 0x0u /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
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219 | #define ADC_CTRLB_PRESCALER_DIV8_Val 0x1u /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
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220 | #define ADC_CTRLB_PRESCALER_DIV16_Val 0x2u /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
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221 | #define ADC_CTRLB_PRESCALER_DIV32_Val 0x3u /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
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222 | #define ADC_CTRLB_PRESCALER_DIV64_Val 0x4u /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
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223 | #define ADC_CTRLB_PRESCALER_DIV128_Val 0x5u /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
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224 | #define ADC_CTRLB_PRESCALER_DIV256_Val 0x6u /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
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225 | #define ADC_CTRLB_PRESCALER_DIV512_Val 0x7u /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
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226 | #define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
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227 | #define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
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228 | #define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
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229 | #define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
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230 | #define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
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231 | #define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
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232 | #define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
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233 | #define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
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234 | #define ADC_CTRLB_MASK 0x073Fu /**< \brief (ADC_CTRLB) MASK Register */
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235 |
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236 | /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
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237 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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238 | typedef union {
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239 | struct {
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240 | uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
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241 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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242 | } bit; /*!< Structure used for bit access */
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243 | uint8_t reg; /*!< Type used for register access */
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244 | } ADC_WINCTRL_Type;
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245 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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246 |
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247 | #define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
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248 | #define ADC_WINCTRL_RESETVALUE 0x00 /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
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249 |
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250 | #define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
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251 | #define ADC_WINCTRL_WINMODE_Msk (0x7u << ADC_WINCTRL_WINMODE_Pos)
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252 | #define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))
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253 | #define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0u /**< \brief (ADC_WINCTRL) No window mode (default) */
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254 | #define ADC_WINCTRL_WINMODE_MODE1_Val 0x1u /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
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255 | #define ADC_WINCTRL_WINMODE_MODE2_Val 0x2u /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
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256 | #define ADC_WINCTRL_WINMODE_MODE3_Val 0x3u /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
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257 | #define ADC_WINCTRL_WINMODE_MODE4_Val 0x4u /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
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258 | #define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
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259 | #define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
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260 | #define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
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261 | #define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
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262 | #define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
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263 | #define ADC_WINCTRL_MASK 0x07u /**< \brief (ADC_WINCTRL) MASK Register */
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264 |
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265 | /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
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266 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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267 | typedef union {
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268 | struct {
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269 | uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
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270 | uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
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271 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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272 | } bit; /*!< Structure used for bit access */
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273 | uint8_t reg; /*!< Type used for register access */
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274 | } ADC_SWTRIG_Type;
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275 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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276 |
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277 | #define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
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278 | #define ADC_SWTRIG_RESETVALUE 0x00 /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
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279 |
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280 | #define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
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281 | #define ADC_SWTRIG_FLUSH (0x1u << ADC_SWTRIG_FLUSH_Pos)
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282 | #define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
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283 | #define ADC_SWTRIG_START (0x1u << ADC_SWTRIG_START_Pos)
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284 | #define ADC_SWTRIG_MASK 0x03u /**< \brief (ADC_SWTRIG) MASK Register */
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285 |
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286 | /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
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287 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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288 | typedef union {
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289 | struct {
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290 | uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
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291 | uint32_t :3; /*!< bit: 5.. 7 Reserved */
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292 | uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
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293 | uint32_t :3; /*!< bit: 13..15 Reserved */
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294 | uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
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295 | uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
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296 | uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
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297 | uint32_t :4; /*!< bit: 28..31 Reserved */
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298 | } bit; /*!< Structure used for bit access */
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299 | uint32_t reg; /*!< Type used for register access */
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300 | } ADC_INPUTCTRL_Type;
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301 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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302 |
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303 | #define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
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304 | #define ADC_INPUTCTRL_RESETVALUE 0x00000000 /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
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305 |
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306 | #define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
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307 | #define ADC_INPUTCTRL_MUXPOS_Msk (0x1Fu << ADC_INPUTCTRL_MUXPOS_Pos)
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308 | #define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))
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309 | #define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0u /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
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310 | #define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1u /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
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311 | #define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2u /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
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312 | #define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3u /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
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313 | #define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4u /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
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314 | #define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5u /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
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315 | #define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6u /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
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316 | #define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7u /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
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317 | #define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8u /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
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318 | #define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9u /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
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319 | #define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAu /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
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320 | #define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBu /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
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321 | #define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCu /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
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322 | #define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDu /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
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323 | #define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEu /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
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324 | #define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFu /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
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325 | #define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10u /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
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326 | #define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11u /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
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327 | #define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12u /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
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328 | #define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13u /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
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329 | #define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18u /**< \brief (ADC_INPUTCTRL) Temperature Reference */
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330 | #define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19u /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
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331 | #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Au /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
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332 | #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bu /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
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333 | #define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cu /**< \brief (ADC_INPUTCTRL) DAC Output */
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334 | #define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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335 | #define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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336 | #define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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337 | #define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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338 | #define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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339 | #define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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340 | #define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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341 | #define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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342 | #define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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343 | #define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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344 | #define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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345 | #define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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346 | #define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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347 | #define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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348 | #define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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349 | #define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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350 | #define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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351 | #define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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352 | #define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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353 | #define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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354 | #define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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355 | #define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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356 | #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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357 | #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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358 | #define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
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359 | #define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
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360 | #define ADC_INPUTCTRL_MUXNEG_Msk (0x1Fu << ADC_INPUTCTRL_MUXNEG_Pos)
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361 | #define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))
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362 | #define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0u /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
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363 | #define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1u /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
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364 | #define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2u /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
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365 | #define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3u /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
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366 | #define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4u /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
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367 | #define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5u /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
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368 | #define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6u /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
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369 | #define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7u /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
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370 | #define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18u /**< \brief (ADC_INPUTCTRL) Internal Ground */
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371 | #define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19u /**< \brief (ADC_INPUTCTRL) I/O Ground */
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372 | #define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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373 | #define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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374 | #define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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375 | #define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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376 | #define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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377 | #define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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378 | #define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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379 | #define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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380 | #define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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381 | #define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
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382 | #define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
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383 | #define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFu << ADC_INPUTCTRL_INPUTSCAN_Pos)
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384 | #define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
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385 | #define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
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386 | #define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFu << ADC_INPUTCTRL_INPUTOFFSET_Pos)
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387 | #define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
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388 | #define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
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389 | #define ADC_INPUTCTRL_GAIN_Msk (0xFu << ADC_INPUTCTRL_GAIN_Pos)
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390 | #define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))
|
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391 | #define ADC_INPUTCTRL_GAIN_1X_Val 0x0u /**< \brief (ADC_INPUTCTRL) 1x */
|
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392 | #define ADC_INPUTCTRL_GAIN_2X_Val 0x1u /**< \brief (ADC_INPUTCTRL) 2x */
|
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393 | #define ADC_INPUTCTRL_GAIN_4X_Val 0x2u /**< \brief (ADC_INPUTCTRL) 4x */
|
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394 | #define ADC_INPUTCTRL_GAIN_8X_Val 0x3u /**< \brief (ADC_INPUTCTRL) 8x */
|
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395 | #define ADC_INPUTCTRL_GAIN_16X_Val 0x4u /**< \brief (ADC_INPUTCTRL) 16x */
|
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396 | #define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFu /**< \brief (ADC_INPUTCTRL) 1/2x */
|
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397 | #define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
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398 | #define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
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399 | #define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
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400 | #define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
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401 | #define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
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402 | #define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
|
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403 | #define ADC_INPUTCTRL_MASK 0x0FFF1F1Fu /**< \brief (ADC_INPUTCTRL) MASK Register */
|
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404 |
|
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405 | /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
|
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406 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
407 | typedef union {
|
---|
408 | struct {
|
---|
409 | uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
|
---|
410 | uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
|
---|
411 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
---|
412 | uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
|
---|
413 | uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
|
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414 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
415 | } bit; /*!< Structure used for bit access */
|
---|
416 | uint8_t reg; /*!< Type used for register access */
|
---|
417 | } ADC_EVCTRL_Type;
|
---|
418 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
419 |
|
---|
420 | #define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
|
---|
421 | #define ADC_EVCTRL_RESETVALUE 0x00 /**< \brief (ADC_EVCTRL reset_value) Event Control */
|
---|
422 |
|
---|
423 | #define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
|
---|
424 | #define ADC_EVCTRL_STARTEI (0x1u << ADC_EVCTRL_STARTEI_Pos)
|
---|
425 | #define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
|
---|
426 | #define ADC_EVCTRL_SYNCEI (0x1u << ADC_EVCTRL_SYNCEI_Pos)
|
---|
427 | #define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
|
---|
428 | #define ADC_EVCTRL_RESRDYEO (0x1u << ADC_EVCTRL_RESRDYEO_Pos)
|
---|
429 | #define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
|
---|
430 | #define ADC_EVCTRL_WINMONEO (0x1u << ADC_EVCTRL_WINMONEO_Pos)
|
---|
431 | #define ADC_EVCTRL_MASK 0x33u /**< \brief (ADC_EVCTRL) MASK Register */
|
---|
432 |
|
---|
433 | /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
|
---|
434 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
435 | typedef union {
|
---|
436 | struct {
|
---|
437 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
|
---|
438 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
|
---|
439 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
|
---|
440 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
|
---|
441 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
---|
442 | } bit; /*!< Structure used for bit access */
|
---|
443 | uint8_t reg; /*!< Type used for register access */
|
---|
444 | } ADC_INTENCLR_Type;
|
---|
445 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
446 |
|
---|
447 | #define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
|
---|
448 | #define ADC_INTENCLR_RESETVALUE 0x00 /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
|
---|
449 |
|
---|
450 | #define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
|
---|
451 | #define ADC_INTENCLR_RESRDY (0x1u << ADC_INTENCLR_RESRDY_Pos)
|
---|
452 | #define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
|
---|
453 | #define ADC_INTENCLR_OVERRUN (0x1u << ADC_INTENCLR_OVERRUN_Pos)
|
---|
454 | #define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
|
---|
455 | #define ADC_INTENCLR_WINMON (0x1u << ADC_INTENCLR_WINMON_Pos)
|
---|
456 | #define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
|
---|
457 | #define ADC_INTENCLR_SYNCRDY (0x1u << ADC_INTENCLR_SYNCRDY_Pos)
|
---|
458 | #define ADC_INTENCLR_MASK 0x0Fu /**< \brief (ADC_INTENCLR) MASK Register */
|
---|
459 |
|
---|
460 | /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
|
---|
461 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
462 | typedef union {
|
---|
463 | struct {
|
---|
464 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
|
---|
465 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
|
---|
466 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
|
---|
467 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
|
---|
468 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
---|
469 | } bit; /*!< Structure used for bit access */
|
---|
470 | uint8_t reg; /*!< Type used for register access */
|
---|
471 | } ADC_INTENSET_Type;
|
---|
472 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
473 |
|
---|
474 | #define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
|
---|
475 | #define ADC_INTENSET_RESETVALUE 0x00 /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
|
---|
476 |
|
---|
477 | #define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
|
---|
478 | #define ADC_INTENSET_RESRDY (0x1u << ADC_INTENSET_RESRDY_Pos)
|
---|
479 | #define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
|
---|
480 | #define ADC_INTENSET_OVERRUN (0x1u << ADC_INTENSET_OVERRUN_Pos)
|
---|
481 | #define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
|
---|
482 | #define ADC_INTENSET_WINMON (0x1u << ADC_INTENSET_WINMON_Pos)
|
---|
483 | #define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
|
---|
484 | #define ADC_INTENSET_SYNCRDY (0x1u << ADC_INTENSET_SYNCRDY_Pos)
|
---|
485 | #define ADC_INTENSET_MASK 0x0Fu /**< \brief (ADC_INTENSET) MASK Register */
|
---|
486 |
|
---|
487 | /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
|
---|
488 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
489 | typedef union {
|
---|
490 | struct {
|
---|
491 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
|
---|
492 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
|
---|
493 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
|
---|
494 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
---|
495 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
---|
496 | } bit; /*!< Structure used for bit access */
|
---|
497 | uint8_t reg; /*!< Type used for register access */
|
---|
498 | } ADC_INTFLAG_Type;
|
---|
499 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
500 |
|
---|
501 | #define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
|
---|
502 | #define ADC_INTFLAG_RESETVALUE 0x00 /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
---|
503 |
|
---|
504 | #define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
|
---|
505 | #define ADC_INTFLAG_RESRDY (0x1u << ADC_INTFLAG_RESRDY_Pos)
|
---|
506 | #define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
|
---|
507 | #define ADC_INTFLAG_OVERRUN (0x1u << ADC_INTFLAG_OVERRUN_Pos)
|
---|
508 | #define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
|
---|
509 | #define ADC_INTFLAG_WINMON (0x1u << ADC_INTFLAG_WINMON_Pos)
|
---|
510 | #define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
|
---|
511 | #define ADC_INTFLAG_SYNCRDY (0x1u << ADC_INTFLAG_SYNCRDY_Pos)
|
---|
512 | #define ADC_INTFLAG_MASK 0x0Fu /**< \brief (ADC_INTFLAG) MASK Register */
|
---|
513 |
|
---|
514 | /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
|
---|
515 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
516 | typedef union {
|
---|
517 | struct {
|
---|
518 | uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
---|
519 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
|
---|
520 | } bit; /*!< Structure used for bit access */
|
---|
521 | uint8_t reg; /*!< Type used for register access */
|
---|
522 | } ADC_STATUS_Type;
|
---|
523 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
524 |
|
---|
525 | #define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
|
---|
526 | #define ADC_STATUS_RESETVALUE 0x00 /**< \brief (ADC_STATUS reset_value) Status */
|
---|
527 |
|
---|
528 | #define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
|
---|
529 | #define ADC_STATUS_SYNCBUSY (0x1u << ADC_STATUS_SYNCBUSY_Pos)
|
---|
530 | #define ADC_STATUS_MASK 0x80u /**< \brief (ADC_STATUS) MASK Register */
|
---|
531 |
|
---|
532 | /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
|
---|
533 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
534 | typedef union {
|
---|
535 | struct {
|
---|
536 | uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
|
---|
537 | } bit; /*!< Structure used for bit access */
|
---|
538 | uint16_t reg; /*!< Type used for register access */
|
---|
539 | } ADC_RESULT_Type;
|
---|
540 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
541 |
|
---|
542 | #define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
|
---|
543 | #define ADC_RESULT_RESETVALUE 0x0000 /**< \brief (ADC_RESULT reset_value) Result */
|
---|
544 |
|
---|
545 | #define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
|
---|
546 | #define ADC_RESULT_RESULT_Msk (0xFFFFu << ADC_RESULT_RESULT_Pos)
|
---|
547 | #define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))
|
---|
548 | #define ADC_RESULT_MASK 0xFFFFu /**< \brief (ADC_RESULT) MASK Register */
|
---|
549 |
|
---|
550 | /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
|
---|
551 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
552 | typedef union {
|
---|
553 | struct {
|
---|
554 | uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
|
---|
555 | } bit; /*!< Structure used for bit access */
|
---|
556 | uint16_t reg; /*!< Type used for register access */
|
---|
557 | } ADC_WINLT_Type;
|
---|
558 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
559 |
|
---|
560 | #define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
|
---|
561 | #define ADC_WINLT_RESETVALUE 0x0000 /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
|
---|
562 |
|
---|
563 | #define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
|
---|
564 | #define ADC_WINLT_WINLT_Msk (0xFFFFu << ADC_WINLT_WINLT_Pos)
|
---|
565 | #define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))
|
---|
566 | #define ADC_WINLT_MASK 0xFFFFu /**< \brief (ADC_WINLT) MASK Register */
|
---|
567 |
|
---|
568 | /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
|
---|
569 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
570 | typedef union {
|
---|
571 | struct {
|
---|
572 | uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
|
---|
573 | } bit; /*!< Structure used for bit access */
|
---|
574 | uint16_t reg; /*!< Type used for register access */
|
---|
575 | } ADC_WINUT_Type;
|
---|
576 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
577 |
|
---|
578 | #define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
|
---|
579 | #define ADC_WINUT_RESETVALUE 0x0000 /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
|
---|
580 |
|
---|
581 | #define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
|
---|
582 | #define ADC_WINUT_WINUT_Msk (0xFFFFu << ADC_WINUT_WINUT_Pos)
|
---|
583 | #define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))
|
---|
584 | #define ADC_WINUT_MASK 0xFFFFu /**< \brief (ADC_WINUT) MASK Register */
|
---|
585 |
|
---|
586 | /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
|
---|
587 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
588 | typedef union {
|
---|
589 | struct {
|
---|
590 | uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
|
---|
591 | uint16_t :4; /*!< bit: 12..15 Reserved */
|
---|
592 | } bit; /*!< Structure used for bit access */
|
---|
593 | uint16_t reg; /*!< Type used for register access */
|
---|
594 | } ADC_GAINCORR_Type;
|
---|
595 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
596 |
|
---|
597 | #define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
|
---|
598 | #define ADC_GAINCORR_RESETVALUE 0x0000 /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
|
---|
599 |
|
---|
600 | #define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
|
---|
601 | #define ADC_GAINCORR_GAINCORR_Msk (0xFFFu << ADC_GAINCORR_GAINCORR_Pos)
|
---|
602 | #define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))
|
---|
603 | #define ADC_GAINCORR_MASK 0x0FFFu /**< \brief (ADC_GAINCORR) MASK Register */
|
---|
604 |
|
---|
605 | /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
|
---|
606 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
607 | typedef union {
|
---|
608 | struct {
|
---|
609 | uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
|
---|
610 | uint16_t :4; /*!< bit: 12..15 Reserved */
|
---|
611 | } bit; /*!< Structure used for bit access */
|
---|
612 | uint16_t reg; /*!< Type used for register access */
|
---|
613 | } ADC_OFFSETCORR_Type;
|
---|
614 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
615 |
|
---|
616 | #define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
|
---|
617 | #define ADC_OFFSETCORR_RESETVALUE 0x0000 /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
|
---|
618 |
|
---|
619 | #define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
|
---|
620 | #define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFu << ADC_OFFSETCORR_OFFSETCORR_Pos)
|
---|
621 | #define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))
|
---|
622 | #define ADC_OFFSETCORR_MASK 0x0FFFu /**< \brief (ADC_OFFSETCORR) MASK Register */
|
---|
623 |
|
---|
624 | /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
|
---|
625 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
626 | typedef union {
|
---|
627 | struct {
|
---|
628 | uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
|
---|
629 | uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
|
---|
630 | uint16_t :5; /*!< bit: 11..15 Reserved */
|
---|
631 | } bit; /*!< Structure used for bit access */
|
---|
632 | uint16_t reg; /*!< Type used for register access */
|
---|
633 | } ADC_CALIB_Type;
|
---|
634 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
635 |
|
---|
636 | #define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
|
---|
637 | #define ADC_CALIB_RESETVALUE 0x0000 /**< \brief (ADC_CALIB reset_value) Calibration */
|
---|
638 |
|
---|
639 | #define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
|
---|
640 | #define ADC_CALIB_LINEARITY_CAL_Msk (0xFFu << ADC_CALIB_LINEARITY_CAL_Pos)
|
---|
641 | #define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))
|
---|
642 | #define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
|
---|
643 | #define ADC_CALIB_BIAS_CAL_Msk (0x7u << ADC_CALIB_BIAS_CAL_Pos)
|
---|
644 | #define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))
|
---|
645 | #define ADC_CALIB_MASK 0x07FFu /**< \brief (ADC_CALIB) MASK Register */
|
---|
646 |
|
---|
647 | /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
|
---|
648 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
649 | typedef union {
|
---|
650 | struct {
|
---|
651 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
|
---|
652 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
653 | } bit; /*!< Structure used for bit access */
|
---|
654 | uint8_t reg; /*!< Type used for register access */
|
---|
655 | } ADC_DBGCTRL_Type;
|
---|
656 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
657 |
|
---|
658 | #define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
|
---|
659 | #define ADC_DBGCTRL_RESETVALUE 0x00 /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
|
---|
660 |
|
---|
661 | #define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
|
---|
662 | #define ADC_DBGCTRL_DBGRUN (0x1u << ADC_DBGCTRL_DBGRUN_Pos)
|
---|
663 | #define ADC_DBGCTRL_MASK 0x01u /**< \brief (ADC_DBGCTRL) MASK Register */
|
---|
664 |
|
---|
665 | /** \brief ADC hardware registers */
|
---|
666 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
667 | typedef struct {
|
---|
668 | __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
|
---|
669 | __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
|
---|
670 | __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
|
---|
671 | __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
|
---|
672 | __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
|
---|
673 | RoReg8 Reserved1[0x2];
|
---|
674 | __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
|
---|
675 | RoReg8 Reserved2[0x3];
|
---|
676 | __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
|
---|
677 | RoReg8 Reserved3[0x3];
|
---|
678 | __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
|
---|
679 | __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
|
---|
680 | RoReg8 Reserved4[0x1];
|
---|
681 | __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
|
---|
682 | __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
|
---|
683 | __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
|
---|
684 | __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
|
---|
685 | __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
|
---|
686 | __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
|
---|
687 | RoReg8 Reserved5[0x2];
|
---|
688 | __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
|
---|
689 | RoReg8 Reserved6[0x2];
|
---|
690 | __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
|
---|
691 | __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
|
---|
692 | __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
|
---|
693 | __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
|
---|
694 | } Adc;
|
---|
695 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
696 |
|
---|
697 | /*@}*/
|
---|
698 |
|
---|
699 | #endif /* _SAMD21_ADC_COMPONENT_ */
|
---|