source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/CMSIS/Include/core_sc000.h@ 136

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1/**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V3.30
5 * @date 24. February 2014
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2014 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_SC000_H_GENERIC
43#define __CORE_SC000_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup SC000
67 @{
68 */
69
70/* CMSIS SC000 definitions */
71#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_SC (000) /*!< Cortex secure core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ ) /* Cosmic */
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
112*/
113#define __FPU_USED 0
114
115#if defined ( __CC_ARM )
116 #if defined __TARGET_FPU_VFP
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120#elif defined ( __GNUC__ )
121 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124
125#elif defined ( __ICCARM__ )
126 #if defined __ARMVFP__
127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #endif
129
130#elif defined ( __TMS470__ )
131 #if defined __TI__VFP_SUPPORT____
132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
133 #endif
134
135#elif defined ( __TASKING__ )
136 #if defined __FPU_VFP__
137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
138 #endif
139
140#elif defined ( __CSMC__ ) /* Cosmic */
141 #if ( __CSMC__ & 0x400) // FPU present for parser
142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
143 #endif
144#endif
145
146#include <stdint.h> /* standard types definitions */
147#include <core_cmInstr.h> /* Core Instruction Access */
148#include <core_cmFunc.h> /* Core Function Access */
149
150#endif /* __CORE_SC000_H_GENERIC */
151
152#ifndef __CMSIS_GENERIC
153
154#ifndef __CORE_SC000_H_DEPENDANT
155#define __CORE_SC000_H_DEPENDANT
156
157/* check device defines and use defaults */
158#if defined __CHECK_DEVICE_DEFINES
159 #ifndef __SC000_REV
160 #define __SC000_REV 0x0000
161 #warning "__SC000_REV not defined in device header file; using default!"
162 #endif
163
164 #ifndef __MPU_PRESENT
165 #define __MPU_PRESENT 0
166 #warning "__MPU_PRESENT not defined in device header file; using default!"
167 #endif
168
169 #ifndef __NVIC_PRIO_BITS
170 #define __NVIC_PRIO_BITS 2
171 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
172 #endif
173
174 #ifndef __Vendor_SysTickConfig
175 #define __Vendor_SysTickConfig 0
176 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
177 #endif
178#endif
179
180/* IO definitions (access restrictions to peripheral registers) */
181/**
182 \defgroup CMSIS_glob_defs CMSIS Global Defines
183
184 <strong>IO Type Qualifiers</strong> are used
185 \li to specify the access to peripheral variables.
186 \li for automatic generation of peripheral register debug information.
187*/
188#ifdef __cplusplus
189 #define __I volatile /*!< Defines 'read only' permissions */
190#else
191 #define __I volatile const /*!< Defines 'read only' permissions */
192#endif
193#define __O volatile /*!< Defines 'write only' permissions */
194#define __IO volatile /*!< Defines 'read / write' permissions */
195
196/*@} end of group SC000 */
197
198
199
200/*******************************************************************************
201 * Register Abstraction
202 Core Register contain:
203 - Core Register
204 - Core NVIC Register
205 - Core SCB Register
206 - Core SysTick Register
207 - Core MPU Register
208 ******************************************************************************/
209/** \defgroup CMSIS_core_register Defines and Type Definitions
210 \brief Type definitions and defines for Cortex-M processor based devices.
211*/
212
213/** \ingroup CMSIS_core_register
214 \defgroup CMSIS_CORE Status and Control Registers
215 \brief Core Register type definitions.
216 @{
217 */
218
219/** \brief Union type to access the Application Program Status Register (APSR).
220 */
221typedef union
222{
223 struct
224 {
225#if (__CORTEX_M != 0x04)
226 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
227#else
228 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
229 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
230 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
231#endif
232 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
233 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
234 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
235 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
236 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
237 } b; /*!< Structure used for bit access */
238 uint32_t w; /*!< Type used for word access */
239} APSR_Type;
240
241
242/** \brief Union type to access the Interrupt Program Status Register (IPSR).
243 */
244typedef union
245{
246 struct
247 {
248 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
249 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
250 } b; /*!< Structure used for bit access */
251 uint32_t w; /*!< Type used for word access */
252} IPSR_Type;
253
254
255/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
256 */
257typedef union
258{
259 struct
260 {
261 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
262#if (__CORTEX_M != 0x04)
263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
264#else
265 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
266 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
267 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
268#endif
269 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
270 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
271 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
272 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
273 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
274 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
275 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
276 } b; /*!< Structure used for bit access */
277 uint32_t w; /*!< Type used for word access */
278} xPSR_Type;
279
280
281/** \brief Union type to access the Control Registers (CONTROL).
282 */
283typedef union
284{
285 struct
286 {
287 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
288 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
289 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
290 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
291 } b; /*!< Structure used for bit access */
292 uint32_t w; /*!< Type used for word access */
293} CONTROL_Type;
294
295/*@} end of group CMSIS_CORE */
296
297
298/** \ingroup CMSIS_core_register
299 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
300 \brief Type definitions for the NVIC Registers
301 @{
302 */
303
304/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
305 */
306typedef struct
307{
308 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
309 uint32_t RESERVED0[31];
310 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
311 uint32_t RSERVED1[31];
312 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
313 uint32_t RESERVED2[31];
314 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
315 uint32_t RESERVED3[31];
316 uint32_t RESERVED4[64];
317 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
318} NVIC_Type;
319
320/*@} end of group CMSIS_NVIC */
321
322
323/** \ingroup CMSIS_core_register
324 \defgroup CMSIS_SCB System Control Block (SCB)
325 \brief Type definitions for the System Control Block Registers
326 @{
327 */
328
329/** \brief Structure type to access the System Control Block (SCB).
330 */
331typedef struct
332{
333 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
334 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
335 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
336 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
337 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
338 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
339 uint32_t RESERVED0[1];
340 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
341 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
342 uint32_t RESERVED1[154];
343 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
344} SCB_Type;
345
346/* SCB CPUID Register Definitions */
347#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
348#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
349
350#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
351#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
352
353#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
354#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
355
356#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
357#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
358
359#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
360#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
361
362/* SCB Interrupt Control State Register Definitions */
363#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
364#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
365
366#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
367#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
368
369#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
370#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
371
372#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
373#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
374
375#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
376#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
377
378#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
379#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
380
381#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
382#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
383
384#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
385#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
386
387#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
388#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
389
390/* SCB Interrupt Control State Register Definitions */
391#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
392#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
393
394/* SCB Application Interrupt and Reset Control Register Definitions */
395#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
396#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
397
398#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
399#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
400
401#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
402#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
403
404#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
405#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
406
407#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
408#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
409
410/* SCB System Control Register Definitions */
411#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
412#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
413
414#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
415#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
416
417#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
418#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
419
420/* SCB Configuration Control Register Definitions */
421#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
422#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
423
424#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
425#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
426
427/* SCB System Handler Control and State Register Definitions */
428#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
429#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
430
431/* SCB Security Features Register Definitions */
432#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
433#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
434
435#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
436#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
437
438/*@} end of group CMSIS_SCB */
439
440
441/** \ingroup CMSIS_core_register
442 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
443 \brief Type definitions for the System Control and ID Register not in the SCB
444 @{
445 */
446
447/** \brief Structure type to access the System Control and ID Register not in the SCB.
448 */
449typedef struct
450{
451 uint32_t RESERVED0[2];
452 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
453} SCnSCB_Type;
454
455/* Auxiliary Control Register Definitions */
456#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
457#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
458
459/*@} end of group CMSIS_SCnotSCB */
460
461
462/** \ingroup CMSIS_core_register
463 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
464 \brief Type definitions for the System Timer Registers.
465 @{
466 */
467
468/** \brief Structure type to access the System Timer (SysTick).
469 */
470typedef struct
471{
472 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
473 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
474 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
475 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
476} SysTick_Type;
477
478/* SysTick Control / Status Register Definitions */
479#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
480#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
481
482#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
483#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
484
485#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
486#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
487
488#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
489#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
490
491/* SysTick Reload Register Definitions */
492#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
493#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
494
495/* SysTick Current Register Definitions */
496#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
497#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
498
499/* SysTick Calibration Register Definitions */
500#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
501#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
502
503#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
504#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
505
506#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
507#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
508
509/*@} end of group CMSIS_SysTick */
510
511#if (__MPU_PRESENT == 1)
512/** \ingroup CMSIS_core_register
513 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
514 \brief Type definitions for the Memory Protection Unit (MPU)
515 @{
516 */
517
518/** \brief Structure type to access the Memory Protection Unit (MPU).
519 */
520typedef struct
521{
522 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
523 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
524 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
525 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
526 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
527} MPU_Type;
528
529/* MPU Type Register */
530#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
531#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
532
533#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
534#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
535
536#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
537#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
538
539/* MPU Control Register */
540#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
541#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
542
543#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
544#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
545
546#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
547#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
548
549/* MPU Region Number Register */
550#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
551#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
552
553/* MPU Region Base Address Register */
554#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
555#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
556
557#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
558#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
559
560#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
561#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
562
563/* MPU Region Attribute and Size Register */
564#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
565#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
566
567#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
568#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
569
570#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
571#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
572
573#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
574#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
575
576#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
577#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
578
579#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
580#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
581
582#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
583#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
584
585#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
586#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
587
588#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
589#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
590
591#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
592#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
593
594/*@} end of group CMSIS_MPU */
595#endif
596
597
598/** \ingroup CMSIS_core_register
599 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
600 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
601 are only accessible over DAP and not via processor. Therefore
602 they are not covered by the Cortex-M0 header file.
603 @{
604 */
605/*@} end of group CMSIS_CoreDebug */
606
607
608/** \ingroup CMSIS_core_register
609 \defgroup CMSIS_core_base Core Definitions
610 \brief Definitions for base addresses, unions, and structures.
611 @{
612 */
613
614/* Memory mapping of SC000 Hardware */
615#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
616#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
617#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
618#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
619
620#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
621#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
622#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
623#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
624
625#if (__MPU_PRESENT == 1)
626 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
627 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
628#endif
629
630/*@} */
631
632
633
634/*******************************************************************************
635 * Hardware Abstraction Layer
636 Core Function Interface contains:
637 - Core NVIC Functions
638 - Core SysTick Functions
639 - Core Register Access Functions
640 ******************************************************************************/
641/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
642*/
643
644
645
646/* ########################## NVIC functions #################################### */
647/** \ingroup CMSIS_Core_FunctionInterface
648 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
649 \brief Functions that manage interrupts and exceptions via the NVIC.
650 @{
651 */
652
653/* Interrupt Priorities are WORD accessible only under ARMv6M */
654/* The following MACROS handle generation of the register offset and byte masks */
655#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
656#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
657#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
658
659
660/** \brief Enable External Interrupt
661
662 The function enables a device-specific interrupt in the NVIC interrupt controller.
663
664 \param [in] IRQn External interrupt number. Value cannot be negative.
665 */
666__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
667{
668 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
669}
670
671
672/** \brief Disable External Interrupt
673
674 The function disables a device-specific interrupt in the NVIC interrupt controller.
675
676 \param [in] IRQn External interrupt number. Value cannot be negative.
677 */
678__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
679{
680 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
681}
682
683
684/** \brief Get Pending Interrupt
685
686 The function reads the pending register in the NVIC and returns the pending bit
687 for the specified interrupt.
688
689 \param [in] IRQn Interrupt number.
690
691 \return 0 Interrupt status is not pending.
692 \return 1 Interrupt status is pending.
693 */
694__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
695{
696 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
697}
698
699
700/** \brief Set Pending Interrupt
701
702 The function sets the pending bit of an external interrupt.
703
704 \param [in] IRQn Interrupt number. Value cannot be negative.
705 */
706__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
707{
708 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
709}
710
711
712/** \brief Clear Pending Interrupt
713
714 The function clears the pending bit of an external interrupt.
715
716 \param [in] IRQn External interrupt number. Value cannot be negative.
717 */
718__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
719{
720 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
721}
722
723
724/** \brief Set Interrupt Priority
725
726 The function sets the priority of an interrupt.
727
728 \note The priority cannot be set for every core interrupt.
729
730 \param [in] IRQn Interrupt number.
731 \param [in] priority Priority to set.
732 */
733__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
734{
735 if(IRQn < 0) {
736 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
737 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
738 else {
739 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
740 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
741}
742
743
744/** \brief Get Interrupt Priority
745
746 The function reads the priority of an interrupt. The interrupt
747 number can be positive to specify an external (device specific)
748 interrupt, or negative to specify an internal (core) interrupt.
749
750
751 \param [in] IRQn Interrupt number.
752 \return Interrupt Priority. Value is aligned automatically to the implemented
753 priority bits of the microcontroller.
754 */
755__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
756{
757
758 if(IRQn < 0) {
759 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
760 else {
761 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
762}
763
764
765/** \brief System Reset
766
767 The function initiates a system reset request to reset the MCU.
768 */
769__STATIC_INLINE void NVIC_SystemReset(void)
770{
771 __DSB(); /* Ensure all outstanding memory accesses included
772 buffered write are completed before reset */
773 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
774 SCB_AIRCR_SYSRESETREQ_Msk);
775 __DSB(); /* Ensure completion of memory access */
776 while(1); /* wait until reset */
777}
778
779/*@} end of CMSIS_Core_NVICFunctions */
780
781
782
783/* ################################## SysTick function ############################################ */
784/** \ingroup CMSIS_Core_FunctionInterface
785 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
786 \brief Functions that configure the System.
787 @{
788 */
789
790#if (__Vendor_SysTickConfig == 0)
791
792/** \brief System Tick Configuration
793
794 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
795 Counter is in free running mode to generate periodic interrupts.
796
797 \param [in] ticks Number of ticks between two interrupts.
798
799 \return 0 Function succeeded.
800 \return 1 Function failed.
801
802 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
803 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
804 must contain a vendor-specific implementation of this function.
805
806 */
807__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
808{
809 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
810
811 SysTick->LOAD = ticks - 1; /* set reload register */
812 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
813 SysTick->VAL = 0; /* Load the SysTick Counter Value */
814 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
815 SysTick_CTRL_TICKINT_Msk |
816 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
817 return (0); /* Function successful */
818}
819
820#endif
821
822/*@} end of CMSIS_Core_SysTickFunctions */
823
824
825
826
827#endif /* __CORE_SC000_H_DEPENDANT */
828
829#ifdef __cplusplus
830}
831#endif
832
833#endif /* __CMSIS_GENERIC */
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