source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/CMSIS/Include/core_cm4.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

ライブラリとOS及びベーシックなサンプルの追加．
File size: 105.6 KB
Line 
1/**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V3.30
5 * @date 24. February 2014
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2014 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_CM4_H_GENERIC
43#define __CORE_CM4_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex_M4
67 @{
68 */
69
70/* CMSIS CM4 definitions */
71#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x04) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ ) /* Cosmic */
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
112*/
113#if defined ( __CC_ARM )
114 #if defined __TARGET_FPU_VFP
115 #if (__FPU_PRESENT == 1)
116 #define __FPU_USED 1
117 #else
118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119 #define __FPU_USED 0
120 #endif
121 #else
122 #define __FPU_USED 0
123 #endif
124
125#elif defined ( __GNUC__ )
126 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
127 #if (__FPU_PRESENT == 1)
128 #define __FPU_USED 1
129 #else
130 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
131 #define __FPU_USED 0
132 #endif
133 #else
134 #define __FPU_USED 0
135 #endif
136
137#elif defined ( __ICCARM__ )
138 #if defined __ARMVFP__
139 #if (__FPU_PRESENT == 1)
140 #define __FPU_USED 1
141 #else
142 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
143 #define __FPU_USED 0
144 #endif
145 #else
146 #define __FPU_USED 0
147 #endif
148
149#elif defined ( __TMS470__ )
150 #if defined __TI_VFP_SUPPORT__
151 #if (__FPU_PRESENT == 1)
152 #define __FPU_USED 1
153 #else
154 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
155 #define __FPU_USED 0
156 #endif
157 #else
158 #define __FPU_USED 0
159 #endif
160
161#elif defined ( __TASKING__ )
162 #if defined __FPU_VFP__
163 #if (__FPU_PRESENT == 1)
164 #define __FPU_USED 1
165 #else
166 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
167 #define __FPU_USED 0
168 #endif
169 #else
170 #define __FPU_USED 0
171 #endif
172
173#elif defined ( __CSMC__ ) /* Cosmic */
174 #if ( __CSMC__ & 0x400) // FPU present for parser
175 #if (__FPU_PRESENT == 1)
176 #define __FPU_USED 1
177 #else
178 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
179 #define __FPU_USED 0
180 #endif
181 #else
182 #define __FPU_USED 0
183 #endif
184#endif
185
186#include <stdint.h> /* standard types definitions */
187#include <core_cmInstr.h> /* Core Instruction Access */
188#include <core_cmFunc.h> /* Core Function Access */
189#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
190
191#endif /* __CORE_CM4_H_GENERIC */
192
193#ifndef __CMSIS_GENERIC
194
195#ifndef __CORE_CM4_H_DEPENDANT
196#define __CORE_CM4_H_DEPENDANT
197
198/* check device defines and use defaults */
199#if defined __CHECK_DEVICE_DEFINES
200 #ifndef __CM4_REV
201 #define __CM4_REV 0x0000
202 #warning "__CM4_REV not defined in device header file; using default!"
203 #endif
204
205 #ifndef __FPU_PRESENT
206 #define __FPU_PRESENT 0
207 #warning "__FPU_PRESENT not defined in device header file; using default!"
208 #endif
209
210 #ifndef __MPU_PRESENT
211 #define __MPU_PRESENT 0
212 #warning "__MPU_PRESENT not defined in device header file; using default!"
213 #endif
214
215 #ifndef __NVIC_PRIO_BITS
216 #define __NVIC_PRIO_BITS 4
217 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
218 #endif
219
220 #ifndef __Vendor_SysTickConfig
221 #define __Vendor_SysTickConfig 0
222 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
223 #endif
224#endif
225
226/* IO definitions (access restrictions to peripheral registers) */
227/**
228 \defgroup CMSIS_glob_defs CMSIS Global Defines
229
230 <strong>IO Type Qualifiers</strong> are used
231 \li to specify the access to peripheral variables.
232 \li for automatic generation of peripheral register debug information.
233*/
234#ifdef __cplusplus
235 #define __I volatile /*!< Defines 'read only' permissions */
236#else
237 #define __I volatile const /*!< Defines 'read only' permissions */
238#endif
239#define __O volatile /*!< Defines 'write only' permissions */
240#define __IO volatile /*!< Defines 'read / write' permissions */
241
242/*@} end of group Cortex_M4 */
243
244
245
246/*******************************************************************************
247 * Register Abstraction
248 Core Register contain:
249 - Core Register
250 - Core NVIC Register
251 - Core SCB Register
252 - Core SysTick Register
253 - Core Debug Register
254 - Core MPU Register
255 - Core FPU Register
256 ******************************************************************************/
257/** \defgroup CMSIS_core_register Defines and Type Definitions
258 \brief Type definitions and defines for Cortex-M processor based devices.
259*/
260
261/** \ingroup CMSIS_core_register
262 \defgroup CMSIS_CORE Status and Control Registers
263 \brief Core Register type definitions.
264 @{
265 */
266
267/** \brief Union type to access the Application Program Status Register (APSR).
268 */
269typedef union
270{
271 struct
272 {
273#if (__CORTEX_M != 0x04)
274 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
275#else
276 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
277 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
278 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
279#endif
280 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
281 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
282 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
283 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
284 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
285 } b; /*!< Structure used for bit access */
286 uint32_t w; /*!< Type used for word access */
287} APSR_Type;
288
289
290/** \brief Union type to access the Interrupt Program Status Register (IPSR).
291 */
292typedef union
293{
294 struct
295 {
296 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
297 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
298 } b; /*!< Structure used for bit access */
299 uint32_t w; /*!< Type used for word access */
300} IPSR_Type;
301
302
303/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
304 */
305typedef union
306{
307 struct
308 {
309 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
310#if (__CORTEX_M != 0x04)
311 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
312#else
313 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
314 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
315 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
316#endif
317 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
318 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
319 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
320 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
321 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
322 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
323 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
324 } b; /*!< Structure used for bit access */
325 uint32_t w; /*!< Type used for word access */
326} xPSR_Type;
327
328
329/** \brief Union type to access the Control Registers (CONTROL).
330 */
331typedef union
332{
333 struct
334 {
335 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
336 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
337 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
338 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
339 } b; /*!< Structure used for bit access */
340 uint32_t w; /*!< Type used for word access */
341} CONTROL_Type;
342
343/*@} end of group CMSIS_CORE */
344
345
346/** \ingroup CMSIS_core_register
347 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
348 \brief Type definitions for the NVIC Registers
349 @{
350 */
351
352/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
353 */
354typedef struct
355{
356 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
357 uint32_t RESERVED0[24];
358 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
359 uint32_t RSERVED1[24];
360 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
361 uint32_t RESERVED2[24];
362 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
363 uint32_t RESERVED3[24];
364 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
365 uint32_t RESERVED4[56];
366 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
367 uint32_t RESERVED5[644];
368 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
369} NVIC_Type;
370
371/* Software Triggered Interrupt Register Definitions */
372#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
373#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
374
375/*@} end of group CMSIS_NVIC */
376
377
378/** \ingroup CMSIS_core_register
379 \defgroup CMSIS_SCB System Control Block (SCB)
380 \brief Type definitions for the System Control Block Registers
381 @{
382 */
383
384/** \brief Structure type to access the System Control Block (SCB).
385 */
386typedef struct
387{
388 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
389 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
390 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
391 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
392 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
393 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
394 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
396 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
397 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
398 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
399 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
400 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
401 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
402 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
403 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
404 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
405 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
406 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
407 uint32_t RESERVED0[5];
408 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
409} SCB_Type;
410
411/* SCB CPUID Register Definitions */
412#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
413#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
414
415#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
416#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
417
418#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
419#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
420
421#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
422#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
423
424#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
425#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
426
427/* SCB Interrupt Control State Register Definitions */
428#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
429#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
430
431#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
432#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
433
434#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
435#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
436
437#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
438#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
439
440#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
441#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
442
443#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
444#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
445
446#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
447#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
448
449#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
450#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
451
452#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
453#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
454
455#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
456#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
457
458/* SCB Vector Table Offset Register Definitions */
459#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
460#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
461
462/* SCB Application Interrupt and Reset Control Register Definitions */
463#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
464#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
465
466#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
467#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
468
469#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
470#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
471
472#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
473#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
474
475#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
476#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
477
478#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
479#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
480
481#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
482#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
483
484/* SCB System Control Register Definitions */
485#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
486#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
487
488#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
489#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
490
491#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
492#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
493
494/* SCB Configuration Control Register Definitions */
495#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
496#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
497
498#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
499#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
500
501#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
502#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
503
504#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
505#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
506
507#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
508#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
509
510#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
511#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
512
513/* SCB System Handler Control and State Register Definitions */
514#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
515#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
516
517#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
518#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
519
520#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
521#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
522
523#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
524#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
525
526#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
527#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
528
529#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
530#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
531
532#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
533#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
534
535#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
536#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
537
538#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
539#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
540
541#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
542#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
543
544#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
545#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
546
547#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
548#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
549
550#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
551#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
552
553#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
554#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
555
556/* SCB Configurable Fault Status Registers Definitions */
557#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
558#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
559
560#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
561#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
562
563#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
564#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
565
566/* SCB Hard Fault Status Registers Definitions */
567#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
568#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
569
570#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
571#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
572
573#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
574#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
575
576/* SCB Debug Fault Status Register Definitions */
577#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
578#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
579
580#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
581#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
582
583#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
584#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
585
586#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
587#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
588
589#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
590#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
591
592/*@} end of group CMSIS_SCB */
593
594
595/** \ingroup CMSIS_core_register
596 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
597 \brief Type definitions for the System Control and ID Register not in the SCB
598 @{
599 */
600
601/** \brief Structure type to access the System Control and ID Register not in the SCB.
602 */
603typedef struct
604{
605 uint32_t RESERVED0[1];
606 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
607 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
608} SCnSCB_Type;
609
610/* Interrupt Controller Type Register Definitions */
611#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
612#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
613
614/* Auxiliary Control Register Definitions */
615#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
616#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
617
618#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
619#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
620
621#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
622#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
623
624#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
625#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
626
627#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
628#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
629
630/*@} end of group CMSIS_SCnotSCB */
631
632
633/** \ingroup CMSIS_core_register
634 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
635 \brief Type definitions for the System Timer Registers.
636 @{
637 */
638
639/** \brief Structure type to access the System Timer (SysTick).
640 */
641typedef struct
642{
643 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
644 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
645 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
646 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
647} SysTick_Type;
648
649/* SysTick Control / Status Register Definitions */
650#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
651#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
652
653#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
654#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
655
656#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
657#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
658
659#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
660#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
661
662/* SysTick Reload Register Definitions */
663#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
664#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
665
666/* SysTick Current Register Definitions */
667#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
668#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
669
670/* SysTick Calibration Register Definitions */
671#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
672#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
673
674#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
675#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
676
677#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
678#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
679
680/*@} end of group CMSIS_SysTick */
681
682
683/** \ingroup CMSIS_core_register
684 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
685 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
686 @{
687 */
688
689/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
690 */
691typedef struct
692{
693 __O union
694 {
695 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
696 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
697 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
698 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
699 uint32_t RESERVED0[864];
700 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
701 uint32_t RESERVED1[15];
702 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
703 uint32_t RESERVED2[15];
704 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
705 uint32_t RESERVED3[29];
706 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
707 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
708 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
709 uint32_t RESERVED4[43];
710 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
711 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
712 uint32_t RESERVED5[6];
713 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
714 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
715 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
716 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
717 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
718 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
719 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
720 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
721 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
722 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
723 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
724 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
725} ITM_Type;
726
727/* ITM Trace Privilege Register Definitions */
728#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
729#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
730
731/* ITM Trace Control Register Definitions */
732#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
733#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
734
735#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
736#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
737
738#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
739#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
740
741#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
742#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
743
744#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
745#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
746
747#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
748#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
749
750#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
751#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
752
753#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
754#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
755
756#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
757#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
758
759/* ITM Integration Write Register Definitions */
760#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
761#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
762
763/* ITM Integration Read Register Definitions */
764#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
765#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
766
767/* ITM Integration Mode Control Register Definitions */
768#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
769#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
770
771/* ITM Lock Status Register Definitions */
772#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
773#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
774
775#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
776#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
777
778#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
779#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
780
781/*@}*/ /* end of group CMSIS_ITM */
782
783
784/** \ingroup CMSIS_core_register
785 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
786 \brief Type definitions for the Data Watchpoint and Trace (DWT)
787 @{
788 */
789
790/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
791 */
792typedef struct
793{
794 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
795 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
796 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
797 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
798 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
799 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
800 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
801 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
802 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
803 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
804 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
805 uint32_t RESERVED0[1];
806 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
807 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
808 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
809 uint32_t RESERVED1[1];
810 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
811 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
812 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
813 uint32_t RESERVED2[1];
814 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
815 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
816 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
817} DWT_Type;
818
819/* DWT Control Register Definitions */
820#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
821#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
822
823#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
824#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
825
826#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
827#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
828
829#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
830#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
831
832#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
833#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
834
835#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
836#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
837
838#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
839#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
840
841#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
842#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
843
844#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
845#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
846
847#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
848#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
849
850#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
851#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
852
853#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
854#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
855
856#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
857#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
858
859#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
860#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
861
862#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
863#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
864
865#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
866#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
867
868#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
869#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
870
871#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
872#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
873
874/* DWT CPI Count Register Definitions */
875#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
876#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
877
878/* DWT Exception Overhead Count Register Definitions */
879#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
880#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
881
882/* DWT Sleep Count Register Definitions */
883#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
884#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
885
886/* DWT LSU Count Register Definitions */
887#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
888#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
889
890/* DWT Folded-instruction Count Register Definitions */
891#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
892#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
893
894/* DWT Comparator Mask Register Definitions */
895#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
896#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
897
898/* DWT Comparator Function Register Definitions */
899#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
900#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
901
902#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
903#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
904
905#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
906#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
907
908#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
909#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
910
911#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
912#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
913
914#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
915#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
916
917#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
918#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
919
920#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
921#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
922
923#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
924#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
925
926/*@}*/ /* end of group CMSIS_DWT */
927
928
929/** \ingroup CMSIS_core_register
930 \defgroup CMSIS_TPI Trace Port Interface (TPI)
931 \brief Type definitions for the Trace Port Interface (TPI)
932 @{
933 */
934
935/** \brief Structure type to access the Trace Port Interface Register (TPI).
936 */
937typedef struct
938{
939 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
940 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
941 uint32_t RESERVED0[2];
942 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
943 uint32_t RESERVED1[55];
944 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
945 uint32_t RESERVED2[131];
946 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
947 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
948 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
949 uint32_t RESERVED3[759];
950 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
951 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
952 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
953 uint32_t RESERVED4[1];
954 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
955 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
956 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
957 uint32_t RESERVED5[39];
958 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
959 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
960 uint32_t RESERVED7[8];
961 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
962 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
963} TPI_Type;
964
965/* TPI Asynchronous Clock Prescaler Register Definitions */
966#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
967#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
968
969/* TPI Selected Pin Protocol Register Definitions */
970#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
971#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
972
973/* TPI Formatter and Flush Status Register Definitions */
974#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
975#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
976
977#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
978#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
979
980#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
981#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
982
983#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
984#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
985
986/* TPI Formatter and Flush Control Register Definitions */
987#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
988#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
989
990#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
991#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
992
993/* TPI TRIGGER Register Definitions */
994#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
995#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
996
997/* TPI Integration ETM Data Register Definitions (FIFO0) */
998#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
999#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1000
1001#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
1002#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1003
1004#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
1005#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1006
1007#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
1008#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1009
1010#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
1011#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1012
1013#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
1014#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1015
1016#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
1017#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
1018
1019/* TPI ITATBCTR2 Register Definitions */
1020#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
1021#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
1022
1023/* TPI Integration ITM Data Register Definitions (FIFO1) */
1024#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
1025#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1026
1027#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
1028#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1029
1030#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
1031#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1032
1033#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
1034#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1035
1036#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
1037#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1038
1039#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
1040#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1041
1042#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
1043#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
1044
1045/* TPI ITATBCTR0 Register Definitions */
1046#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
1047#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
1048
1049/* TPI Integration Mode Control Register Definitions */
1050#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1051#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
1052
1053/* TPI DEVID Register Definitions */
1054#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1055#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1056
1057#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1058#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1059
1060#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1061#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1062
1063#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1064#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1065
1066#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1067#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1068
1069#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1070#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
1071
1072/* TPI DEVTYPE Register Definitions */
1073#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1074#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
1075
1076#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1077#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1078
1079/*@}*/ /* end of group CMSIS_TPI */
1080
1081
1082#if (__MPU_PRESENT == 1)
1083/** \ingroup CMSIS_core_register
1084 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1085 \brief Type definitions for the Memory Protection Unit (MPU)
1086 @{
1087 */
1088
1089/** \brief Structure type to access the Memory Protection Unit (MPU).
1090 */
1091typedef struct
1092{
1093 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1094 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1095 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1096 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1097 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1098 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1099 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1100 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1101 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1102 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1103 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1104} MPU_Type;
1105
1106/* MPU Type Register */
1107#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1108#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1109
1110#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1111#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1112
1113#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1114#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1115
1116/* MPU Control Register */
1117#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1118#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1119
1120#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1121#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1122
1123#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1124#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1125
1126/* MPU Region Number Register */
1127#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1128#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1129
1130/* MPU Region Base Address Register */
1131#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1132#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1133
1134#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1135#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1136
1137#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1138#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1139
1140/* MPU Region Attribute and Size Register */
1141#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1142#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1143
1144#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1145#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1146
1147#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1148#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1149
1150#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1151#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1152
1153#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1154#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1155
1156#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1157#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1158
1159#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1160#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1161
1162#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1163#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1164
1165#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1166#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1167
1168#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1169#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1170
1171/*@} end of group CMSIS_MPU */
1172#endif
1173
1174
1175#if (__FPU_PRESENT == 1)
1176/** \ingroup CMSIS_core_register
1177 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1178 \brief Type definitions for the Floating Point Unit (FPU)
1179 @{
1180 */
1181
1182/** \brief Structure type to access the Floating Point Unit (FPU).
1183 */
1184typedef struct
1185{
1186 uint32_t RESERVED0[1];
1187 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1188 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1189 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1190 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1191 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1192} FPU_Type;
1193
1194/* Floating-Point Context Control Register */
1195#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
1196#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1197
1198#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
1199#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1200
1201#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
1202#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1203
1204#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
1205#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1206
1207#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
1208#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1209
1210#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
1211#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1212
1213#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
1214#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1215
1216#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
1217#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1218
1219#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
1220#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
1221
1222/* Floating-Point Context Address Register */
1223#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
1224#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1225
1226/* Floating-Point Default Status Control Register */
1227#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
1228#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1229
1230#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
1231#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1232
1233#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
1234#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1235
1236#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
1237#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1238
1239/* Media and FP Feature Register 0 */
1240#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
1241#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1242
1243#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
1244#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1245
1246#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
1247#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1248
1249#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
1250#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1251
1252#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
1253#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1254
1255#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
1256#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1257
1258#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
1259#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1260
1261#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
1262#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
1263
1264/* Media and FP Feature Register 1 */
1265#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
1266#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1267
1268#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
1269#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1270
1271#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
1272#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1273
1274#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
1275#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
1276
1277/*@} end of group CMSIS_FPU */
1278#endif
1279
1280
1281/** \ingroup CMSIS_core_register
1282 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1283 \brief Type definitions for the Core Debug Registers
1284 @{
1285 */
1286
1287/** \brief Structure type to access the Core Debug Register (CoreDebug).
1288 */
1289typedef struct
1290{
1291 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1292 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1293 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1294 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1295} CoreDebug_Type;
1296
1297/* Debug Halting Control and Status Register */
1298#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1299#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1300
1301#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1302#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1303
1304#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1305#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1306
1307#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1308#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1309
1310#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1311#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1312
1313#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1314#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1315
1316#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1317#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1318
1319#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1320#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1321
1322#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1323#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1324
1325#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1326#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1327
1328#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1329#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1330
1331#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1332#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1333
1334/* Debug Core Register Selector Register */
1335#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1336#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1337
1338#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1339#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1340
1341/* Debug Exception and Monitor Control Register */
1342#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1343#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1344
1345#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1346#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1347
1348#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1349#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1350
1351#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1352#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1353
1354#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1355#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1356
1357#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1358#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1359
1360#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1361#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1362
1363#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1364#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1365
1366#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1367#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1368
1369#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1370#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1371
1372#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1373#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1374
1375#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1376#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1377
1378#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1379#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1380
1381/*@} end of group CMSIS_CoreDebug */
1382
1383
1384/** \ingroup CMSIS_core_register
1385 \defgroup CMSIS_core_base Core Definitions
1386 \brief Definitions for base addresses, unions, and structures.
1387 @{
1388 */
1389
1390/* Memory mapping of Cortex-M4 Hardware */
1391#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1392#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1393#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1394#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1395#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1396#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1397#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1398#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1399
1400#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1401#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1402#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1403#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1404#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1405#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1406#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1407#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1408
1409#if (__MPU_PRESENT == 1)
1410 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1411 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1412#endif
1413
1414#if (__FPU_PRESENT == 1)
1415 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1416 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1417#endif
1418
1419/*@} */
1420
1421
1422
1423/*******************************************************************************
1424 * Hardware Abstraction Layer
1425 Core Function Interface contains:
1426 - Core NVIC Functions
1427 - Core SysTick Functions
1428 - Core Debug Functions
1429 - Core Register Access Functions
1430 ******************************************************************************/
1431/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1432*/
1433
1434
1435
1436/* ########################## NVIC functions #################################### */
1437/** \ingroup CMSIS_Core_FunctionInterface
1438 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1439 \brief Functions that manage interrupts and exceptions via the NVIC.
1440 @{
1441 */
1442
1443/** \brief Set Priority Grouping
1444
1445 The function sets the priority grouping field using the required unlock sequence.
1446 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1447 Only values from 0..7 are used.
1448 In case of a conflict between priority grouping and available
1449 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1450
1451 \param [in] PriorityGroup Priority grouping field.
1452 */
1453__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1454{
1455 uint32_t reg_value;
1456 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1457
1458 reg_value = SCB->AIRCR; /* read old register configuration */
1459 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1460 reg_value = (reg_value |
1461 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1462 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1463 SCB->AIRCR = reg_value;
1464}
1465
1466
1467/** \brief Get Priority Grouping
1468
1469 The function reads the priority grouping field from the NVIC Interrupt Controller.
1470
1471 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1472 */
1473__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1474{
1475 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1476}
1477
1478
1479/** \brief Enable External Interrupt
1480
1481 The function enables a device-specific interrupt in the NVIC interrupt controller.
1482
1483 \param [in] IRQn External interrupt number. Value cannot be negative.
1484 */
1485__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1486{
1487/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
1488 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
1489}
1490
1491
1492/** \brief Disable External Interrupt
1493
1494 The function disables a device-specific interrupt in the NVIC interrupt controller.
1495
1496 \param [in] IRQn External interrupt number. Value cannot be negative.
1497 */
1498__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1499{
1500 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1501}
1502
1503
1504/** \brief Get Pending Interrupt
1505
1506 The function reads the pending register in the NVIC and returns the pending bit
1507 for the specified interrupt.
1508
1509 \param [in] IRQn Interrupt number.
1510
1511 \return 0 Interrupt status is not pending.
1512 \return 1 Interrupt status is pending.
1513 */
1514__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1515{
1516 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1517}
1518
1519
1520/** \brief Set Pending Interrupt
1521
1522 The function sets the pending bit of an external interrupt.
1523
1524 \param [in] IRQn Interrupt number. Value cannot be negative.
1525 */
1526__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1527{
1528 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1529}
1530
1531
1532/** \brief Clear Pending Interrupt
1533
1534 The function clears the pending bit of an external interrupt.
1535
1536 \param [in] IRQn External interrupt number. Value cannot be negative.
1537 */
1538__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1539{
1540 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1541}
1542
1543
1544/** \brief Get Active Interrupt
1545
1546 The function reads the active register in NVIC and returns the active bit.
1547
1548 \param [in] IRQn Interrupt number.
1549
1550 \return 0 Interrupt status is not active.
1551 \return 1 Interrupt status is active.
1552 */
1553__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1554{
1555 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1556}
1557
1558
1559/** \brief Set Interrupt Priority
1560
1561 The function sets the priority of an interrupt.
1562
1563 \note The priority cannot be set for every core interrupt.
1564
1565 \param [in] IRQn Interrupt number.
1566 \param [in] priority Priority to set.
1567 */
1568__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1569{
1570 if(IRQn < 0) {
1571 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1572 else {
1573 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1574}
1575
1576
1577/** \brief Get Interrupt Priority
1578
1579 The function reads the priority of an interrupt. The interrupt
1580 number can be positive to specify an external (device specific)
1581 interrupt, or negative to specify an internal (core) interrupt.
1582
1583
1584 \param [in] IRQn Interrupt number.
1585 \return Interrupt Priority. Value is aligned automatically to the implemented
1586 priority bits of the microcontroller.
1587 */
1588__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1589{
1590
1591 if(IRQn < 0) {
1592 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1593 else {
1594 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1595}
1596
1597
1598/** \brief Encode Priority
1599
1600 The function encodes the priority for an interrupt with the given priority group,
1601 preemptive priority value, and subpriority value.
1602 In case of a conflict between priority grouping and available
1603 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1604
1605 \param [in] PriorityGroup Used priority group.
1606 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1607 \param [in] SubPriority Subpriority value (starting from 0).
1608 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1609 */
1610__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1611{
1612 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1613 uint32_t PreemptPriorityBits;
1614 uint32_t SubPriorityBits;
1615
1616 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1617 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1618
1619 return (
1620 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1621 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1622 );
1623}
1624
1625
1626/** \brief Decode Priority
1627
1628 The function decodes an interrupt priority value with a given priority group to
1629 preemptive priority value and subpriority value.
1630 In case of a conflict between priority grouping and available
1631 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1632
1633 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1634 \param [in] PriorityGroup Used priority group.
1635 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1636 \param [out] pSubPriority Subpriority value (starting from 0).
1637 */
1638__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1639{
1640 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1641 uint32_t PreemptPriorityBits;
1642 uint32_t SubPriorityBits;
1643
1644 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1645 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1646
1647 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1648 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1649}
1650
1651
1652/** \brief System Reset
1653
1654 The function initiates a system reset request to reset the MCU.
1655 */
1656__STATIC_INLINE void NVIC_SystemReset(void)
1657{
1658 __DSB(); /* Ensure all outstanding memory accesses included
1659 buffered write are completed before reset */
1660 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1661 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1662 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1663 __DSB(); /* Ensure completion of memory access */
1664 while(1); /* wait until reset */
1665}
1666
1667/*@} end of CMSIS_Core_NVICFunctions */
1668
1669
1670
1671/* ################################## SysTick function ############################################ */
1672/** \ingroup CMSIS_Core_FunctionInterface
1673 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1674 \brief Functions that configure the System.
1675 @{
1676 */
1677
1678#if (__Vendor_SysTickConfig == 0)
1679
1680/** \brief System Tick Configuration
1681
1682 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1683 Counter is in free running mode to generate periodic interrupts.
1684
1685 \param [in] ticks Number of ticks between two interrupts.
1686
1687 \return 0 Function succeeded.
1688 \return 1 Function failed.
1689
1690 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1691 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1692 must contain a vendor-specific implementation of this function.
1693
1694 */
1695__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1696{
1697 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1698
1699 SysTick->LOAD = ticks - 1; /* set reload register */
1700 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1701 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1702 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1703 SysTick_CTRL_TICKINT_Msk |
1704 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1705 return (0); /* Function successful */
1706}
1707
1708#endif
1709
1710/*@} end of CMSIS_Core_SysTickFunctions */
1711
1712
1713
1714/* ##################################### Debug In/Output function ########################################### */
1715/** \ingroup CMSIS_Core_FunctionInterface
1716 \defgroup CMSIS_core_DebugFunctions ITM Functions
1717 \brief Functions that access the ITM debug interface.
1718 @{
1719 */
1720
1721extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1722#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1723
1724
1725/** \brief ITM Send Character
1726
1727 The function transmits a character via the ITM channel 0, and
1728 \li Just returns when no debugger is connected that has booked the output.
1729 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1730
1731 \param [in] ch Character to transmit.
1732
1733 \returns Character to transmit.
1734 */
1735__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1736{
1737 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1738 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1739 {
1740 while (ITM->PORT[0].u32 == 0);
1741 ITM->PORT[0].u8 = (uint8_t) ch;
1742 }
1743 return (ch);
1744}
1745
1746
1747/** \brief ITM Receive Character
1748
1749 The function inputs a character via the external variable \ref ITM_RxBuffer.
1750
1751 \return Received character.
1752 \return -1 No character pending.
1753 */
1754__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1755 int32_t ch = -1; /* no character available */
1756
1757 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1758 ch = ITM_RxBuffer;
1759 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1760 }
1761
1762 return (ch);
1763}
1764
1765
1766/** \brief ITM Check Character
1767
1768 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1769
1770 \return 0 No character available.
1771 \return 1 Character available.
1772 */
1773__STATIC_INLINE int32_t ITM_CheckChar (void) {
1774
1775 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1776 return (0); /* no character available */
1777 } else {
1778 return (1); /* character available */
1779 }
1780}
1781
1782/*@} end of CMSIS_core_DebugFunctions */
1783
1784#endif /* __CORE_CM4_H_DEPENDANT */
1785
1786#ifdef __cplusplus
1787}
1788#endif
1789
1790#endif /* __CMSIS_GENERIC */
Note: See TracBrowser for help on using the repository browser.