source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/CMSIS/Include/core_cm0plus.h@ 136

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1/**************************************************************************//**
2 * @file core_cm0plus.h
3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4 * @version V3.30
5 * @date 24. February 2014
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2014 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_CM0PLUS_H_GENERIC
43#define __CORE_CM0PLUS_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex-M0+
67 @{
68 */
69
70/* CMSIS CM0P definitions */
71#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x00) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ ) /* Cosmic */
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
112*/
113#define __FPU_USED 0
114
115#if defined ( __CC_ARM )
116 #if defined __TARGET_FPU_VFP
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120#elif defined ( __GNUC__ )
121 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124
125#elif defined ( __ICCARM__ )
126 #if defined __ARMVFP__
127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #endif
129
130#elif defined ( __TMS470__ )
131 #if defined __TI__VFP_SUPPORT____
132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
133 #endif
134
135#elif defined ( __TASKING__ )
136 #if defined __FPU_VFP__
137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
138 #endif
139
140#elif defined ( __CSMC__ ) /* Cosmic */
141 #if ( __CSMC__ & 0x400) // FPU present for parser
142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
143 #endif
144#endif
145
146#include <stdint.h> /* standard types definitions */
147#include <core_cmInstr.h> /* Core Instruction Access */
148#include <core_cmFunc.h> /* Core Function Access */
149
150#endif /* __CORE_CM0PLUS_H_GENERIC */
151
152#ifndef __CMSIS_GENERIC
153
154#ifndef __CORE_CM0PLUS_H_DEPENDANT
155#define __CORE_CM0PLUS_H_DEPENDANT
156
157/* check device defines and use defaults */
158#if defined __CHECK_DEVICE_DEFINES
159 #ifndef __CM0PLUS_REV
160 #define __CM0PLUS_REV 0x0000
161 #warning "__CM0PLUS_REV not defined in device header file; using default!"
162 #endif
163
164 #ifndef __MPU_PRESENT
165 #define __MPU_PRESENT 0
166 #warning "__MPU_PRESENT not defined in device header file; using default!"
167 #endif
168
169 #ifndef __VTOR_PRESENT
170 #define __VTOR_PRESENT 0
171 #warning "__VTOR_PRESENT not defined in device header file; using default!"
172 #endif
173
174 #ifndef __NVIC_PRIO_BITS
175 #define __NVIC_PRIO_BITS 2
176 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
177 #endif
178
179 #ifndef __Vendor_SysTickConfig
180 #define __Vendor_SysTickConfig 0
181 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
182 #endif
183#endif
184
185/* IO definitions (access restrictions to peripheral registers) */
186/**
187 \defgroup CMSIS_glob_defs CMSIS Global Defines
188
189 <strong>IO Type Qualifiers</strong> are used
190 \li to specify the access to peripheral variables.
191 \li for automatic generation of peripheral register debug information.
192*/
193#ifdef __cplusplus
194 #define __I volatile /*!< Defines 'read only' permissions */
195#else
196 #define __I volatile const /*!< Defines 'read only' permissions */
197#endif
198#define __O volatile /*!< Defines 'write only' permissions */
199#define __IO volatile /*!< Defines 'read / write' permissions */
200
201/*@} end of group Cortex-M0+ */
202
203
204
205/*******************************************************************************
206 * Register Abstraction
207 Core Register contain:
208 - Core Register
209 - Core NVIC Register
210 - Core SCB Register
211 - Core SysTick Register
212 - Core MPU Register
213 ******************************************************************************/
214/** \defgroup CMSIS_core_register Defines and Type Definitions
215 \brief Type definitions and defines for Cortex-M processor based devices.
216*/
217
218/** \ingroup CMSIS_core_register
219 \defgroup CMSIS_CORE Status and Control Registers
220 \brief Core Register type definitions.
221 @{
222 */
223
224/** \brief Union type to access the Application Program Status Register (APSR).
225 */
226typedef union
227{
228 struct
229 {
230#if (__CORTEX_M != 0x04)
231 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
232#else
233 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
234 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
235 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
236#endif
237 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
242 } b; /*!< Structure used for bit access */
243 uint32_t w; /*!< Type used for word access */
244} APSR_Type;
245
246
247/** \brief Union type to access the Interrupt Program Status Register (IPSR).
248 */
249typedef union
250{
251 struct
252 {
253 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
254 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
255 } b; /*!< Structure used for bit access */
256 uint32_t w; /*!< Type used for word access */
257} IPSR_Type;
258
259
260/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
261 */
262typedef union
263{
264 struct
265 {
266 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
267#if (__CORTEX_M != 0x04)
268 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
269#else
270 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
271 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
272 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
273#endif
274 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
275 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
276 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
277 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
278 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
279 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
280 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
281 } b; /*!< Structure used for bit access */
282 uint32_t w; /*!< Type used for word access */
283} xPSR_Type;
284
285
286/** \brief Union type to access the Control Registers (CONTROL).
287 */
288typedef union
289{
290 struct
291 {
292 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
293 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
294 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
295 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
296 } b; /*!< Structure used for bit access */
297 uint32_t w; /*!< Type used for word access */
298} CONTROL_Type;
299
300/*@} end of group CMSIS_CORE */
301
302
303/** \ingroup CMSIS_core_register
304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
305 \brief Type definitions for the NVIC Registers
306 @{
307 */
308
309/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
310 */
311typedef struct
312{
313 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
314 uint32_t RESERVED0[31];
315 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
316 uint32_t RSERVED1[31];
317 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
318 uint32_t RESERVED2[31];
319 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
320 uint32_t RESERVED3[31];
321 uint32_t RESERVED4[64];
322 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
323} NVIC_Type;
324
325/*@} end of group CMSIS_NVIC */
326
327
328/** \ingroup CMSIS_core_register
329 \defgroup CMSIS_SCB System Control Block (SCB)
330 \brief Type definitions for the System Control Block Registers
331 @{
332 */
333
334/** \brief Structure type to access the System Control Block (SCB).
335 */
336typedef struct
337{
338 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
339 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
340#if (__VTOR_PRESENT == 1)
341 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
342#else
343 uint32_t RESERVED0;
344#endif
345 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
346 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
347 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
348 uint32_t RESERVED1;
349 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
350 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
351} SCB_Type;
352
353/* SCB CPUID Register Definitions */
354#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
355#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
356
357#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
358#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
359
360#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
361#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
362
363#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
364#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
365
366#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
367#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
368
369/* SCB Interrupt Control State Register Definitions */
370#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
371#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
372
373#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
374#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
375
376#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
377#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
378
379#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
380#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
381
382#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
383#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
384
385#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
386#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
387
388#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
389#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
390
391#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
392#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
393
394#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
395#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
396
397#if (__VTOR_PRESENT == 1)
398/* SCB Interrupt Control State Register Definitions */
399#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
400#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
401#endif
402
403/* SCB Application Interrupt and Reset Control Register Definitions */
404#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
405#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
406
407#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
408#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
409
410#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
411#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
412
413#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
414#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
415
416#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
417#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
418
419/* SCB System Control Register Definitions */
420#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
421#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
422
423#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
424#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
425
426#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
427#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
428
429/* SCB Configuration Control Register Definitions */
430#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
431#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
432
433#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
434#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
435
436/* SCB System Handler Control and State Register Definitions */
437#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
438#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
439
440/*@} end of group CMSIS_SCB */
441
442
443/** \ingroup CMSIS_core_register
444 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
445 \brief Type definitions for the System Timer Registers.
446 @{
447 */
448
449/** \brief Structure type to access the System Timer (SysTick).
450 */
451typedef struct
452{
453 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
454 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
455 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
456 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
457} SysTick_Type;
458
459/* SysTick Control / Status Register Definitions */
460#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
461#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
462
463#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
464#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
465
466#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
467#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
468
469#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
470#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
471
472/* SysTick Reload Register Definitions */
473#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
474#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
475
476/* SysTick Current Register Definitions */
477#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
478#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
479
480/* SysTick Calibration Register Definitions */
481#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
482#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
483
484#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
485#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
486
487#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
488#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
489
490/*@} end of group CMSIS_SysTick */
491
492#if (__MPU_PRESENT == 1)
493/** \ingroup CMSIS_core_register
494 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
495 \brief Type definitions for the Memory Protection Unit (MPU)
496 @{
497 */
498
499/** \brief Structure type to access the Memory Protection Unit (MPU).
500 */
501typedef struct
502{
503 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
504 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
505 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
506 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
507 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
508} MPU_Type;
509
510/* MPU Type Register */
511#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
512#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
513
514#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
515#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
516
517#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
518#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
519
520/* MPU Control Register */
521#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
522#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
523
524#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
525#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
526
527#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
528#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
529
530/* MPU Region Number Register */
531#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
532#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
533
534/* MPU Region Base Address Register */
535#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
536#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
537
538#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
539#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
540
541#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
542#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
543
544/* MPU Region Attribute and Size Register */
545#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
546#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
547
548#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
549#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
550
551#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
552#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
553
554#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
555#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
556
557#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
558#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
559
560#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
561#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
562
563#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
564#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
565
566#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
567#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
568
569#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
570#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
571
572#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
573#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
574
575/*@} end of group CMSIS_MPU */
576#endif
577
578
579/** \ingroup CMSIS_core_register
580 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
581 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
582 are only accessible over DAP and not via processor. Therefore
583 they are not covered by the Cortex-M0 header file.
584 @{
585 */
586/*@} end of group CMSIS_CoreDebug */
587
588
589/** \ingroup CMSIS_core_register
590 \defgroup CMSIS_core_base Core Definitions
591 \brief Definitions for base addresses, unions, and structures.
592 @{
593 */
594
595/* Memory mapping of Cortex-M0+ Hardware */
596#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
597#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
598#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
599#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
600
601#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
602#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
603#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
604
605#if (__MPU_PRESENT == 1)
606 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
607 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
608#endif
609
610/*@} */
611
612
613
614/*******************************************************************************
615 * Hardware Abstraction Layer
616 Core Function Interface contains:
617 - Core NVIC Functions
618 - Core SysTick Functions
619 - Core Register Access Functions
620 ******************************************************************************/
621/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
622*/
623
624
625
626/* ########################## NVIC functions #################################### */
627/** \ingroup CMSIS_Core_FunctionInterface
628 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
629 \brief Functions that manage interrupts and exceptions via the NVIC.
630 @{
631 */
632
633/* Interrupt Priorities are WORD accessible only under ARMv6M */
634/* The following MACROS handle generation of the register offset and byte masks */
635#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
636#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
637#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
638
639
640/** \brief Enable External Interrupt
641
642 The function enables a device-specific interrupt in the NVIC interrupt controller.
643
644 \param [in] IRQn External interrupt number. Value cannot be negative.
645 */
646__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
647{
648// NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
649 extern void rca_ena_int(uint32_t intno);
650 rca_ena_int(IRQn);
651}
652
653
654/** \brief Disable External Interrupt
655
656 The function disables a device-specific interrupt in the NVIC interrupt controller.
657
658 \param [in] IRQn External interrupt number. Value cannot be negative.
659 */
660__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
661{
662// NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
663 extern void rca_dis_int(uint32_t intno);
664 rca_dis_int(IRQn);
665}
666
667
668/** \brief Get Pending Interrupt
669
670 The function reads the pending register in the NVIC and returns the pending bit
671 for the specified interrupt.
672
673 \param [in] IRQn Interrupt number.
674
675 \return 0 Interrupt status is not pending.
676 \return 1 Interrupt status is pending.
677 */
678__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
679{
680 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
681}
682
683
684/** \brief Set Pending Interrupt
685
686 The function sets the pending bit of an external interrupt.
687
688 \param [in] IRQn Interrupt number. Value cannot be negative.
689 */
690__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
691{
692 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
693}
694
695
696/** \brief Clear Pending Interrupt
697
698 The function clears the pending bit of an external interrupt.
699
700 \param [in] IRQn External interrupt number. Value cannot be negative.
701 */
702__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
703{
704 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
705}
706
707
708/** \brief Set Interrupt Priority
709
710 The function sets the priority of an interrupt.
711
712 \note The priority cannot be set for every core interrupt.
713
714 \param [in] IRQn Interrupt number.
715 \param [in] priority Priority to set.
716 */
717__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
718{
719 if(IRQn < 0) {
720 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
721 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
722 else {
723 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
724 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
725}
726
727
728/** \brief Get Interrupt Priority
729
730 The function reads the priority of an interrupt. The interrupt
731 number can be positive to specify an external (device specific)
732 interrupt, or negative to specify an internal (core) interrupt.
733
734
735 \param [in] IRQn Interrupt number.
736 \return Interrupt Priority. Value is aligned automatically to the implemented
737 priority bits of the microcontroller.
738 */
739__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
740{
741
742 if(IRQn < 0) {
743 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
744 else {
745 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
746}
747
748
749/** \brief System Reset
750
751 The function initiates a system reset request to reset the MCU.
752 */
753__STATIC_INLINE void NVIC_SystemReset(void)
754{
755 __DSB(); /* Ensure all outstanding memory accesses included
756 buffered write are completed before reset */
757 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
758 SCB_AIRCR_SYSRESETREQ_Msk);
759 __DSB(); /* Ensure completion of memory access */
760 while(1); /* wait until reset */
761}
762
763/*@} end of CMSIS_Core_NVICFunctions */
764
765
766
767/* ################################## SysTick function ############################################ */
768/** \ingroup CMSIS_Core_FunctionInterface
769 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
770 \brief Functions that configure the System.
771 @{
772 */
773
774#if (__Vendor_SysTickConfig == 0)
775
776/** \brief System Tick Configuration
777
778 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
779 Counter is in free running mode to generate periodic interrupts.
780
781 \param [in] ticks Number of ticks between two interrupts.
782
783 \return 0 Function succeeded.
784 \return 1 Function failed.
785
786 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
787 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
788 must contain a vendor-specific implementation of this function.
789
790 */
791__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
792{
793 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
794
795 SysTick->LOAD = ticks - 1; /* set reload register */
796 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
797 SysTick->VAL = 0; /* Load the SysTick Counter Value */
798 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
799 SysTick_CTRL_TICKINT_Msk |
800 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
801 return (0); /* Function successful */
802}
803
804#endif
805
806/*@} end of CMSIS_Core_SysTickFunctions */
807
808
809
810
811#endif /* __CORE_CM0PLUS_H_DEPENDANT */
812
813#ifdef __cplusplus
814}
815#endif
816
817#endif /* __CMSIS_GENERIC */
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