source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/CMSIS/Include/core_cm0.h@ 136

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1/**************************************************************************//**
2 * @file core_cm0.h
3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4 * @version V3.30
5 * @date 24. February 2014
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2014 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_CM0_H_GENERIC
43#define __CORE_CM0_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex_M0
67 @{
68 */
69
70/* CMSIS CM0 definitions */
71#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x00) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ ) /* Cosmic */
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
112*/
113#define __FPU_USED 0
114
115#if defined ( __CC_ARM )
116 #if defined __TARGET_FPU_VFP
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120#elif defined ( __GNUC__ )
121 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124
125#elif defined ( __ICCARM__ )
126 #if defined __ARMVFP__
127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #endif
129
130#elif defined ( __TMS470__ )
131 #if defined __TI__VFP_SUPPORT____
132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
133 #endif
134
135#elif defined ( __TASKING__ )
136 #if defined __FPU_VFP__
137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
138 #endif
139
140#elif defined ( __CSMC__ ) /* Cosmic */
141 #if ( __CSMC__ & 0x400) // FPU present for parser
142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
143 #endif
144#endif
145
146#include <stdint.h> /* standard types definitions */
147#include <core_cmInstr.h> /* Core Instruction Access */
148#include <core_cmFunc.h> /* Core Function Access */
149
150#endif /* __CORE_CM0_H_GENERIC */
151
152#ifndef __CMSIS_GENERIC
153
154#ifndef __CORE_CM0_H_DEPENDANT
155#define __CORE_CM0_H_DEPENDANT
156
157/* check device defines and use defaults */
158#if defined __CHECK_DEVICE_DEFINES
159 #ifndef __CM0_REV
160 #define __CM0_REV 0x0000
161 #warning "__CM0_REV not defined in device header file; using default!"
162 #endif
163
164 #ifndef __NVIC_PRIO_BITS
165 #define __NVIC_PRIO_BITS 2
166 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
167 #endif
168
169 #ifndef __Vendor_SysTickConfig
170 #define __Vendor_SysTickConfig 0
171 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
172 #endif
173#endif
174
175/* IO definitions (access restrictions to peripheral registers) */
176/**
177 \defgroup CMSIS_glob_defs CMSIS Global Defines
178
179 <strong>IO Type Qualifiers</strong> are used
180 \li to specify the access to peripheral variables.
181 \li for automatic generation of peripheral register debug information.
182*/
183#ifdef __cplusplus
184 #define __I volatile /*!< Defines 'read only' permissions */
185#else
186 #define __I volatile const /*!< Defines 'read only' permissions */
187#endif
188#define __O volatile /*!< Defines 'write only' permissions */
189#define __IO volatile /*!< Defines 'read / write' permissions */
190
191/*@} end of group Cortex_M0 */
192
193
194
195/*******************************************************************************
196 * Register Abstraction
197 Core Register contain:
198 - Core Register
199 - Core NVIC Register
200 - Core SCB Register
201 - Core SysTick Register
202 ******************************************************************************/
203/** \defgroup CMSIS_core_register Defines and Type Definitions
204 \brief Type definitions and defines for Cortex-M processor based devices.
205*/
206
207/** \ingroup CMSIS_core_register
208 \defgroup CMSIS_CORE Status and Control Registers
209 \brief Core Register type definitions.
210 @{
211 */
212
213/** \brief Union type to access the Application Program Status Register (APSR).
214 */
215typedef union
216{
217 struct
218 {
219#if (__CORTEX_M != 0x04)
220 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
221#else
222 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
223 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
224 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
225#endif
226 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
227 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
228 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
229 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
230 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
231 } b; /*!< Structure used for bit access */
232 uint32_t w; /*!< Type used for word access */
233} APSR_Type;
234
235
236/** \brief Union type to access the Interrupt Program Status Register (IPSR).
237 */
238typedef union
239{
240 struct
241 {
242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
244 } b; /*!< Structure used for bit access */
245 uint32_t w; /*!< Type used for word access */
246} IPSR_Type;
247
248
249/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
250 */
251typedef union
252{
253 struct
254 {
255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
256#if (__CORTEX_M != 0x04)
257 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
258#else
259 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
260 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
261 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
262#endif
263 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
264 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
265 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
270 } b; /*!< Structure used for bit access */
271 uint32_t w; /*!< Type used for word access */
272} xPSR_Type;
273
274
275/** \brief Union type to access the Control Registers (CONTROL).
276 */
277typedef union
278{
279 struct
280 {
281 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
282 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
283 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
284 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
285 } b; /*!< Structure used for bit access */
286 uint32_t w; /*!< Type used for word access */
287} CONTROL_Type;
288
289/*@} end of group CMSIS_CORE */
290
291
292/** \ingroup CMSIS_core_register
293 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
294 \brief Type definitions for the NVIC Registers
295 @{
296 */
297
298/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
299 */
300typedef struct
301{
302 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
303 uint32_t RESERVED0[31];
304 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
305 uint32_t RSERVED1[31];
306 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
307 uint32_t RESERVED2[31];
308 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
309 uint32_t RESERVED3[31];
310 uint32_t RESERVED4[64];
311 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
312} NVIC_Type;
313
314/*@} end of group CMSIS_NVIC */
315
316
317/** \ingroup CMSIS_core_register
318 \defgroup CMSIS_SCB System Control Block (SCB)
319 \brief Type definitions for the System Control Block Registers
320 @{
321 */
322
323/** \brief Structure type to access the System Control Block (SCB).
324 */
325typedef struct
326{
327 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
328 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
329 uint32_t RESERVED0;
330 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
331 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
332 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
333 uint32_t RESERVED1;
334 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
335 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
336} SCB_Type;
337
338/* SCB CPUID Register Definitions */
339#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
340#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
341
342#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
343#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
344
345#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
346#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
347
348#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
349#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
350
351#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
352#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
353
354/* SCB Interrupt Control State Register Definitions */
355#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
356#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
357
358#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
359#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
360
361#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
362#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
363
364#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
365#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
366
367#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
368#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
369
370#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
371#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
372
373#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
374#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
375
376#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
377#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
378
379#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
380#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
381
382/* SCB Application Interrupt and Reset Control Register Definitions */
383#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
384#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
385
386#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
387#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
388
389#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
390#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
391
392#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
393#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
394
395#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
396#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
397
398/* SCB System Control Register Definitions */
399#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
400#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
401
402#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
403#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
404
405#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
406#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
407
408/* SCB Configuration Control Register Definitions */
409#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
410#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
411
412#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
413#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
414
415/* SCB System Handler Control and State Register Definitions */
416#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
417#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
418
419/*@} end of group CMSIS_SCB */
420
421
422/** \ingroup CMSIS_core_register
423 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
424 \brief Type definitions for the System Timer Registers.
425 @{
426 */
427
428/** \brief Structure type to access the System Timer (SysTick).
429 */
430typedef struct
431{
432 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
433 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
434 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
435 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
436} SysTick_Type;
437
438/* SysTick Control / Status Register Definitions */
439#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
440#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
441
442#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
443#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
444
445#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
446#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
447
448#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
449#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
450
451/* SysTick Reload Register Definitions */
452#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
453#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
454
455/* SysTick Current Register Definitions */
456#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
457#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
458
459/* SysTick Calibration Register Definitions */
460#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
461#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
462
463#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
464#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
465
466#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
467#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
468
469/*@} end of group CMSIS_SysTick */
470
471
472/** \ingroup CMSIS_core_register
473 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
474 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
475 are only accessible over DAP and not via processor. Therefore
476 they are not covered by the Cortex-M0 header file.
477 @{
478 */
479/*@} end of group CMSIS_CoreDebug */
480
481
482/** \ingroup CMSIS_core_register
483 \defgroup CMSIS_core_base Core Definitions
484 \brief Definitions for base addresses, unions, and structures.
485 @{
486 */
487
488/* Memory mapping of Cortex-M0 Hardware */
489#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
490#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
491#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
492#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
493
494#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
495#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
496#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
497
498
499/*@} */
500
501
502
503/*******************************************************************************
504 * Hardware Abstraction Layer
505 Core Function Interface contains:
506 - Core NVIC Functions
507 - Core SysTick Functions
508 - Core Register Access Functions
509 ******************************************************************************/
510/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
511*/
512
513
514
515/* ########################## NVIC functions #################################### */
516/** \ingroup CMSIS_Core_FunctionInterface
517 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
518 \brief Functions that manage interrupts and exceptions via the NVIC.
519 @{
520 */
521
522/* Interrupt Priorities are WORD accessible only under ARMv6M */
523/* The following MACROS handle generation of the register offset and byte masks */
524#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
525#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
526#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
527
528
529/** \brief Enable External Interrupt
530
531 The function enables a device-specific interrupt in the NVIC interrupt controller.
532
533 \param [in] IRQn External interrupt number. Value cannot be negative.
534 */
535__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
536{
537 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
538}
539
540
541/** \brief Disable External Interrupt
542
543 The function disables a device-specific interrupt in the NVIC interrupt controller.
544
545 \param [in] IRQn External interrupt number. Value cannot be negative.
546 */
547__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
548{
549 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
550}
551
552
553/** \brief Get Pending Interrupt
554
555 The function reads the pending register in the NVIC and returns the pending bit
556 for the specified interrupt.
557
558 \param [in] IRQn Interrupt number.
559
560 \return 0 Interrupt status is not pending.
561 \return 1 Interrupt status is pending.
562 */
563__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
564{
565 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
566}
567
568
569/** \brief Set Pending Interrupt
570
571 The function sets the pending bit of an external interrupt.
572
573 \param [in] IRQn Interrupt number. Value cannot be negative.
574 */
575__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
576{
577 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
578}
579
580
581/** \brief Clear Pending Interrupt
582
583 The function clears the pending bit of an external interrupt.
584
585 \param [in] IRQn External interrupt number. Value cannot be negative.
586 */
587__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
588{
589 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
590}
591
592
593/** \brief Set Interrupt Priority
594
595 The function sets the priority of an interrupt.
596
597 \note The priority cannot be set for every core interrupt.
598
599 \param [in] IRQn Interrupt number.
600 \param [in] priority Priority to set.
601 */
602__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
603{
604 if(IRQn < 0) {
605 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
606 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
607 else {
608 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
609 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
610}
611
612
613/** \brief Get Interrupt Priority
614
615 The function reads the priority of an interrupt. The interrupt
616 number can be positive to specify an external (device specific)
617 interrupt, or negative to specify an internal (core) interrupt.
618
619
620 \param [in] IRQn Interrupt number.
621 \return Interrupt Priority. Value is aligned automatically to the implemented
622 priority bits of the microcontroller.
623 */
624__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
625{
626
627 if(IRQn < 0) {
628 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
629 else {
630 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
631}
632
633
634/** \brief System Reset
635
636 The function initiates a system reset request to reset the MCU.
637 */
638__STATIC_INLINE void NVIC_SystemReset(void)
639{
640 __DSB(); /* Ensure all outstanding memory accesses included
641 buffered write are completed before reset */
642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
643 SCB_AIRCR_SYSRESETREQ_Msk);
644 __DSB(); /* Ensure completion of memory access */
645 while(1); /* wait until reset */
646}
647
648/*@} end of CMSIS_Core_NVICFunctions */
649
650
651
652/* ################################## SysTick function ############################################ */
653/** \ingroup CMSIS_Core_FunctionInterface
654 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
655 \brief Functions that configure the System.
656 @{
657 */
658
659#if (__Vendor_SysTickConfig == 0)
660
661/** \brief System Tick Configuration
662
663 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
664 Counter is in free running mode to generate periodic interrupts.
665
666 \param [in] ticks Number of ticks between two interrupts.
667
668 \return 0 Function succeeded.
669 \return 1 Function failed.
670
671 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
672 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
673 must contain a vendor-specific implementation of this function.
674
675 */
676__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
677{
678 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
679
680 SysTick->LOAD = ticks - 1; /* set reload register */
681 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
682 SysTick->VAL = 0; /* Load the SysTick Counter Value */
683 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
684 SysTick_CTRL_TICKINT_Msk |
685 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
686 return (0); /* Function successful */
687}
688
689#endif
690
691/*@} end of CMSIS_Core_SysTickFunctions */
692
693
694
695
696#endif /* __CORE_CM0_H_DEPENDANT */
697
698#ifdef __cplusplus
699}
700#endif
701
702#endif /* __CMSIS_GENERIC */
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