source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/ARM.CMSIS.pdsc@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

ライブラリとOS及びベーシックなサンプルの追加.

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1<?xml version="1.0" encoding="utf-8"?>
2
3<package schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
4 <name>CMSIS</name>
5 <description>Cortex Microcontroller Software Interface Standard (CMSIS) CORE, DSP, RTOS, Driver</description>
6 <vendor>ARM</vendor>
7 <!-- <license>CMSIS\CMSIS_END_USER_LICENCE_AGREEMENT.rtf</license> -->
8 <url>http://www.keil.com/pack/</url>
9
10 <taxonomy>
11 <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
12 <description Cclass="CMSIS" doc="CMSIS\Documentation\General\html\index.html">Cortex Microcontroller Software Interface Components</description>
13 <description Cclass="Device" doc="CMSIS\Documentation\Core\html\index.html">Startup, System Setup</description>
14 <description Cclass="Drivers" doc="CMSIS\Documentation\Driver\html\index.html">Unified Device Drivers</description>
15 <description Cclass="File System">File Drive Support and File System</description>
16 <description Cclass="Network">Network Stack using IP descriptions</description>
17 <description Cclass="USB">Universal Serial Bus Stack</description>
18 </taxonomy>
19
20 <releases>
21 <release version="4.0.0">
22 - CMSIS-Driver 2.00 Preliminary (incompatible update)
23 - CMSIS-Pack 1.10 Preliminary
24 - CMSIS-DSP 1.4.2 (see revision history for details)
25 - CMSIS-Core 3.30 (see revision history for details)
26 - CMSIS-RTOS RTX 4.74 (see revision history for details)
27 - CMSIS-RTOS API 1.02 (unchanged)
28 - CMSIS-SVD 1.10 (unchanged)
29 </release>
30 <release version="3.20.4">
31 - CMSIS-RTOS 4.74 (see revision history for details)
32 - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
33 </release>
34 <release version="3.20.3">
35 - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
36 - CMSIS-RTOS 4.73 (see revision history for details)
37 </release>
38 <release version="3.20.2">
39 - CMSIS-Pack documentation has been added
40 - CMSIS-Drivers header and documentation have been added to PACK
41 - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
42 </release>
43 <release version="3.20.1">
44 - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
45 - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
46 </release>
47 <release version="3.20.0">
48 The software portions that are deployed in the application program are now under a BSD license which allows usage
49 of CMSIS components in any commercial or open source projects. The Pack Description file Arm.CMSIS.pdsc describes the use cases
50 The individual components have been update as listed below:
51 - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
52 - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
53 - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
54 - CMSIS-SVD is unchanged.
55 </release>
56 </releases>
57
58 <devices>
59 <!-- ****************************** Cortex-M0 ****************************** -->
60 <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
61 <device Dname="ARMCM0">
62 <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="0" Dmpu="0" Dendian="Little-endian" Dclock="10000000"/>
63 <compile header="Device\ARM\ARMCM0\Include\ARMCM0.h"/>
64 <debug svd="Device\ARM\SVD\ARMCM0.svd"/>
65 <algorithm name="Device\ARM\Flash\NEW_DEVICE.flm" start="0x00000000" size="0x00040000" default="1"/>
66 <book name="Device\ARM\Documents\cortex_m0_dgug.pdf" title="Cortex-M4 Device Generic Users Guide"/>
67
68 <description>
69 The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed
70 for a broad range of embedded applications. It offers significant benefits to developers,
71 including:
72 • simple, easy-to-use programmers model
73 • highly efficient ultra-low power operation
74 • excellent code density
75 • deterministic, high-performance interrupt handling
76 • upward compatibility with the rest of the Cortex-M processor family.
77 </description>
78 </device>
79 </family>
80
81 <!-- ****************************** Cortex-M0P ****************************** -->
82 <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
83 <device Dname="ARMCM0P">
84 <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Little-endian" Dclock="10000000"/>
85 <compile header="Device\ARM\ARMCM0plus\Include\ARMCM0plus.h"/>
86 <debug svd="Device\ARM\SVD\ARMCM0P.svd"/>
87 <algorithm name="Device\ARM\Flash\NEW_DEVICE.flm" start="0x00000000" size="0x00040000" default="1"/>
88 <book name="Device\ARM\Documents\cortex_m0p_dgug.pdf" title="Cortex-M4 Device Generic Users Guide"/>
89 <description>
90 The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed
91 for a broad range of embedded applications. It offers significant benefits to developers,
92 including:
93 • simple, easy-to-use programmers model
94 • highly efficient ultra-low power operation
95 • excellent code density
96 • deterministic, high-performance interrupt handling
97 • upward compatibility with the rest of the Cortex-M processor family.
98 </description>
99 </device>
100 </family>
101
102 <!-- ****************************** Cortex-M3 ****************************** -->
103 <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
104 <device Dname="ARMCM3">
105 <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="0" Dmpu="0" Dendian="Little-endian" Dclock="10000000"/>
106 <compile header="Device\ARM\ARMCM3\Include\ARMCM3.h"/>
107 <debug svd="Device\ARM\SVD\ARMCM3.svd"/>
108 <algorithm name="Device\ARM\Flash\NEW_DEVICE.flm" start="0x00000000" size="0x00040000" default="1"/>
109 <book name="Device\ARM\Documents\cortex_m3_dgug.pdf" title="Cortex-M3 Device Generic Users Guide"/>
110 <description>
111 The Cortex-M3 processor is an entry-level 32-bit ARM Cortex processor designed
112 for a broad range of embedded applications. It offers significant benefits to developers,
113 including:
114 • simple, easy-to-use programmers model
115 • highly efficient ultra-low power operation
116 • excellent code density
117 • deterministic, high-performance interrupt handling
118 • upward compatibility with the rest of the Cortex-M processor family.
119 </description>
120 </device>
121 </family>
122
123 <!-- ****************************** Cortex-M4 ****************************** -->
124 <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
125 <device Dname="ARMCM4">
126 <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="1" Dmpu="0" Dendian="Little-endian" Dclock="10000000"/>
127 <compile header="Device\ARM\ARMCM4\Include\ARMCM4.h"/>
128 <debug svd="Device\ARM\SVD\ARMCM4.svd"/>
129 <algorithm name="Device\ARM\Flash\NEW_DEVICE.flm" start="0x00000000" size="0x00040000" default="1"/>
130 <book name="Device\ARM\Documents\cortex_m4_dgug.pdf" title="Cortex-M4 Device Generic Users Guide"/>
131 <description>
132 The Cortex-M4 processor is an entry-level 32-bit ARM Cortex processor designed
133 for a broad range of embedded applications. It offers significant benefits to developers,
134 including:
135 • simple, easy-to-use programmers model
136 • highly efficient ultra-low power operation
137 • excellent code density
138 • deterministic, high-performance interrupt handling
139 • upward compatibility with the rest of the Cortex-M processor family.
140 </description>
141 </device>
142 </family>
143
144
145 <!-- ****************************** ARMSC000 ****************************** -->
146 <family Dfamily="ARM SC000" Dvendor="ARM:82">
147 <device Dname="ARMSC000">
148 <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Little-endian" Dclock="10000000"/>
149 <compile header="Device\ARM\ARMSC000\Include\ARMSC000.h"/>
150 <debug svd="Device\ARM\SVD\ARMSC000.svd"/>
151 <algorithm name="Device\ARM\Flash\NEW_DEVICE.flm" start="0x00000000" size="0x00040000" default="1"/>
152 <description>
153 The ARM SC000 processor is an entry-level 32-bit ARM Cortex processor designed
154 for a broad range of secure embedded applications. It offers significant benefits to developers,
155 including:
156 • simple, easy-to-use programmers model
157 • highly efficient ultra-low power operation
158 • excellent code density
159 • deterministic, high-performance interrupt handling
160 </description>
161 </device>
162 </family>
163
164
165 <!-- ****************************** ARMSC300 ****************************** -->
166 <family Dfamily="ARM SC300" Dvendor="ARM:82">
167 <device Dname="ARMSC300">
168 <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Little-endian" Dclock="10000000"/>
169 <compile header="Device\ARM\ARMSC300\Include\ARMSC300.h"/>
170 <debug svd="Device\ARM\SVD\ARMSC300.svd"/>
171 <algorithm name="Device\ARM\Flash\NEW_DEVICE.flm" start="0x00000000" size="0x00040000" default="1"/>
172
173 <description>
174 The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed
175 for a broad range of secure embedded applications. It offers significant benefits to developers,
176 including:
177 • simple, easy-to-use programmers model
178 • highly efficient ultra-low power operation
179 • excellent code density
180 • deterministic, high-performance interrupt handling
181 </description>
182 </device>
183 </family>
184
185 </devices>
186
187
188 <apis>
189 <!-- CMSIS-RTOS API -->
190 <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0" exclusive="0">
191 <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
192 <files>
193 <file category="doc" name="CMSIS\Documentation\RTOS\html\index.html"/>
194 </files>
195 </api>
196 <api Cclass="Drivers" Cgroup="UART" Capiversion="2.00" exclusive="0">
197 <description>UART Driver API for Cortex-M</description>
198 <files>
199 <file category="doc" name="CMSIS\Documentation\Driver\html\group__usart__interface__gr.html" />
200 <file category="header" name="CMSIS\Driver\Include\Driver_USART.h" />
201 </files>
202 </api>
203 <api Cclass="Drivers" Cgroup="SPI" Capiversion="2.00" exclusive="0">
204 <description>SPI Driver API for Cortex-M</description>
205 <files>
206 <file category="doc" name="CMSIS\Documentation\Driver\html\group__spi__interface__gr.html" />
207 <file category="header" name="CMSIS\Driver\Include\Driver_SPI.h" />
208 </files>
209 </api>
210 <api Cclass="Drivers" Cgroup="I2C" Capiversion="2.00" exclusive="0">
211 <description>I2C Driver API for Cortex-M</description>
212 <files>
213 <file category="doc" name="CMSIS\Documentation\Driver\html\group__i2c__interface__gr.html"/>
214 <file category="header" name="CMSIS\Driver\Include\Driver_I2C.h" />
215 </files>
216 </api>
217 <api Cclass="Drivers" Cgroup="MCI" Capiversion="2.00" exclusive="0">
218 <description>MCI Driver API for Cortex-M</description>
219 <files>
220 <file category="doc" name="CMSIS\Documentation\Driver\html\group__mci__interface__gr.html" />
221 <file category="header" name="CMSIS\Driver\Include\Driver_MCI.h" />
222 </files>
223 </api>
224 <api Cclass="Drivers" Cgroup="NAND" Capiversion="2.00" exclusive="0">
225 <description>NAND Flash Driver API for Cortex-M</description>
226 <files>
227 <file category="doc" name="CMSIS\Documentation\Driver\html\group__mci__interface__gr.html" />
228 <file category="header" name="CMSIS\Driver\Include\Driver_NAND.h" />
229 </files>
230 </api>
231 <api Cclass="Drivers" Cgroup="NOR" Capiversion="2.00" exclusive="0">
232 <description>NOR Flash Driver API for Cortex-M</description>
233 <files>
234 <file category="doc" name="CMSIS\Documentation\Driver\html\group__nor__interface__gr.html" />
235 <file category="header" name="CMSIS\Driver\Include\Driver_NOR.h" />
236 </files>
237 </api>
238 <api Cclass="Drivers" Cgroup="Ethernet" Capiversion="2.00" exclusive="0">
239 <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
240 <files>
241 <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__interface__gr.html" />
242 <file category="header" name="CMSIS\Driver\Include\Driver_ETH_MAC.h" />
243 <file category="header" name="CMSIS\Driver\Include\Driver_ETH_PHY.h" />
244 </files>
245 </api>
246 <api Cclass="Drivers" Cgroup="Ethernet MAC" Capiversion="2.00" exclusive="0">
247 <description>Ethernet MAC Driver API for Cortex-M</description>
248 <files>
249 <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__mac__interface__gr.html" />
250 <file category="header" name="CMSIS\Driver\Include\Driver_ETH_MAC.h" />
251 </files>
252 </api>
253 <api Cclass="Drivers" Cgroup="Ethernet PHY" Capiversion="2.00" exclusive="0">
254 <description>Ethernet PHY Driver API for Cortex-M</description>
255 <files>
256 <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__phy__interface__gr.html" />
257 <file category="header" name="CMSIS\Driver\Include\Driver_ETH_PHY.h" />
258 </files>
259 </api>
260 <api Cclass="Drivers" Cgroup="USB Device" Capiversion="2.00" exclusive="0">
261 <description>USB Device Driver API for Cortex-M</description>
262 <files>
263 <file category="doc" name="CMSIS\Documentation\Driver\html\group__usbd__interface__gr.html" />
264 <file category="header" name="CMSIS\Driver\Include\Driver_USBD.h" />
265 </files>
266 </api>
267 <api Cclass="Drivers" Cgroup="USB Host" Capiversion="2.00" exclusive="0">
268 <description>USB Host Driver API for Cortex-M</description>
269 <files>
270 <file category="doc" name="CMSIS\Documentation\Driver\html\group__usbh__interface__gr.html" />
271 <file category="header" name="CMSIS\Driver\Include\Driver_USBH.h" />
272 </files>
273 </api>
274 </apis>
275
276 <!-- conditions are dependency rules that can apply to a component or an individual file -->
277 <conditions>
278 <condition id="Is ARM Compiler">
279 <require Tcompiler="ARMCC"/>
280 </condition>
281
282 <condition id="Cortex-M Device">
283 <description>Cortex-M processor based device: one of CM0, CM0+, CM3, CM4, SC000, SC3000</description>
284 <accept Dcore="Cortex-M0"/>
285 <accept Dcore="Cortex-M0+"/>
286 <accept Dcore="Cortex-M3"/>
287 <accept Dcore="Cortex-M4"/>
288 <accept Dcore="SC000"/>
289 <accept Dcore="SC300"/>
290 </condition>
291
292 <condition id="Cortex-M CMSIS Device">
293 <description>ARM Cortex-M device</description>
294 <accept Dname="ARMCM0"/>
295 <accept Dname="ARMCM0+"/>
296 <accept Dname="ARMCM3"/>
297 <accept Dname="ARMCM4"/>
298 <accept Dname="ARMSC000"/>
299 <accept Dname="ARMSC300"/>
300 </condition>
301
302 <condition id="CMSIS Core">
303 <description>CMSIS CORE processor and device specific Startup files</description>
304 <require condition="Cortex-M Device"/>
305 <require Cclass="Device" Cgroup="Startup"/>
306 </condition>
307
308 <condition id="ARMCM0">
309 <!-- conditions selecting Devices -->
310 <description>Generic ARM Cortex-M0 device</description>
311 <require Dvendor="ARM:82" Dname="ARMCM0"/>
312 </condition>
313
314 <condition id="ARMCM0+">
315 <description>Generic ARM Cortex-M0+ device</description>
316 <require Dvendor="ARM:82" Dname="ARMCM0P"/>
317 </condition>
318
319 <condition id="ARMCM3">
320 <description>Generic ARM Cortex-M3 device</description>
321 <require Dvendor="ARM:82" Dname="ARMCM3"/>
322 </condition>
323
324 <condition id="ARMCM4">
325 <description>Generic ARM Cortex-M4 device</description>
326 <require Dvendor="ARM:82" Dname="ARMCM4"/>
327 </condition>
328
329 <condition id="ARMSC000">
330 <description>Generic ARM SC000 device</description>
331 <require Dvendor="ARM:82" Dname="ARMSC000"/>
332 </condition>
333
334 <condition id="ARMSC300">
335 <description>Generic ARM SC300 device</description>
336 <require Dvendor="ARM:82" Dname="ARMSC300"/>
337 </condition>
338
339 <condition id="CMSIS DSP">
340 <description>CMSIS DSP Library is for ARM Cortex-M Devices only and is prebuild for one of the compilers ARMCC, GCC, G++ or IAR</description>
341 <require condition="Cortex-M Device"/>
342 <accept Tcompiler="GCC"/>
343 <accept Tcompiler="G++"/>
344 <accept Tcompiler="ARMCC"/>
345 <accept Tcompiler="IAR"/>
346 </condition>
347
348 <condition id="CM0_LE_ARMCC">
349 <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the ARM Compiler</description>
350 <accept Dcore="Cortex-M0"/>
351 <accept Dcore="Cortex-M0+"/>
352 <accept Dcore="SC000"/>
353 <require Dendian="Little-endian"/>
354 <require Tcompiler="ARMCC"/>
355 </condition>
356
357 <condition id="CM0_BE_ARMCC">
358 <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the ARM Compiler</description>
359 <accept Dcore="Cortex-M0"/>
360 <accept Dcore="Cortex-M0+"/>
361 <accept Dcore="SC000"/>
362 <require Dendian="Big-endian"/>
363 <require Tcompiler="ARMCC"/>
364 </condition>
365
366 <condition id="CM3_LE_ARMCC">
367 <description>Cortex-M3 or SC300 processor based device in little endian mode for the ARM Compiler</description>
368 <accept Dcore="Cortex-M3"/>
369 <accept Dcore="SC300"/>
370 <require Dendian="Little-endian"/>
371 <require Tcompiler="ARMCC"/>
372 </condition>
373
374 <condition id="CM3_BE_ARMCC">
375 <description>Cortex-M3 or SC300 processor based device in big endian mode for the ARM Compiler</description>
376 <accept Dcore="Cortex-M3"/>
377 <accept Dcore="SC300"/>
378 <require Dendian="Big-endian"/>
379 <require Tcompiler="ARMCC"/>
380 </condition>
381
382 <condition id="CM4_LE_ARMCC">
383 <description>Cortex-M4 processor based device in little endian mode for the ARM Compiler</description>
384 <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
385 <require Tcompiler="ARMCC"/>
386 </condition>
387
388 <condition id="CM4_BE_ARMCC">
389 <description>Cortex-M4 processor based device in big endian mode for the ARM Compiler</description>
390 <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Big-endian"/>
391 <require Tcompiler="ARMCC"/>
392 </condition>
393
394 <condition id="CM4F_LE_ARMCC">
395 <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
396 <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
397 <deny Dvendor="Infineon:7" Dname="XMC4*"/>
398 <require Tcompiler="ARMCC"/>
399 </condition>
400
401 <!-- XMC 4000 Series devices from Infineon require a special library -->
402 <condition id="CM4F_LE_ARMCC_IFX">
403 <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler and Infineon devices</description>
404 <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>
405 <require Tcompiler="ARMCC"/>
406 </condition>
407
408 <condition id="CM4F_BE_ARMCC">
409 <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
410 <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Big-endian"/>
411 <require Tcompiler="ARMCC"/>
412 </condition>
413
414 <condition id="CM0_LE_GCC">
415 <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
416 <accept Dcore="Cortex-M0"/>
417 <accept Dcore="Cortex-M0+"/>
418 <accept Dcore="SC000"/>
419 <require Dendian="Little-endian"/>
420 <require Tcompiler="GCC"/>
421 </condition>
422
423 <condition id="CM3_LE_GCC">
424 <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
425 <accept Dcore="Cortex-M3"/>
426 <accept Dcore="SC300"/>
427 <require Dendian="Little-endian"/>
428 <require Tcompiler="GCC"/>
429 </condition>
430
431 <condition id="CM4_LE_GCC">
432 <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
433 <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
434 <require Tcompiler="GCC"/>
435 </condition>
436
437 <condition id="CM4F_LE_GCC">
438 <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
439 <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
440 <deny Dvendor="Infineon:7" Dname="XMC4*"/>
441 <require Tcompiler="GCC"/>
442 </condition>
443
444 <!-- XMC 4000 Series devices from Infineon require a special library -->
445 <condition id="CM4F_LE_GCC_IFX">
446 <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler and Infineon devices</description>
447 <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>
448 <require Tcompiler="GCC"/>
449 </condition>
450
451 <!-- G++ compiler -->
452 <condition id="CM0_LE_G++">
453 <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the G++ Compiler</description>
454 <accept Dcore="Cortex-M0"/>
455 <accept Dcore="Cortex-M0+"/>
456 <accept Dcore="SC000"/>
457 <require Dendian="Little-endian"/>
458 <require Tcompiler="G++"/>
459 </condition>
460
461 <condition id="CM3_LE_G++">
462 <description>Cortex-M3 or SC300 processor based device in little endian mode for the G++ Compiler</description>
463 <accept Dcore="Cortex-M3"/>
464 <accept Dcore="SC300"/>
465 <require Dendian="Little-endian"/>
466 <require Tcompiler="G++"/>
467 </condition>
468
469 <condition id="CM4_LE_G++">
470 <description>Cortex-M4 processor based device in little endian mode for the G++ Compiler</description>
471 <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
472 <require Tcompiler="G++"/>
473 </condition>
474
475 <condition id="CM4F_LE_G++">
476 <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the G++ Compiler</description>
477 <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
478 <require Tcompiler="G++"/>
479 </condition>
480
481 <condition id="CM0_LE_IAR">
482 <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the ARM Compiler</description>
483 <accept Dcore="Cortex-M0"/>
484 <accept Dcore="Cortex-M0+"/>
485 <accept Dcore="SC000"/>
486 <require Dendian="Little-endian"/>
487 <require Tcompiler="IAR"/>
488 </condition>
489
490 <condition id="CM0_BE_IAR">
491 <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the ARM Compiler</description>
492 <accept Dcore="Cortex-M0"/>
493 <accept Dcore="Cortex-M0+"/>
494 <accept Dcore="SC000"/>
495 <require Dendian="Big-endian"/>
496 <require Tcompiler="IAR"/>
497 </condition>
498
499 <condition id="CM3_LE_IAR">
500 <description>Cortex-M3 or SC300 processor based device in little endian mode for the ARM Compiler</description>
501 <accept Dcore="Cortex-M3"/>
502 <accept Dcore="SC300"/>
503 <require Dendian="Little-endian"/>
504 <require Tcompiler="IAR"/>
505 </condition>
506
507 <condition id="CM3_BE_IAR">
508 <description>Cortex-M3 or SC300 processor based device in big endian mode for the ARM Compiler</description>
509 <accept Dcore="Cortex-M3"/>
510 <accept Dcore="SC300"/>
511 <require Dendian="Big-endian"/>
512 <require Tcompiler="IAR"/>
513 </condition>
514
515 <condition id="CM4_LE_IAR">
516 <description>Cortex-M4 processor based device in little endian mode for the ARM Compiler</description>
517 <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
518 <require Tcompiler="IAR"/>
519 </condition>
520
521 <condition id="CM4_BE_IAR">
522 <description>Cortex-M4 processor based device in big endian mode for the ARM Compiler</description>
523 <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Big-endian"/>
524 <require Tcompiler="IAR"/>
525 </condition>
526
527 <condition id="CM4F_LE_IAR">
528 <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
529 <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
530 <require Tcompiler="IAR"/>
531 </condition>
532
533 <condition id="CM4F_BE_IAR">
534 <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
535 <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Big-endian"/>
536 <require Tcompiler="IAR"/>
537 </condition>
538 </conditions>
539
540 <components>
541 <!-- CMSIS-Core component -->
542 <component Cclass="CMSIS" Cgroup="CORE" Cversion="3.30.0" condition="CMSIS Core">
543 <description>CMSIS-CORE for Cortex-M, SC000, and SC300</description>
544 <files>
545 <!-- RTX templates -->
546 <file category="source" attr="template" name="CMSIS\UserCodeTemplates\ITM_Retarget.c" select="CMSIS-CORE 'ITM Printf Debug'" condition="Is ARM Compiler"/>
547 <!-- CPU independent -->
548 <file category="doc" name="CMSIS\Documentation\Core\html\index.html"/>
549 <file category="include" name="CMSIS\Include\"/>
550 </files>
551 </component>
552
553 <!-- CMSIS-Startup component -->
554 <component Cclass="Device" Cgroup="Startup" Cversion="1.0.0" condition="Cortex-M CMSIS Device">
555 <!-- Cversion is necessary -->
556 <description>System and Startup for Generic ARM Cortex-Mx devices</description>
557 <files>
558 <!-- include folder -->
559 <file category="header" name="Device\ARM\ARMCM0\Include\ARMCM0.h" condition="ARMCM0"/>
560 <file category="header" name="Device\ARM\ARMCM0plus\Include\ARMCM0plus.h" condition="ARMCM0+"/>
561 <file category="header" name="Device\ARM\ARMCM3\Include\ARMCM3.h" condition="ARMCM3"/>
562 <file category="header" name="Device\ARM\ARMCM4\Include\ARMCM4.h" condition="ARMCM4"/>
563 <file category="header" name="Device\ARM\ARMSC000\Include\ARMSC000.h" condition="ARMSC000"/>
564 <file category="header" name="Device\ARM\ARMSC300\Include\ARMSC300.h" condition="ARMSC300"/>
565
566 <!-- include path for system header not required, as the device header is specified for device -->
567 <!-- startup files -->
568 <file category="source" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCM0"/>
569 <file category="source" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCM0+"/>
570 <file category="source" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCM3"/>
571 <file category="source" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCM4"/>
572 <file category="source" name="Device\ARM\ARMSC000\Source\ARM\startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMSC000"/>
573 <file category="source" name="Device\ARM\ARMSC300\Source\ARM\startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMSC300"/>
574
575 <!-- system file -->
576 <file category="source" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0" attr="config" condition="ARMCM0"/>
577 <file category="source" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0" attr="config" condition="ARMCM0+"/>
578 <file category="source" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0" attr="config" condition="ARMCM3"/>
579 <file category="source" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0" attr="config" condition="ARMCM4"/>
580 <file category="source" name="Device\ARM\ARMSC000\Source\system_ARMSC000.c" version="1.0.0" attr="config" condition="ARMSC000"/>
581 <file category="source" name="Device\ARM\ARMSC300\Source\system_ARMSC300.c" version="1.0.0" attr="config" condition="ARMSC300"/>
582 </files>
583 </component>
584
585
586 <!-- CMSIS-DSP component -->
587 <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.4.2" condition="CMSIS DSP">
588 <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
589 <files>
590 <!-- CPU independent -->
591 <file category="doc" name="CMSIS\Documentation\DSP\html\index.html"/>
592 <!-- <file category="header" name="CMSIS\Include\arm_common_tables.h"/> -->
593 <file category="header" name="CMSIS\Include\arm_math.h"/>
594 <!-- CPU and Compiler dependent -->
595 <!-- ARMCC -->
596 <file category="library" condition="CM0_LE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM0l_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
597 <file category="library" condition="CM0_BE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM0b_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
598 <file category="library" condition="CM3_LE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM3l_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
599 <file category="library" condition="CM3_BE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM3b_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
600 <file category="library" condition="CM4_LE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM4l_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
601 <file category="library" condition="CM4_BE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM4b_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
602 <file category="library" condition="CM4F_LE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM4lf_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
603 <file category="library" condition="CM4F_BE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM4bf_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
604
605 <!-- GCC -->
606 <file category="library" condition="CM0_LE_GCC" name="CMSIS\Lib\GCC\libarm_cortexM0l_math.a" src="CMSIS\DSP_Lib\Source\GCC"/>
607 <file category="library" condition="CM3_LE_GCC" name="CMSIS\Lib\GCC\libarm_cortexM3l_math.a" src="CMSIS\DSP_Lib\Source\GCC"/>
608 <file category="library" condition="CM4_LE_GCC" name="CMSIS\Lib\GCC\libarm_cortexM4l_math.a" src="CMSIS\DSP_Lib\Source\GCC"/>
609 <file category="library" condition="CM4F_LE_GCC" name="CMSIS\Lib\GCC\libarm_cortexM4lf_math.a" src="CMSIS\DSP_Lib\Source\GCC"/>
610 <!-- G++ -->
611 <file category="library" condition="CM0_LE_G++" name="CMSIS\Lib\G++\libarm_cortexM0l_math.a" src="CMSIS\DSP_Lib\Source\G++"/>
612 <file category="library" condition="CM3_LE_G++" name="CMSIS\Lib\G++\libarm_cortexM3l_math.a" src="CMSIS\DSP_Lib\Source\G++"/>
613 <file category="library" condition="CM4_LE_G++" name="CMSIS\Lib\G++\libarm_cortexM4l_math.a" src="CMSIS\DSP_Lib\Source\G++"/>
614 <file category="library" condition="CM4F_LE_G++" name="CMSIS\Lib\G++\libarm_cortexM4lf_math.a" src="CMSIS\DSP_Lib\Source\G++"/>
615 </files>
616 </component>
617
618 <!-- CMSIS-RTOS Keil RTX component -->
619 <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.74.0" condition="CMSIS Core">
620 <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
621 <RTE_Components_h>
622 <!-- the following content goes into file 'RTE_Components.h' -->
623 #define RTE_RTOS_RTX /* CMSIS-RTOS Keil RTX */
624 </RTE_Components_h>
625 <files>
626 <!-- CPU independent -->
627 <file category="doc" name="CMSIS_RTX\Doc\index.html"/>
628 <file category="header" name="CMSIS_RTX\INC\cmsis_os.h"/>
629 <file category="source" attr="config" name="CMSIS_RTX\Templates\RTX_Conf_CM.c" version="4.70"/>
630
631 <!-- RTX templates -->
632 <file category="header" attr="template" name="CMSIS_RTX\UserCodeTemplates\osObjects.h" select="CMSIS-RTOS 'main' function"/>
633 <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\main.c" select="CMSIS-RTOS 'main' function"/>
634 <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
635 <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MemPool.c" select="CMSIS-RTOS Memory Pool"/>
636 <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MsgQueue.c" select="CMSIS-RTOS Message Queue"/>
637 <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Mutex.c" select="CMSIS-RTOS Mutex"/>
638 <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Semaphore.c" select="CMSIS-RTOS Semaphore"/>
639 <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Thread.c" select="CMSIS-RTOS Thread"/>
640
641 <!-- CPU and Compiler dependent -->
642 <!-- ARMCC -->
643 <file category="library" condition="CM0_LE_ARMCC" name="CMSIS_RTX\Lib\ARM\RTX_CM0.lib" src="CMSIS_RTX\SRC\ARM"/>
644 <file category="library" condition="CM0_BE_ARMCC" name="CMSIS_RTX\Lib\ARM\RTX_CM0_B.lib" src="CMSIS_RTX\SRC\ARM"/>
645 <file category="library" condition="CM3_LE_ARMCC" name="CMSIS_RTX\Lib\ARM\RTX_CM3.lib" src="CMSIS_RTX\SRC\ARM"/>
646 <file category="library" condition="CM3_BE_ARMCC" name="CMSIS_RTX\Lib\ARM\RTX_CM3_B.lib" src="CMSIS_RTX\SRC\ARM"/>
647 <file category="library" condition="CM4_LE_ARMCC" name="CMSIS_RTX\Lib\ARM\RTX_CM3.lib" src="CMSIS_RTX\SRC\ARM"/>
648 <file category="library" condition="CM4_BE_ARMCC" name="CMSIS_RTX\Lib\ARM\RTX_CM3_B.lib" src="CMSIS_RTX\SRC\ARM"/>
649 <file category="library" condition="CM4F_LE_ARMCC" name="CMSIS_RTX\Lib\ARM\RTX_CM4.lib" src="CMSIS_RTX\SRC\ARM"/>
650 <file category="library" condition="CM4F_BE_ARMCC" name="CMSIS_RTX\Lib\ARM\RTX_CM4_B.lib" src="CMSIS_RTX\SRC\ARM"/>
651 <file category="library" condition="CM4F_LE_ARMCC_IFX" name="CMSIS_RTX\Lib\ARM\RTX_CM4_IFX.lib" src="CMSIS\DSP_Lib\Source\ARM"/>
652 <!-- GCC -->
653 <file category="library" condition="CM0_LE_GCC" name="CMSIS_RTX\Lib\GCC\libRTX_CM0.a" src="CMSIS_RTX\SRC\GCC"/>
654 <file category="library" condition="CM3_LE_GCC" name="CMSIS_RTX\Lib\GCC\libRTX_CM3.a" src="CMSIS_RTX\SRC\GCC"/>
655 <file category="library" condition="CM4_LE_GCC" name="CMSIS_RTX\Lib\GCC\libRTX_CM3.a" src="CMSIS_RTX\SRC\GCC"/>
656 <file category="library" condition="CM4F_LE_GCC" name="CMSIS_RTX\Lib\GCC\libRTX_CM4.a" src="CMSIS_RTX\SRC\GCC"/>
657 <file category="library" condition="CM4F_LE_GCC_IFX" name="CMSIS_RTX\Lib\GCC\libRTX_CM4_IFX.a" src="CMSIS\DSP_Lib\Source\GCC"/>
658 <!-- IAR -->
659 <file category="library" condition="CM0_LE_IAR" name="CMSIS_RTX\Lib\IAR\RTX_CM0.a" src="CMSIS_RTX\SRC\IAR"/>
660 <file category="library" condition="CM0_BE_IAR" name="CMSIS_RTX\Lib\IAR\RTX_CM0_B.a" src="CMSIS_RTX\SRC\IAR"/>
661 <file category="library" condition="CM3_LE_IAR" name="CMSIS_RTX\Lib\IAR\RTX_CM3.a" src="CMSIS_RTX\SRC\IAR"/>
662 <file category="library" condition="CM3_BE_IAR" name="CMSIS_RTX\Lib\IAR\RTX_CM3_B.a" src="CMSIS_RTX\SRC\IAR"/>
663 <file category="library" condition="CM4_LE_IAR" name="CMSIS_RTX\Lib\IAR\RTX_CM3.a" src="CMSIS_RTX\SRC\IAR"/>
664 <file category="library" condition="CM4_BE_IAR" name="CMSIS_RTX\Lib\IAR\RTX_CM3_B.a" src="CMSIS_RTX\SRC\IAR"/>
665 <file category="library" condition="CM4F_LE_IAR" name="CMSIS_RTX\Lib\IAR\RTX_CM4.a" src="CMSIS_RTX\SRC\IAR"/>
666 <file category="library" condition="CM4F_BE_IAR" name="CMSIS_RTX\Lib\IAR\RTX_CM4_B.a" src="CMSIS_RTX\SRC\IAR"/>
667 </files>
668 </component>
669 </components>
670</package>
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