[136] | 1 | /*
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| 2 | Copyright (c) 2011 Arduino. All right reserved.
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| 3 |
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| 4 | This library is free software; you can redistribute it and/or
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| 5 | modify it under the terms of the GNU Lesser General Public
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| 6 | License as published by the Free Software Foundation; either
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| 7 | version 2.1 of the License, or (at your option) any later version.
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| 8 |
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| 9 | This library is distributed in the hope that it will be useful,
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| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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| 12 | See the GNU Lesser General Public License for more details.
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| 13 |
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| 14 | You should have received a copy of the GNU Lesser General Public
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| 15 | License along with this library; if not, write to the Free Software
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| 16 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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| 17 | */
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| 18 |
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| 19 | #include "variant.h"
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| 20 | #include "wiring_digital.h"
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| 21 | #include "wiring.h"
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| 22 |
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| 23 | #ifdef __cplusplus
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| 24 | extern "C" {
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| 25 | #endif
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| 26 |
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| 27 | /*
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| 28 | * System Core Clock is at 1MHz at Reset.
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| 29 | * It is switched to 48MHz in the Reset Handler (startup.c)
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| 30 | */
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| 31 | uint32_t SystemCoreClock=1000000ul ;
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| 32 |
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| 33 | /*
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| 34 | * Arduino Zero board initialization
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| 35 | *
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| 36 | * Good to know:
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| 37 | * - At reset, ResetHandler did the system clock configuration. Core is running at 48MHz.
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| 38 | * - Watchdog is disabled by default, unless someone plays with NVM User page
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| 39 | * - During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
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| 40 | */
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| 41 | void init( void )
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| 42 | {
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| 43 | uint32_t ul ;
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| 44 |
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| 45 | // Set Systick to 1ms interval, common to all Cortex-M variants
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| 46 | if ( SysTick_Config( SystemCoreClock / 1000 ) )
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| 47 | {
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| 48 | // Capture error
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| 49 | while ( 1 ) ;
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| 50 | }
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| 51 |
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| 52 | // Clock PORT for Digital I/O
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| 53 | // PM->APBBMASK.reg |= PM_APBBMASK_PORT ;
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| 54 | //
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| 55 | // Clock EIC for I/O interrupts
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| 56 | // PM->APBAMASK.reg |= PM_APBAMASK_EIC ;
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| 57 |
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| 58 | // Clock SERCOM for Serial
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| 59 | PM->APBCMASK.reg |= PM_APBCMASK_SERCOM0 | PM_APBCMASK_SERCOM1 | PM_APBCMASK_SERCOM2 | PM_APBCMASK_SERCOM3 | PM_APBCMASK_SERCOM4 | PM_APBCMASK_SERCOM5 ;
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| 60 |
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| 61 | // Clock TC/TCC for Pulse and Analog
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| 62 | PM->APBCMASK.reg |= PM_APBCMASK_TCC0 | PM_APBCMASK_TCC1 | PM_APBCMASK_TCC2 | PM_APBCMASK_TC3 | PM_APBCMASK_TC4 | PM_APBCMASK_TC5 | PM_APBCMASK_TC6 | PM_APBCMASK_TC7 ;
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| 63 |
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| 64 | // Clock ADC/DAC for Analog
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| 65 | PM->APBCMASK.reg |= PM_APBCMASK_ADC | PM_APBCMASK_DAC ;
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| 66 |
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| 67 | // Setup all pins (digital and analog) in INPUT mode (default is nothing)
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| 68 | for ( ul = 0 ; ul < NUM_DIGITAL_PINS ; ul++ )
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| 69 | {
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| 70 | pinMode( ul, INPUT ) ;
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| 71 | }
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| 72 |
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| 73 | // Initialize Analog Controller
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| 74 | // Setting clock
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| 75 | GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_ADC ) | // Generic Clock ADC
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| 76 | GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
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| 77 | GCLK_CLKCTRL_CLKEN ;
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| 78 | // Setting CTRLB
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| 79 | ADC->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV128 | // Divide Clock by 128.
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| 80 | ADC_CTRLB_RESSEL_10BIT; // Result on 10 bits
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| 81 | ADC->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | // No Negative input (Internal Ground)
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[175] | 82 | ADC_INPUTCTRL_GAIN_DIV2; // Gain setted to 1/2
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[136] | 83 | // Averaging (see table 31-2 p.816 datasheet)
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| 84 | ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_2 | // 2 samples
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| 85 | ADC_AVGCTRL_ADJRES(0x01ul); // Adjusting result by 1
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| 86 |
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| 87 | ADC->SAMPCTRL.reg = 0x3f;
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| 88 | ADC->REFCTRL.reg = ADC_REFCTRL_REFSEL_INTVCC1; // Reference intvcc1 [default]
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| 89 |
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| 90 | ADC->CTRLA.bit.ENABLE = 1; // Enable ADC
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| 91 | while( ADC->STATUS.bit.SYNCBUSY == 1 )
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| 92 | {
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| 93 | // Waiting for synchroinization
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| 94 | }
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| 95 |
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| 96 | // Initialize DAC
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| 97 | // Setting clock
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| 98 | GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_DAC ) | // Generic Clock ADC
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| 99 | GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
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| 100 | GCLK_CLKCTRL_CLKEN ;
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| 101 |
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| 102 |
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| 103 | DAC->CTRLB.reg = DAC_CTRLB_REFSEL_AVCC | // Using the 3.3V reference
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| 104 | DAC_CTRLB_EOEN; // External Output Enable (Vout)
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| 105 | DAC->DATA.reg = 0x3FFul;
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| 106 | }
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| 107 |
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| 108 | #ifdef __cplusplus
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| 109 | }
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| 110 | #endif
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