[136] | 1 | /*
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| 2 | Arduino.h - Main include file for the Arduino SDK
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| 3 | Copyright (c) 2014 Arduino Team. All right reserved.
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| 4 |
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| 5 | This library is free software; you can redistribute it and/or
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| 6 | modify it under the terms of the GNU Lesser General Public
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| 7 | License as published by the Free Software Foundation; either
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| 8 | version 2.1 of the License, or (at your option) any later version.
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| 9 |
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| 10 | This library is distributed in the hope that it will be useful,
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| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 13 | Lesser General Public License for more details.
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| 14 |
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| 15 | You should have received a copy of the GNU Lesser General Public
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| 16 | License along with this library; if not, write to the Free Software
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| 17 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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| 18 | */
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| 19 |
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| 20 | #include "sam.h"
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| 21 | #include "variant.h"
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| 22 |
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| 23 | /* Initialize segments */
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| 24 | extern uint32_t __etext ;
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| 25 | extern uint32_t __data_start__ ;
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| 26 | extern uint32_t __data_end__ ;
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| 27 | extern uint32_t __bss_start__ ;
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| 28 | extern uint32_t __bss_end__ ;
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| 29 | extern uint32_t __StackTop;
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| 30 |
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| 31 | extern int main( void ) ;
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| 32 | extern void __libc_init_array(void);
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| 33 |
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| 34 | /* Default empty handler */
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| 35 | void Dummy_Handler(void);
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| 36 |
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| 37 | /* Cortex-M0+ core handlers */
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| 38 | #if defined DEBUG
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| 39 | void NMI_Handler( void )
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| 40 | {
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| 41 | while ( 1 )
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| 42 | {
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| 43 | }
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| 44 | }
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| 45 |
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| 46 | void HardFault_Handler( void )
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| 47 | {
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| 48 | while ( 1 )
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| 49 | {
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| 50 | }
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| 51 | }
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| 52 |
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| 53 | void SVC_Handler( void )
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| 54 | {
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| 55 | while ( 1 )
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| 56 | {
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| 57 | }
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| 58 | }
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| 59 |
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| 60 | void PendSV_Handler( void )
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| 61 | {
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| 62 | while ( 1 )
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| 63 | {
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| 64 | }
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| 65 | }
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| 66 |
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| 67 | void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 68 | #else
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| 69 | void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 70 | void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 71 | void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 72 | void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 73 | void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 74 | #endif //DEBUG
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| 75 |
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| 76 | /* Peripherals handlers */
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| 77 | void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 78 | void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 79 | void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 80 | void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 81 | void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 82 | void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 83 | void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 84 | void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 85 | void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 86 | void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 87 | void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 88 | void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 89 | void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 90 | void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 91 | void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 92 | void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 93 | void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 94 | void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 95 | void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 96 | void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 97 | void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 98 | void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 99 | void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 100 | void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 101 | void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 102 | void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 103 | void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 104 | void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
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| 105 |
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| 106 | /* Exception Table */
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| 107 | __attribute__ ((section(".isr_vector")))
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| 108 | const DeviceVectors exception_table=
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| 109 | {
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| 110 | /* Configure Initial Stack Pointer, using linker-generated symbols */
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| 111 | (void*) (&__StackTop),
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| 112 |
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| 113 | (void*) Reset_Handler,
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| 114 | (void*) NMI_Handler,
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| 115 | (void*) HardFault_Handler,
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| 116 | (void*) (0UL), /* Reserved */
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| 117 | (void*) (0UL), /* Reserved */
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| 118 | (void*) (0UL), /* Reserved */
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| 119 | (void*) (0UL), /* Reserved */
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| 120 | (void*) (0UL), /* Reserved */
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| 121 | (void*) (0UL), /* Reserved */
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| 122 | (void*) (0UL), /* Reserved */
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| 123 | (void*) SVC_Handler,
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| 124 | (void*) (0UL), /* Reserved */
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| 125 | (void*) (0UL), /* Reserved */
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| 126 | (void*) PendSV_Handler,
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| 127 | (void*) SysTick_Handler,
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| 128 |
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| 129 | /* Configurable interrupts */
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| 130 | (void*) PM_Handler, /* 0 Power Manager */
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| 131 | (void*) SYSCTRL_Handler, /* 1 System Control */
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| 132 | (void*) WDT_Handler, /* 2 Watchdog Timer */
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| 133 | (void*) RTC_Handler, /* 3 Real-Time Counter */
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| 134 | (void*) EIC_Handler, /* 4 External Interrupt Controller */
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| 135 | (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
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| 136 | (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
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| 137 | (void*) USB_Handler, /* 7 Universal Serial Bus */
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| 138 | (void*) EVSYS_Handler, /* 8 Event System Interface */
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| 139 | (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
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| 140 | (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
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| 141 | (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
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| 142 | (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
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| 143 | (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
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| 144 | (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
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| 145 | (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
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| 146 | (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
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| 147 | (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
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| 148 | (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
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| 149 | (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
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| 150 | (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
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| 151 | (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
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| 152 | (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
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| 153 | (void*) ADC_Handler, /* 23 Analog Digital Converter */
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| 154 | (void*) AC_Handler, /* 24 Analog Comparators */
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| 155 | (void*) DAC_Handler, /* 25 Digital Analog Converter */
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| 156 | (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
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| 157 | (void*) I2S_Handler /* 27 Inter-IC Sound Interface */
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| 158 | } ;
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| 159 |
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| 160 | /**
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| 161 | * \brief This is the code that gets called on processor reset.
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| 162 | * It configures the needed clocks and according Flash Read Wait States.
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| 163 | * At reset:
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| 164 | * - OSC8M clock source is enabled with a divider by 8 (1MHz).
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| 165 | * - Generic Clock Generator 0 (GCLKMAIN) is using OSC8M as source.
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| 166 | * We need to:
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| 167 | * 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator), will be used as DFLL48M reference.
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| 168 | * 2) Put XOSC32K as source of Generic Clock Generator 1
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| 169 | * 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
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| 170 | * 4) Enable DFLL48M clock
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| 171 | * 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
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| 172 | * 6) Modify PRESCaler value of OSCM to have 8MHz
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| 173 | * 7) Put OSC8M as source for Generic Clock Generator 3
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| 174 | */
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| 175 | // Constants for Clock generators
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| 176 | #define GENERIC_CLOCK_GENERATOR_MAIN (0u)
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| 177 | #define GENERIC_CLOCK_GENERATOR_XOSC32K (1u)
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| 178 | #define GENERIC_CLOCK_GENERATOR_OSCULP32K (2u) /* Initialized at reset for WDT */
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| 179 | #define GENERIC_CLOCK_GENERATOR_OSC8M (3u)
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| 180 | // Constants for Clock multiplexers
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| 181 | #define GENERIC_CLOCK_MULTIPLEXER_DFLL48M (0u)
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| 182 |
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| 183 | void SystemInit( void )
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| 184 | {
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| 185 | //----- Tx & Rx led blinking during transmission (pin declaration) ----- begin ----
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| 186 | PORT->Group[1].DIRSET.reg=0x00000008; //PB03 as output (RX_LED)
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| 187 | PORT->Group[1].OUTSET.reg=0x00000008; //PB03 as output (RX_LED)
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| 188 |
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| 189 | PORT->Group[0].DIRSET.reg=0x08000000; //PB03 as output (TX_LED)
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| 190 | PORT->Group[0].OUTSET.reg=0x08000000; //PB03 as output (TX_LED)
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| 191 | //----- Tx & Rx led blinking during transmission (pin declaration) ----- end ----
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| 192 |
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| 193 | /* Set 1 Flash Wait State for 48MHz, cf tables 20.9 and 35.27 in SAMD21 Datasheet */
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| 194 | NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
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| 195 |
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| 196 | /* Turn on the digital interface clock */
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| 197 | PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
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| 198 |
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| 199 | /* ----------------------------------------------------------------------------------------------
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| 200 | * 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
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| 201 | */
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| 202 | SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x6u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
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| 203 | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K ;
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| 204 | SYSCTRL->XOSC32K.bit.ENABLE = 1 ; /* separate call, as described in chapter 15.6.3 */
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| 205 |
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| 206 | while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0 )
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| 207 | {
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| 208 | /* Wait for oscillator stabilization */
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| 209 | }
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| 210 |
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| 211 | /* Software reset the module to ensure it is re-initialized correctly */
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| 212 | /* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
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| 213 | * CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete, as described in chapter 13.8.1
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| 214 | */
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| 215 | GCLK->CTRL.reg = GCLK_CTRL_SWRST ;
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| 216 |
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| 217 | while ( (GCLK->CTRL.reg & GCLK_CTRL_SWRST) && (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) )
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| 218 | {
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| 219 | /* Wait for reset to complete */
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| 220 | }
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| 221 |
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| 222 | /* ----------------------------------------------------------------------------------------------
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| 223 | * 2) Put XOSC32K as source of Generic Clock Generator 1
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| 224 | */
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| 225 | GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) ; // Generic Clock Generator 1
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| 226 |
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| 227 | while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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| 228 | {
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| 229 | /* Wait for synchronization */
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| 230 | }
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| 231 |
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| 232 | /* Write Generic Clock Generator 1 configuration */
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| 233 | GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) | // Generic Clock Generator 1
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| 234 | GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
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| 235 | // GCLK_GENCTRL_OE | // Output clock to a pin for tests
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| 236 | GCLK_GENCTRL_GENEN ;
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| 237 |
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| 238 | while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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| 239 | {
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| 240 | /* Wait for synchronization */
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| 241 | }
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| 242 |
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| 243 | /* ----------------------------------------------------------------------------------------------
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| 244 | * 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
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| 245 | */
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| 246 | GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_MULTIPLEXER_DFLL48M ) | // Generic Clock Multiplexer 0
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| 247 | GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
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| 248 | GCLK_CLKCTRL_CLKEN ;
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| 249 |
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| 250 | while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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| 251 | {
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| 252 | /* Wait for synchronization */
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| 253 | }
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| 254 |
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| 255 | /* ----------------------------------------------------------------------------------------------
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| 256 | * 4) Enable DFLL48M clock
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| 257 | */
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| 258 |
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| 259 | /* DFLL Configuration in Closed Loop mode, cf product datasheet chapter 15.6.7.1 - Closed-Loop Operation */
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| 260 |
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| 261 | /* Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905 */
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| 262 | SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0 ;
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| 263 |
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| 264 | while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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| 265 | {
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| 266 | /* Wait for synchronization */
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| 267 | }
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| 268 |
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| 269 | SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
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| 270 | SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
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| 271 | SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK/VARIANT_MAINOSC) ) ; // External 32KHz is the reference
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| 272 |
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| 273 | while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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| 274 | {
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| 275 | /* Wait for synchronization */
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| 276 | }
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| 277 |
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| 278 | /* Write full configuration to DFLL control register */
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| 279 | SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
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| 280 | SYSCTRL_DFLLCTRL_WAITLOCK |
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| 281 | SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
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| 282 |
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| 283 | while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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| 284 | {
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| 285 | /* Wait for synchronization */
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| 286 | }
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| 287 |
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| 288 | /* Enable the DFLL */
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| 289 | SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
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| 290 |
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| 291 | while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
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| 292 | (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
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| 293 | {
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| 294 | /* Wait for locks flags */
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| 295 | }
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| 296 |
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| 297 | while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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| 298 | {
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| 299 | /* Wait for synchronization */
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| 300 | }
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| 301 |
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| 302 | /* ----------------------------------------------------------------------------------------------
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| 303 | * 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
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| 304 | */
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| 305 | GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_MAIN ) ; // Generic Clock Generator 0
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| 306 |
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| 307 | while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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| 308 | {
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| 309 | /* Wait for synchronization */
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| 310 | }
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| 311 |
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| 312 | /* Write Generic Clock Generator 0 configuration */
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| 313 | GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock Generator 0
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| 314 | GCLK_GENCTRL_SRC_DFLL48M | // Selected source is DFLL 48MHz
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| 315 | // GCLK_GENCTRL_OE | // Output clock to a pin for tests
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| 316 | GCLK_GENCTRL_IDC | // Set 50/50 duty cycle
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| 317 | GCLK_GENCTRL_GENEN ;
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| 318 |
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| 319 | while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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| 320 | {
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| 321 | /* Wait for synchronization */
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| 322 | }
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| 323 |
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| 324 | /* ----------------------------------------------------------------------------------------------
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| 325 | * 6) Modify PRESCaler value of OSC8M to have 8MHz
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| 326 | */
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| 327 | SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_0_Val ;
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| 328 | SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
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| 329 |
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| 330 | /* ----------------------------------------------------------------------------------------------
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| 331 | * 7) Put OSC8M as source for Generic Clock Generator 3
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| 332 | */
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| 333 | GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) ; // Generic Clock Generator 3
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| 334 |
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| 335 | /* Write Generic Clock Generator 3 configuration */
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| 336 | GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) | // Generic Clock Generator 3
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| 337 | GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
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| 338 | // GCLK_GENCTRL_OE | // Output clock to a pin for tests
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| 339 | GCLK_GENCTRL_GENEN ;
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| 340 |
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| 341 | while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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| 342 | {
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| 343 | /* Wait for synchronization */
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| 344 | }
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| 345 |
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| 346 | /*
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| 347 | * Now that all system clocks are configured, we can set CPU and APBx BUS clocks.
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| 348 | * There values are normally the one present after Reset.
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| 349 | */
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| 350 | PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
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| 351 | PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
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| 352 | PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
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| 353 | PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
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| 354 |
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| 355 | SystemCoreClock=VARIANT_MCK ;
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| 356 | }
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| 357 |
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| 358 | /**
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| 359 | * \brief This is the code that gets called on processor reset.
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| 360 | * To initialize the device, and call the main() routine.
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| 361 | */
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| 362 | void Reset_Handler( void )
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| 363 | {
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| 364 | uint32_t *pSrc, *pDest;
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| 365 |
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| 366 | /* Initialize the initialized data section */
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| 367 | pSrc = &__etext;
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| 368 | pDest = &__data_start__;
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| 369 |
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| 370 | if ( (&__data_start__ != &__data_end__) && (pSrc != pDest) )
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| 371 | {
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| 372 | for (; pDest < &__data_end__ ; pDest++, pSrc++ )
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| 373 | {
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| 374 | *pDest = *pSrc ;
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| 375 | }
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| 376 | }
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| 377 |
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| 378 | /* Clear the zero section */
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| 379 | if ( (&__data_start__ != &__data_end__) && (pSrc != pDest) )
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| 380 | {
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| 381 | for ( pDest = &__bss_start__ ; pDest < &__bss_end__ ; pDest++ )
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| 382 | {
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| 383 | *pDest = 0 ;
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| 384 | }
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| 385 | }
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| 386 |
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| 387 | /* Initialize the C library */
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| 388 | __libc_init_array();
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| 389 |
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| 390 | SystemInit() ;
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| 391 |
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| 392 | /* Branch to main function */
|
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| 393 | main() ;
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| 394 |
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| 395 | /* Infinite loop */
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| 396 | while ( 1 )
|
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| 397 | {
|
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| 398 | }
|
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| 399 | }
|
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| 400 |
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| 401 | /**
|
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| 402 | * \brief Default interrupt handler for unused IRQs.
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| 403 | */
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| 404 | void Dummy_Handler( void )
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| 405 | {
|
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| 406 | while ( 1 )
|
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| 407 | {
|
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| 408 | }
|
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| 409 | }
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