1 | /* ----------------------------------------------------------------------------
|
---|
2 | * SAM Software Package License
|
---|
3 | * ----------------------------------------------------------------------------
|
---|
4 | * Copyright (c) 2011-2012, Atmel Corporation
|
---|
5 | *
|
---|
6 | * All rights reserved.
|
---|
7 | *
|
---|
8 | * Redistribution and use in source and binary forms, with or without
|
---|
9 | * modification, are permitted provided that the following condition is met:
|
---|
10 | *
|
---|
11 | * - Redistributions of source code must retain the above copyright notice,
|
---|
12 | * this list of conditions and the disclaimer below.
|
---|
13 | *
|
---|
14 | * Atmel's name may not be used to endorse or promote products derived from
|
---|
15 | * this software without specific prior written permission.
|
---|
16 | *
|
---|
17 | * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
---|
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
---|
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
---|
20 | * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
---|
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
---|
22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
---|
23 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
---|
24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
---|
25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
---|
26 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
---|
27 | * ----------------------------------------------------------------------------
|
---|
28 | */
|
---|
29 |
|
---|
30 | #ifndef UOTGHS_HOST_H_INCLUDED
|
---|
31 | #define UOTGHS_HOST_H_INCLUDED
|
---|
32 |
|
---|
33 |
|
---|
34 | #ifdef __cplusplus
|
---|
35 | extern "C" {
|
---|
36 | #endif
|
---|
37 |
|
---|
38 | //! \ingroup usb_host_group
|
---|
39 | //! \defgroup uhd_group USB Host Driver (UHD)
|
---|
40 | //! UOTGHS low-level driver for USB host mode
|
---|
41 | //!
|
---|
42 | //! @{
|
---|
43 |
|
---|
44 | //! @name UOTGHS Host IP properties
|
---|
45 | //!
|
---|
46 | //! @{
|
---|
47 | //! Get maximal number of endpoints
|
---|
48 | #define uhd_get_pipe_max_nbr() (9)
|
---|
49 | #define UOTGHS_EPT_NUM (uhd_get_pipe_max_nbr()+1)
|
---|
50 | //! @}
|
---|
51 |
|
---|
52 | //! @name Host Vbus line control
|
---|
53 | //!
|
---|
54 | //! VBOF is an optional output pin which allows to enable or disable
|
---|
55 | //! the external VBus generator.
|
---|
56 | //!
|
---|
57 | //! @{
|
---|
58 | //! Enables hardware control of USB_VBOF output pin when a Vbus error occur
|
---|
59 | #define uhd_enable_vbus_error_hw_control() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSHWC))
|
---|
60 | //! Disables hardware control of USB_VBOF output pin when a Vbus error occur
|
---|
61 | #define uhd_disable_vbus_error_hw_control() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSHWC))
|
---|
62 |
|
---|
63 | //! Pin and function for USB_VBOF according to configuration from USB_VBOF
|
---|
64 | #define USB_VBOF_PIN USB_VBOF_GPIO
|
---|
65 | #define USB_VBOF_FUNCTION USB_VBOF_FLAGS
|
---|
66 | //! Output USB_VBOF onto its pin
|
---|
67 | #define uhd_output_vbof_pin() do {\
|
---|
68 | pio_configure_pin(USB_VBOF_PIN, USB_VBOF_FUNCTION); \
|
---|
69 | } while (0)
|
---|
70 |
|
---|
71 | //! Set USB_VBOF output pin polarity
|
---|
72 | #define uhd_set_vbof_active_high() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSPO))
|
---|
73 | #define uhd_set_vbof_active_low() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSPO))
|
---|
74 | //! Requests VBus activation
|
---|
75 | #define uhd_enable_vbus() (Set_bits(UOTGHS->UOTGHS_SFR, UOTGHS_SR_VBUSRQ))
|
---|
76 | //! Requests VBus deactivation
|
---|
77 | #define uhd_disable_vbus() (Set_bits(UOTGHS->UOTGHS_SCR, UOTGHS_SR_VBUSRQ))
|
---|
78 | //! Tests if VBus activation has been requested
|
---|
79 | #define Is_uhd_vbus_enabled() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSRQ))
|
---|
80 | //! @}
|
---|
81 |
|
---|
82 | //! @name Host Vbus line monitoring
|
---|
83 | //!
|
---|
84 | //! The VBus level is always checked by USBC hardware.
|
---|
85 | //!
|
---|
86 | //! @{
|
---|
87 | #define uhd_enable_vbus_error_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
|
---|
88 | #define uhd_disable_vbus_error_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
|
---|
89 | #define Is_uhd_vbus_error_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
|
---|
90 | #define uhd_ack_vbus_error_interrupt() (Set_bits(UOTGHS->UOTGHS_SCR, UOTGHS_SCR_VBERRIC))
|
---|
91 | #define Is_uhd_vbus_error_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBERRI))
|
---|
92 | //! @}
|
---|
93 |
|
---|
94 | #define uhd_ack_errors_interrupt() (UOTGHS->UOTGHS_SCR = (UOTGHS_SCR_VBERRIC|UOTGHS_SCR_BCERRIC|UOTGHS_SCR_HNPERRIC|UOTGHS_SCR_STOIC))
|
---|
95 | #define Is_uhd_errors_interrupt() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE|UOTGHS_CTRL_BCERRE|UOTGHS_CTRL_HNPERRE|UOTGHS_CTRL_STOE))
|
---|
96 | #define uhd_enable_suspend_error_interrupt()
|
---|
97 | #define uhd_enable_hnp_error_interrupt()
|
---|
98 | #define uhd_enable_bconn_error_interrupt()
|
---|
99 |
|
---|
100 | //! @name USB device connection/disconnection monitoring
|
---|
101 | //! @{
|
---|
102 | #define uhd_enable_connection_int() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_DCONNIES)
|
---|
103 | #define uhd_disable_connection_int() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_DCONNIEC)
|
---|
104 | #define Is_uhd_connection_int_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_DCONNIE))
|
---|
105 | #define uhd_ack_connection() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_DCONNIC)
|
---|
106 | #define Is_uhd_connection() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_DCONNI))
|
---|
107 |
|
---|
108 | #define uhd_enable_disconnection_int() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_DDISCIES)
|
---|
109 | #define uhd_disable_disconnection_int() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_DDISCIEC)
|
---|
110 | #define Is_uhd_disconnection_int_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_DDISCIE))
|
---|
111 | #define uhd_ack_disconnection() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_DDISCIC)
|
---|
112 | #define Is_uhd_disconnection() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_DDISCI))
|
---|
113 | //! @}
|
---|
114 |
|
---|
115 | //! @name USB device speed control
|
---|
116 | //! @{
|
---|
117 | #define uhd_get_speed_mode() (Rd_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_SPEED_Msk))
|
---|
118 | #define Is_uhd_low_speed_mode() (uhd_get_speed_mode() == UOTGHS_SR_SPEED_LOW_SPEED)
|
---|
119 | #define Is_uhd_full_speed_mode() (uhd_get_speed_mode() == UOTGHS_SR_SPEED_FULL_SPEED)
|
---|
120 | #define Is_uhd_high_speed_mode() (uhd_get_speed_mode() == UOTGHS_SR_SPEED_HIGH_SPEED)
|
---|
121 | //! Enable high speed mode
|
---|
122 | # define uhd_enable_high_speed_mode() (Wr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SPDCONF_Msk, UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED))
|
---|
123 | //! Disable high speed mode
|
---|
124 | # define uhd_disable_high_speed_mode() (Wr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SPDCONF_Msk, UOTGHS_HSTCTRL_SPDCONF_FORCED_FS))
|
---|
125 | //! @}
|
---|
126 |
|
---|
127 | //! @name Bus events control
|
---|
128 | //! These macros manage the bus events: reset, SOF, resume, wakeup.
|
---|
129 | //! @{
|
---|
130 |
|
---|
131 | //! Initiates a reset event
|
---|
132 | //! @{
|
---|
133 | #define uhd_start_reset() (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
|
---|
134 | #define Is_uhd_starting_reset() (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
|
---|
135 | #define uhd_stop_reset() (Clr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
|
---|
136 |
|
---|
137 | #define uhd_enable_reset_sent_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RSTIES)
|
---|
138 | #define uhd_disable_reset_sent_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RSTIEC)
|
---|
139 | #define Is_uhd_reset_sent_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RSTIE))
|
---|
140 | #define uhd_ack_reset_sent() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RSTIC)
|
---|
141 | #define Is_uhd_reset_sent() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RSTI))
|
---|
142 | //! @}
|
---|
143 |
|
---|
144 | //! Initiates a SOF events
|
---|
145 | //! @{
|
---|
146 | #define uhd_enable_sof() (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
|
---|
147 | #define uhd_disable_sof() (Clr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
|
---|
148 | #define Is_uhd_sof_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
|
---|
149 | #define uhd_get_sof_number() ((UOTGHS->UOTGHS_HSTFNUM&UOTGHS_HSTFNUM_FNUM_Msk)>>UOTGHS_HSTFNUM_FNUM_Pos)
|
---|
150 | #define uhd_get_microsof_number() ((UOTGHS->UOTGHS_HSTFNUM&UOTGHS_HSTFNUM_MFNUM_Msk)>>UOTGHS_HSTFNUM_MFNUM_Pos)
|
---|
151 | #define uhd_get_frame_position() (Rd_bits(UOTGHS->UOTGHS_HSTFNUM, UOTGHS_HSTFNUM_FLENHIGH_Msk))
|
---|
152 | #define uhd_enable_sof_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_HSOFIES)
|
---|
153 | #define uhd_disable_sof_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_HSOFIEC)
|
---|
154 | #define Is_uhd_sof_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_HSOFIE))
|
---|
155 | #define uhd_ack_sof() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_HSOFIC)
|
---|
156 | #define Is_uhd_sof() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_HSOFI))
|
---|
157 | //! @}
|
---|
158 |
|
---|
159 | //! Initiates a resume event
|
---|
160 | //! It is called downstream resume event.
|
---|
161 | //! @{
|
---|
162 | #define uhd_send_resume() (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESUME))
|
---|
163 | #define Is_uhd_sending_resume() (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESUME))
|
---|
164 |
|
---|
165 | #define uhd_enable_downstream_resume_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RSMEDIES)
|
---|
166 | #define uhd_disable_downstream_resume_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RSMEDIEC)
|
---|
167 | #define Is_uhd_downstream_resume_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RSMEDIE))
|
---|
168 | #define uhd_ack_downstream_resume() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RSMEDIC)
|
---|
169 | #define Is_uhd_downstream_resume() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RSMEDI))
|
---|
170 | //! @}
|
---|
171 |
|
---|
172 | //! Detection of a wake-up event
|
---|
173 | //! A wake-up event is received when the host controller is in the suspend mode:
|
---|
174 | //! - and an upstream resume from the peripheral is detected.
|
---|
175 | //! - and a peripheral disconnection is detected.
|
---|
176 | //! @{
|
---|
177 | #define uhd_enable_wakeup_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_HWUPIES)
|
---|
178 | #define uhd_disable_wakeup_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_HWUPIEC)
|
---|
179 | #define Is_uhd_wakeup_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_HWUPIE))
|
---|
180 | #define uhd_ack_wakeup() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_HWUPIC)
|
---|
181 | #define Is_uhd_wakeup() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_HWUPI))
|
---|
182 |
|
---|
183 | #define uhd_enable_upstream_resume_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RXRSMIES)
|
---|
184 | #define uhd_disable_upstream_resume_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RXRSMIEC)
|
---|
185 | #define Is_uhd_upstream_resume_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RXRSMIE))
|
---|
186 | #define uhd_ack_upstream_resume() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RXRSMIC)
|
---|
187 | #define Is_uhd_upstream_resume() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RXRSMI))
|
---|
188 | //! @}
|
---|
189 | //! @}
|
---|
190 |
|
---|
191 |
|
---|
192 | //! @name Pipes management
|
---|
193 | //! @{
|
---|
194 |
|
---|
195 | //! USB address of pipes
|
---|
196 | //! @{
|
---|
197 | #define uhd_configure_address(p, addr) \
|
---|
198 | (Wr_bitfield((&UOTGHS->UOTGHS_HSTADDR1)[(p)>>2], \
|
---|
199 | UOTGHS_HSTADDR1_HSTADDRP0_Msk << (((p)&0x03)<<3), addr))
|
---|
200 | #define uhd_get_configured_address(p) \
|
---|
201 | (Rd_bitfield((&UOTGHS->UOTGHS_HSTADDR1)[(p)>>2], \
|
---|
202 | UOTGHS_HSTADDR1_HSTADDRP0_Msk << (((p)&0x03)<<3)))
|
---|
203 | //! @}
|
---|
204 |
|
---|
205 | //! Pipe enable
|
---|
206 | //! Enable, disable, reset, freeze
|
---|
207 | //! @{
|
---|
208 | #define uhd_enable_pipe(p) \
|
---|
209 | (Set_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
|
---|
210 | #define uhd_disable_pipe(p) \
|
---|
211 | (Clr_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
|
---|
212 | #define Is_uhd_pipe_enabled(p) \
|
---|
213 | (Tst_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
|
---|
214 | #define uhd_reset_pipe(p) \
|
---|
215 | (Set_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p))); \
|
---|
216 | (Clr_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
|
---|
217 | #define Is_uhd_resetting_pipe(p) \
|
---|
218 | (Tst_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
|
---|
219 | #define uhd_freeze_pipe(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_PFREEZES)
|
---|
220 | #define uhd_unfreeze_pipe(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_PFREEZEC)
|
---|
221 | #define Is_uhd_pipe_frozen(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_PFREEZE))
|
---|
222 | #define uhd_reset_data_toggle(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RSTDTS)
|
---|
223 | #define Is_uhd_data_toggle_reset(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RSTDT))
|
---|
224 | //! @}
|
---|
225 |
|
---|
226 | //! Pipe configuration
|
---|
227 | //! @{
|
---|
228 | #define uhd_configure_pipe_int_req_freq(p,freq) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_INTFRQ_Msk, (freq)))
|
---|
229 | #define uhd_get_pipe_int_req_freq(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_INTFRQ_Msk))
|
---|
230 | #define uhd_configure_pipe_endpoint_number(p,ep) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PEPNUM_Msk, (ep)))
|
---|
231 | #define uhd_get_pipe_endpoint_address(p) \
|
---|
232 | (uhd_is_pipe_in(p) ?\
|
---|
233 | (uhd_get_pipe_endpoint_number(p) | USB_EP_DIR_IN) :\
|
---|
234 | (uhd_get_pipe_endpoint_number(p) | USB_EP_DIR_OUT))
|
---|
235 | #define uhd_get_pipe_endpoint_number(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], (UOTGHS_HSTPIPCFG_PEPNUM_Msk)))
|
---|
236 | #define uhd_configure_pipe_type(p, type) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTYPE_Msk, type))
|
---|
237 | #define uhd_get_pipe_type(p) (Rd_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTYPE_Msk))
|
---|
238 | #define uhd_enable_pipe_bank_autoswitch(p) (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
|
---|
239 | #define uhd_disable_pipe_bank_autoswitch(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
|
---|
240 | #define Is_uhd_pipe_bank_autoswitch_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
|
---|
241 | #define uhd_configure_pipe_token(p, token) (Wr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTOKEN_Msk, token))
|
---|
242 | #define uhd_get_pipe_token(p) (Rd_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTOKEN_Msk))
|
---|
243 | #define uhd_is_pipe_in(p) (UOTGHS_HSTPIPCFG_PTOKEN_IN==uhd_get_pipe_token(p))
|
---|
244 | #define uhd_is_pipe_out(p) (UOTGHS_HSTPIPCFG_PTOKEN_OUT==uhd_get_pipe_token(p))
|
---|
245 | //! Bounds given integer size to allowed range and rounds it up to the nearest
|
---|
246 | //! available greater size, then applies register format of UOTGHS controller
|
---|
247 | //! for pipe size bit-field.
|
---|
248 | #define uhd_format_pipe_size(size) \
|
---|
249 | (32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)
|
---|
250 | #define uhd_configure_pipe_size(p,size) \
|
---|
251 | (Wr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PSIZE_Msk, uhd_format_pipe_size(size)))
|
---|
252 | #define uhd_get_pipe_size(p) (8<<((Rd_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], (UOTGHS_HSTPIPCFG_PSIZE_Msk)))>> UOTGHS_HSTPIPCFG_PSIZE_Pos))
|
---|
253 | #define uhd_configure_pipe_bank(p,bank) (Wr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PBK_Msk, (bank)))
|
---|
254 | #define uhd_get_pipe_bank(p) (Rd_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PBK_Msk))
|
---|
255 | #define uhd_allocate_memory(p) (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
|
---|
256 | #define uhd_unallocate_memory(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
|
---|
257 | #define Is_uhd_memory_allocated(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
|
---|
258 |
|
---|
259 | //! Enable PING management only available in HS mode
|
---|
260 | # define uhd_enable_ping(p) (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PINGEN))
|
---|
261 | //#endif
|
---|
262 | #define uhd_configure_pipe(p, freq, ep_num, type, token, size, bank, bank_switch) \
|
---|
263 | (UOTGHS->UOTGHS_HSTPIPCFG[p] = \
|
---|
264 | (bank)|\
|
---|
265 | ((uhd_format_pipe_size(size)<<UOTGHS_HSTPIPCFG_PSIZE_Pos)&UOTGHS_HSTPIPCFG_PSIZE_Msk)|\
|
---|
266 | ((token)&UOTGHS_HSTPIPCFG_PTOKEN_Msk)|\
|
---|
267 | ((type)&UOTGHS_HSTPIPCFG_PTYPE_Msk)|\
|
---|
268 | (((ep_num)<<UOTGHS_HSTPIPCFG_PEPNUM_Pos)&UOTGHS_HSTPIPCFG_PEPNUM_Msk)|\
|
---|
269 | bank_switch |\
|
---|
270 | (((freq)<<UOTGHS_HSTPIPCFG_INTFRQ_Pos)&UOTGHS_HSTPIPCFG_INTFRQ_Msk))
|
---|
271 |
|
---|
272 | #define Is_uhd_pipe_configured(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_CFGOK))
|
---|
273 | //! @}
|
---|
274 |
|
---|
275 | //! Pipe main interrupts management
|
---|
276 | //! @{
|
---|
277 | #define uhd_enable_pipe_interrupt(p) (UOTGHS->UOTGHS_HSTIER = (UOTGHS_HSTIER_PEP_0 << (p)))
|
---|
278 | #define uhd_disable_pipe_interrupt(p) (UOTGHS->UOTGHS_HSTIDR = (UOTGHS_HSTIDR_PEP_0 << (p)))
|
---|
279 | #define Is_uhd_pipe_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_PEP_0 << (p)))
|
---|
280 | #define Is_uhd_pipe_interrupt(p) (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_PEP_0 << (p)))
|
---|
281 | //! returns the lowest pipe number generating a pipe interrupt or UOTGHS_EPT_NUM if none
|
---|
282 | #define uhd_get_interrupt_pipe_number() \
|
---|
283 | (ctz(((UOTGHS->UOTGHS_HSTISR >> 8) & (UOTGHS->UOTGHS_HSTIMR >> 8)) | (1 << UOTGHS_EPT_NUM)))
|
---|
284 | //! @}
|
---|
285 |
|
---|
286 | //! Pipe overflow and underflow for isochronous and interrupt endpoints
|
---|
287 | //! @{
|
---|
288 | #define uhd_enable_overflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_OVERFIES)
|
---|
289 | #define uhd_disable_overflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_OVERFIEC)
|
---|
290 | #define Is_uhd_overflow_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_OVERFIE))
|
---|
291 | #define uhd_ack_overflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_OVERFIC)
|
---|
292 | #define Is_uhd_overflow(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_OVERFI))
|
---|
293 |
|
---|
294 | #define uhd_enable_underflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_UNDERFIES)
|
---|
295 | #define uhd_disable_underflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_UNDERFIEC)
|
---|
296 | #define Is_uhd_underflow_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_UNDERFIE))
|
---|
297 | #define uhd_ack_underflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_UNDERFIC)
|
---|
298 | #define Is_uhd_underflow(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_UNDERFI))
|
---|
299 | //! @}
|
---|
300 |
|
---|
301 | //! USB packet errors management
|
---|
302 | //! @{
|
---|
303 | #define uhd_enable_stall_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RXSTALLDES)
|
---|
304 | #define uhd_disable_stall_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_RXSTALLDEC)
|
---|
305 | #define Is_uhd_stall_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RXSTALLDE))
|
---|
306 | #define uhd_ack_stall(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_RXSTALLDIC)
|
---|
307 | #define Is_uhd_stall(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RXSTALLDI))
|
---|
308 |
|
---|
309 | #define uhd_enable_pipe_error_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_PERRES)
|
---|
310 | #define uhd_disable_pipe_error_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_PERREC)
|
---|
311 | #define Is_uhd_pipe_error_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_PERRE))
|
---|
312 | #define uhd_ack_all_errors(p) (UOTGHS->UOTGHS_HSTPIPERR[p] = 0UL)
|
---|
313 | #define Is_uhd_pipe_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_PERRI))
|
---|
314 | #define uhd_error_status(p) (UOTGHS->UOTGHS_HSTPIPERR[p])
|
---|
315 | #define Is_uhd_bad_data_toggle(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATATGL))
|
---|
316 | #define Is_uhd_data_pid_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATAPID))
|
---|
317 | #define Is_uhd_pid_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_PID))
|
---|
318 | #define Is_uhd_timeout_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_TIMEOUT))
|
---|
319 | #define Is_uhd_crc16_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_CRC16))
|
---|
320 | #define uhd_get_error_counter(p) (Rd_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_COUNTER))
|
---|
321 | //! @}
|
---|
322 |
|
---|
323 | //! Pipe data management
|
---|
324 | //! @{
|
---|
325 | #define uhd_data_toggle(p) (Rd_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_DTSEQ))
|
---|
326 |
|
---|
327 | #define uhd_enable_bank_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_NBUSYBKES)
|
---|
328 | #define uhd_disable_bank_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_NBUSYBKEC)
|
---|
329 | #define Is_uhd_bank_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_NBUSYBKE))
|
---|
330 | #define uhd_nb_busy_bank(p) (Rd_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_NBUSYBK_Msk))
|
---|
331 | #define uhd_current_bank(p) (Rd_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_CURRBK_Msk ))
|
---|
332 |
|
---|
333 | #define uhd_enable_short_packet_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_SHORTPACKETES)
|
---|
334 | #define uhd_disable_short_packet_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_SHORTPACKETIEC)
|
---|
335 | #define Is_uhd_short_packet_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_SHORTPACKETIE)) )
|
---|
336 | #define uhd_ack_short_packet(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_SHORTPACKETIC)
|
---|
337 | #define Is_uhd_short_packet(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_SHORTPACKETI))
|
---|
338 | #define uhd_byte_count(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_PBYCT_Msk))
|
---|
339 |
|
---|
340 | #define Is_uhd_fifocon(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_FIFOCON))
|
---|
341 | #define uhd_ack_fifocon(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_FIFOCONC)
|
---|
342 |
|
---|
343 | #define uhd_enable_setup_ready_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_TXSTPES)
|
---|
344 | #define uhd_disable_setup_ready_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_TXSTPEC)
|
---|
345 | #define Is_uhd_setup_ready_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_TXSTPE))
|
---|
346 | #define uhd_ack_setup_ready(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_TXSTPIC)
|
---|
347 | #define Is_uhd_setup_ready(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_TXSTPI))
|
---|
348 |
|
---|
349 | #define uhd_enable_in_received_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RXINES)
|
---|
350 | #define uhd_disable_in_received_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_RXINEC)
|
---|
351 | #define Is_uhd_in_received_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RXINE))
|
---|
352 | #define uhd_ack_in_received(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_RXINIC)
|
---|
353 | #define Is_uhd_in_received(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RXINI))
|
---|
354 |
|
---|
355 | #define uhd_enable_out_ready_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_TXOUTES)
|
---|
356 | #define uhd_disable_out_ready_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_TXOUTEC)
|
---|
357 | #define Is_uhd_out_ready_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_TXOUTE))
|
---|
358 | #define uhd_ack_out_ready(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_TXOUTIC)
|
---|
359 | #define Is_uhd_out_ready(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_TXOUTI))
|
---|
360 | #define uhd_raise_out_ready(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_TXOUTIS)
|
---|
361 |
|
---|
362 | #define uhd_enable_nak_received_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_NAKEDES)
|
---|
363 | #define uhd_disable_nak_received_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_NAKEDEC)
|
---|
364 | #define Is_uhd_nak_received_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_NAKEDE))
|
---|
365 | #define uhd_ack_nak_received(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_NAKEDIC)
|
---|
366 | #define Is_uhd_nak_received(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_NAKEDI))
|
---|
367 |
|
---|
368 | #define Is_uhd_read_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RWALL))
|
---|
369 | #define Is_uhd_write_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RWALL ))
|
---|
370 |
|
---|
371 | #define uhd_enable_continuous_in_mode(p) (Set_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
|
---|
372 | #define uhd_disable_continuous_in_mode(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
|
---|
373 | #define Is_uhd_continuous_in_mode_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
|
---|
374 |
|
---|
375 | #define uhd_in_request_number(p, in_num) (Set_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], (in_num)-1))
|
---|
376 | #define uhd_get_in_request_number(p) (((Rd_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INRQ_Msk))>>UOTGHS_HSTPIPINRQ_INRQ_Pos)+1)
|
---|
377 | //! @}
|
---|
378 |
|
---|
379 | //! Maximum transfer size on USB DMA
|
---|
380 | #define UHD_PIPE_MAX_TRANS 0x8000
|
---|
381 |
|
---|
382 | //! Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected pipe.
|
---|
383 | //! @param p Target Pipe number
|
---|
384 | //! @param scale Data scale in bits: 64, 32, 16 or 8
|
---|
385 | //! @return Volatile 64-, 32-, 16- or 8-bit data pointer to FIFO data register
|
---|
386 | //! @warning It is up to the user of this macro to make sure that all accesses
|
---|
387 | //! are aligned with their natural boundaries except 64-bit accesses which
|
---|
388 | //! require only 32-bit alignment.
|
---|
389 | //! @warning It is up to the user of this macro to make sure that used HSB
|
---|
390 | //! addresses are identical to the DPRAM internal pointer modulo 32 bits.
|
---|
391 | #define uhd_get_pipe_fifo_access(p, scale) \
|
---|
392 | (((volatile TPASTE2(U, scale) (*)[UHD_PIPE_MAX_TRANS / ((scale) / 8)])UOTGHS_RAM_ADDR)[(p)])
|
---|
393 |
|
---|
394 |
|
---|
395 | #ifdef __cplusplus
|
---|
396 | }
|
---|
397 | #endif
|
---|
398 |
|
---|
399 | #endif /* UOTGHS_HOST_H_INCLUDED */
|
---|