[175] | 1 | /*
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| 2 | Copyright (c) 2014 Arduino. All right reserved.
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| 3 |
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| 4 | This library is free software; you can redistribute it and/or
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| 5 | modify it under the terms of the GNU Lesser General Public
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| 6 | License as published by the Free Software Foundation; either
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| 7 | version 2.1 of the License, or (at your option) any later version.
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| 8 |
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| 9 | This library is distributed in the hope that it will be useful,
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| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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| 12 | See the GNU Lesser General Public License for more details.
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| 13 |
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| 14 | You should have received a copy of the GNU Lesser General Public
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| 15 | License along with this library; if not, write to the Free Software
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| 16 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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| 17 | */
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| 18 |
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[136] | 19 | #include "SERCOM.h"
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| 20 | #include "variant.h"
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| 21 |
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[175] | 22 |
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[136] | 23 | SERCOM::SERCOM(Sercom* s)
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| 24 | {
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[175] | 25 | sercom = s;
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[136] | 26 | }
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| 27 |
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| 28 | /* =========================
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| 29 | * ===== Sercom UART
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| 30 | * =========================
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| 31 | */
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| 32 | void SERCOM::initUART(SercomUartMode mode, SercomUartSampleRate sampleRate, uint32_t baudrate)
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| 33 | {
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[175] | 34 | initClockNVIC();
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[136] | 35 | resetUART();
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| 36 |
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| 37 | //Setting the CTRLA register
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| 38 | sercom->USART.CTRLA.reg = SERCOM_USART_CTRLA_MODE(mode) |
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| 39 | SERCOM_USART_CTRLA_SAMPR(sampleRate);
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| 40 |
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| 41 | //Setting the Interrupt register
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| 42 | sercom->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC | //Received complete
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| 43 | SERCOM_USART_INTENSET_ERROR; //All others errors
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| 44 |
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| 45 | if ( mode == UART_INT_CLOCK )
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| 46 | {
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[175] | 47 | uint16_t sampleRateValue;
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[136] | 48 |
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[175] | 49 | if (sampleRate == SAMPLE_RATE_x16) {
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| 50 | sampleRateValue = 16;
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| 51 | } else {
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| 52 | sampleRateValue = 8;
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[136] | 53 | }
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| 54 |
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[175] | 55 | // Asynchronous fractional mode (Table 24-2 in datasheet)
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| 56 | // BAUD = fref / (sampleRateValue * fbaud)
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| 57 | // (multiply by 8, to calculate fractional piece)
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| 58 | uint32_t baudTimes8 = (SystemCoreClock * 8) / (sampleRateValue * baudrate);
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| 59 |
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| 60 | sercom->USART.BAUD.FRAC.FP = (baudTimes8 % 8);
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| 61 | sercom->USART.BAUD.FRAC.BAUD = (baudTimes8 / 8);
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[136] | 62 | }
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| 63 | }
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| 64 | void SERCOM::initFrame(SercomUartCharSize charSize, SercomDataOrder dataOrder, SercomParityMode parityMode, SercomNumberStopBit nbStopBits)
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| 65 | {
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[175] | 66 | //Setting the CTRLA register
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| 67 | sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM( (parityMode == SERCOM_NO_PARITY ? 0 : 1) ) |
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| 68 | dataOrder << SERCOM_USART_CTRLA_DORD_Pos;
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[136] | 69 |
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[175] | 70 | //Setting the CTRLB register
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| 71 | sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(charSize) |
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| 72 | nbStopBits << SERCOM_USART_CTRLB_SBMODE_Pos |
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| 73 | (parityMode == SERCOM_NO_PARITY ? 0 : parityMode) << SERCOM_USART_CTRLB_PMODE_Pos; //If no parity use default value
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[136] | 74 | }
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| 75 |
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| 76 | void SERCOM::initPads(SercomUartTXPad txPad, SercomRXPad rxPad)
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| 77 | {
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[175] | 78 | //Setting the CTRLA register
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| 79 | sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(txPad) |
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| 80 | SERCOM_USART_CTRLA_RXPO(rxPad);
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[136] | 81 |
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| 82 | // Enable Transceiver and Receiver
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| 83 | sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN ;
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| 84 | }
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| 85 |
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| 86 | void SERCOM::resetUART()
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| 87 | {
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| 88 | // Start the Software Reset
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| 89 | sercom->USART.CTRLA.bit.SWRST = 1 ;
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| 90 |
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| 91 | while ( sercom->USART.CTRLA.bit.SWRST || sercom->USART.SYNCBUSY.bit.SWRST )
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| 92 | {
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| 93 | // Wait for both bits Software Reset from CTRLA and SYNCBUSY coming back to 0
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| 94 | }
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| 95 | }
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| 96 |
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| 97 | void SERCOM::enableUART()
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| 98 | {
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[175] | 99 | //Setting the enable bit to 1
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| 100 | sercom->USART.CTRLA.bit.ENABLE = 0x1u;
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[136] | 101 |
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[175] | 102 | //Wait for then enable bit from SYNCBUSY is equal to 0;
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| 103 | while(sercom->USART.SYNCBUSY.bit.ENABLE);
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[136] | 104 | }
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| 105 |
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| 106 | void SERCOM::flushUART()
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| 107 | {
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[175] | 108 | // Wait for transmission to complete
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| 109 | while(!sercom->USART.INTFLAG.bit.TXC);
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[136] | 110 | }
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| 111 |
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| 112 | void SERCOM::clearStatusUART()
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| 113 | {
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[175] | 114 | //Reset (with 0) the STATUS register
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| 115 | sercom->USART.STATUS.reg = SERCOM_USART_STATUS_RESETVALUE;
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[136] | 116 | }
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| 117 |
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| 118 | bool SERCOM::availableDataUART()
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| 119 | {
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[175] | 120 | //RXC : Receive Complete
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| 121 | return sercom->USART.INTFLAG.bit.RXC;
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[136] | 122 | }
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| 123 |
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[175] | 124 | bool SERCOM::isUARTError()
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| 125 | {
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| 126 | return sercom->USART.INTFLAG.bit.ERROR;
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| 127 | }
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| 128 |
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| 129 | void SERCOM::acknowledgeUARTError()
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| 130 | {
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| 131 | sercom->USART.INTFLAG.bit.ERROR = 1;
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| 132 | }
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| 133 |
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[136] | 134 | bool SERCOM::isBufferOverflowErrorUART()
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| 135 | {
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[175] | 136 | //BUFOVF : Buffer Overflow
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| 137 | return sercom->USART.STATUS.bit.BUFOVF;
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[136] | 138 | }
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| 139 |
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| 140 | bool SERCOM::isFrameErrorUART()
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| 141 | {
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[175] | 142 | //FERR : Frame Error
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| 143 | return sercom->USART.STATUS.bit.FERR;
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[136] | 144 | }
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| 145 |
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| 146 | bool SERCOM::isParityErrorUART()
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| 147 | {
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[175] | 148 | //PERR : Parity Error
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| 149 | return sercom->USART.STATUS.bit.PERR;
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[136] | 150 | }
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| 151 |
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| 152 | bool SERCOM::isDataRegisterEmptyUART()
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| 153 | {
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[175] | 154 | //DRE : Data Register Empty
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| 155 | return sercom->USART.INTFLAG.bit.DRE;
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[136] | 156 | }
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| 157 |
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| 158 | uint8_t SERCOM::readDataUART()
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| 159 | {
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[175] | 160 | return sercom->USART.DATA.bit.DATA;
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[136] | 161 | }
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| 162 |
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| 163 | int SERCOM::writeDataUART(uint8_t data)
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| 164 | {
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[175] | 165 | // Wait for data register to be empty
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| 166 | while(!isDataRegisterEmptyUART());
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[136] | 167 |
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[175] | 168 | //Put data into DATA register
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| 169 | sercom->USART.DATA.reg = (uint16_t)data;
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| 170 | return 1;
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[136] | 171 | }
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| 172 |
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| 173 | /* =========================
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| 174 | * ===== Sercom SPI
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| 175 | * =========================
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| 176 | */
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| 177 | void SERCOM::initSPI(SercomSpiTXPad mosi, SercomRXPad miso, SercomSpiCharSize charSize, SercomDataOrder dataOrder)
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| 178 | {
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[175] | 179 | resetSPI();
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| 180 | initClockNVIC();
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| 181 |
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| 182 | //Setting the CTRLA register
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| 183 | sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE_SPI_MASTER |
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| 184 | SERCOM_SPI_CTRLA_DOPO(mosi) |
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| 185 | SERCOM_SPI_CTRLA_DIPO(miso) |
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| 186 | dataOrder << SERCOM_SPI_CTRLA_DORD_Pos;
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| 187 |
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| 188 | //Setting the CTRLB register
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| 189 | sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(charSize) |
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| 190 | SERCOM_SPI_CTRLB_RXEN; //Active the SPI receiver.
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| 191 |
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| 192 |
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| 193 | }
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| 194 |
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| 195 | void SERCOM::initSPIslave(SercomSpiTXPad mosi, SercomRXPad miso, SercomSpiCharSize charSize, SercomDataOrder dataOrder)
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| 196 | {
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[136] | 197 | resetSPI();
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| 198 | initClockNVIC();
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| 199 |
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[175] | 200 | sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE_SPI_SLAVE |
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| 201 | SERCOM_SPI_CTRLA_DOPO(mosi) | //provo a modificare
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| 202 | SERCOM_SPI_CTRLA_DIPO(miso) | //provo a modificare
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| 203 | dataOrder << SERCOM_SPI_CTRLA_DORD_Pos;
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[136] | 204 |
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| 205 | sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(charSize) |
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[175] | 206 | SERCOM_SPI_CTRLB_RXEN; //Active the SPI receiver.
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| 207 |
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[136] | 208 | }
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| 209 |
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| 210 | void SERCOM::initSPIClock(SercomSpiClockMode clockMode, uint32_t baudrate)
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| 211 | {
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[175] | 212 | //Extract data from clockMode
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| 213 | int cpha, cpol;
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[136] | 214 |
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[175] | 215 | if((clockMode & (0x1ul)) == 0 )
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| 216 | cpha = 0;
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| 217 | else
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| 218 | cpha = 1;
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[136] | 219 |
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[175] | 220 | if((clockMode & (0x2ul)) == 0)
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| 221 | cpol = 0;
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| 222 | else
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| 223 | cpol = 1;
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[136] | 224 |
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[175] | 225 | //Setting the CTRLA register
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| 226 | sercom->SPI.CTRLA.reg |= ( cpha << SERCOM_SPI_CTRLA_CPHA_Pos ) |
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| 227 | ( cpol << SERCOM_SPI_CTRLA_CPOL_Pos );
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[136] | 228 |
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[175] | 229 | //Synchronous arithmetic
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| 230 | sercom->SPI.BAUD.reg = calculateBaudrateSynchronous(baudrate);
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[136] | 231 | }
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| 232 |
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| 233 | void SERCOM::resetSPI()
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| 234 | {
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[175] | 235 | //Setting the Software Reset bit to 1
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| 236 | sercom->SPI.CTRLA.bit.SWRST = 1;
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[136] | 237 |
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[175] | 238 | //Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
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| 239 | while(sercom->SPI.CTRLA.bit.SWRST || sercom->SPI.SYNCBUSY.bit.SWRST);
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[136] | 240 | }
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| 241 |
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| 242 | void SERCOM::enableSPI()
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| 243 | {
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[175] | 244 | //Setting the enable bit to 1
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| 245 | sercom->SPI.CTRLA.bit.ENABLE = 1;
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[136] | 246 |
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[175] | 247 | while(sercom->SPI.SYNCBUSY.bit.ENABLE)
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[136] | 248 | {
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| 249 | //Waiting then enable bit from SYNCBUSY is equal to 0;
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| 250 | }
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| 251 | }
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| 252 |
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| 253 | void SERCOM::disableSPI()
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| 254 | {
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[175] | 255 | //Setting the enable bit to 0
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| 256 | sercom->SPI.CTRLA.bit.ENABLE = 0;
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[136] | 257 |
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[175] | 258 | while(sercom->SPI.SYNCBUSY.bit.ENABLE)
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[136] | 259 | {
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| 260 | //Waiting then enable bit from SYNCBUSY is equal to 0;
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| 261 | }
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| 262 | }
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| 263 |
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| 264 | void SERCOM::setDataOrderSPI(SercomDataOrder dataOrder)
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| 265 | {
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[175] | 266 | //Register enable-protected
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| 267 | disableSPI();
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[136] | 268 |
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[175] | 269 | sercom->SPI.CTRLA.bit.DORD = dataOrder;
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[136] | 270 |
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[175] | 271 | enableSPI();
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[136] | 272 | }
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| 273 |
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[175] | 274 | SercomDataOrder SERCOM::getDataOrderSPI()
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[136] | 275 | {
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[175] | 276 | return (sercom->SPI.CTRLA.bit.DORD ? LSB_FIRST : MSB_FIRST);
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| 277 | }
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[136] | 278 |
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[175] | 279 | void SERCOM::setBaudrateSPI(uint16_t divider)
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| 280 | {
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| 281 | //Can't divide by 0
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| 282 | if(divider == 0)
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| 283 | return;
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[136] | 284 |
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[175] | 285 | //Register enable-protected
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| 286 | disableSPI();
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[136] | 287 |
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[175] | 288 | sercom->SPI.BAUD.reg = calculateBaudrateSynchronous( SERCOM_FREQ_REF / divider );
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| 289 |
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| 290 | enableSPI();
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[136] | 291 | }
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| 292 |
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| 293 | void SERCOM::setClockModeSPI(SercomSpiClockMode clockMode)
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| 294 | {
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[175] | 295 | int cpha, cpol;
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| 296 | if((clockMode & (0x1ul)) == 0)
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| 297 | cpha = 0;
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| 298 | else
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| 299 | cpha = 1;
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[136] | 300 |
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[175] | 301 | if((clockMode & (0x2ul)) == 0)
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| 302 | cpol = 0;
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| 303 | else
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| 304 | cpol = 1;
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[136] | 305 |
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[175] | 306 | //Register enable-protected
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| 307 | disableSPI();
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[136] | 308 |
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[175] | 309 | sercom->SPI.CTRLA.bit.CPOL = cpol;
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| 310 | sercom->SPI.CTRLA.bit.CPHA = cpha;
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[136] | 311 |
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[175] | 312 | enableSPI();
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[136] | 313 | }
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[175] | 314 |
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[136] | 315 | void SERCOM::writeDataSPI(uint8_t data)
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| 316 | {
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| 317 | while( sercom->SPI.INTFLAG.bit.DRE == 0 )
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| 318 | {
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| 319 | // Waiting Data Registry Empty
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| 320 | }
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[175] | 321 | sercom->SPI.DATA.bit.DATA = data; // Writing data into Data register
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[136] | 322 |
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| 323 | while( sercom->SPI.INTFLAG.bit.TXC == 0 || sercom->SPI.INTFLAG.bit.DRE == 0 )
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| 324 | {
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| 325 | // Waiting Complete Transmission
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| 326 | }
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| 327 | }
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| 328 |
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| 329 | uint16_t SERCOM::readDataSPI()
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| 330 | {
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| 331 | while( sercom->SPI.INTFLAG.bit.DRE == 0 || sercom->SPI.INTFLAG.bit.RXC == 0 )
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| 332 | {
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| 333 | // Waiting Complete Reception
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| 334 | }
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| 335 |
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[175] | 336 | return sercom->SPI.DATA.bit.DATA; // Reading data
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[136] | 337 | }
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| 338 |
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| 339 | bool SERCOM::isBufferOverflowErrorSPI()
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| 340 | {
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[175] | 341 | return sercom->SPI.STATUS.bit.BUFOVF;
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[136] | 342 | }
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| 343 |
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| 344 | bool SERCOM::isDataRegisterEmptySPI()
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| 345 | {
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[175] | 346 | //DRE : Data Register Empty
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| 347 | return sercom->SPI.INTFLAG.bit.DRE;
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[136] | 348 | }
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| 349 |
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[175] | 350 | //bool SERCOM::isTransmitCompleteSPI()
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| 351 | //{
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| 352 | // //TXC : Transmit complete
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| 353 | // return sercom->SPI.INTFLAG.bit.TXC;
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| 354 | //}
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| 355 | //
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| 356 | //bool SERCOM::isReceiveCompleteSPI()
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| 357 | //{
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| 358 | // //RXC : Receive complete
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| 359 | // return sercom->SPI.INTFLAG.bit.RXC;
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| 360 | //}
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| 361 |
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[136] | 362 | uint8_t SERCOM::calculateBaudrateSynchronous(uint32_t baudrate)
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| 363 | {
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[175] | 364 | return SERCOM_FREQ_REF / (2 * baudrate) - 1;
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[136] | 365 | }
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| 366 |
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| 367 |
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| 368 | /* =========================
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| 369 | * ===== Sercom WIRE
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| 370 | * =========================
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[175] | 371 | */
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[136] | 372 | void SERCOM::resetWIRE()
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| 373 | {
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[175] | 374 | //I2CM OR I2CS, no matter SWRST is the same bit.
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[136] | 375 |
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[175] | 376 | //Setting the Software bit to 1
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| 377 | sercom->I2CM.CTRLA.bit.SWRST = 1;
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[136] | 378 |
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[175] | 379 | //Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
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| 380 | while(sercom->I2CM.CTRLA.bit.SWRST || sercom->I2CM.SYNCBUSY.bit.SWRST);
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[136] | 381 | }
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| 382 |
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| 383 | void SERCOM::enableWIRE()
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| 384 | {
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| 385 | // I2C Master and Slave modes share the ENABLE bit function.
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| 386 |
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| 387 | // Enable the I²C master mode
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| 388 | sercom->I2CM.CTRLA.bit.ENABLE = 1 ;
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| 389 |
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| 390 | while ( sercom->I2CM.SYNCBUSY.bit.ENABLE != 0 )
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| 391 | {
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| 392 | // Waiting the enable bit from SYNCBUSY is equal to 0;
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| 393 | }
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| 394 |
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| 395 | // Setting bus idle mode
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| 396 | sercom->I2CM.STATUS.bit.BUSSTATE = 1 ;
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| 397 |
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| 398 | while ( sercom->I2CM.SYNCBUSY.bit.SYSOP != 0 )
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| 399 | {
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| 400 | // Wait the SYSOP bit from SYNCBUSY coming back to 0
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| 401 | }
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| 402 | }
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| 403 |
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| 404 | void SERCOM::disableWIRE()
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| 405 | {
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| 406 | // I2C Master and Slave modes share the ENABLE bit function.
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| 407 |
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| 408 | // Enable the I²C master mode
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| 409 | sercom->I2CM.CTRLA.bit.ENABLE = 0 ;
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| 410 |
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| 411 | while ( sercom->I2CM.SYNCBUSY.bit.ENABLE != 0 )
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| 412 | {
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| 413 | // Waiting the enable bit from SYNCBUSY is equal to 0;
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| 414 | }
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| 415 | }
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| 416 |
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| 417 | void SERCOM::initSlaveWIRE( uint8_t ucAddress )
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| 418 | {
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| 419 | // Initialize the peripheral clock and interruption
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| 420 | initClockNVIC() ;
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| 421 | resetWIRE() ;
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| 422 |
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| 423 | // Set slave mode
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| 424 | sercom->I2CS.CTRLA.bit.MODE = I2C_SLAVE_OPERATION ;
|
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| 425 |
|
---|
| 426 | sercom->I2CS.ADDR.reg = SERCOM_I2CS_ADDR_ADDR( ucAddress & 0x7Ful ) | // 0x7F, select only 7 bits
|
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[175] | 427 | SERCOM_I2CS_ADDR_ADDRMASK( 0x3FFul ) ; // 0x3FF all bits set
|
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[136] | 428 |
|
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| 429 | // Set the interrupt register
|
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[175] | 430 | sercom->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC | // Stop
|
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| 431 | SERCOM_I2CS_INTENSET_AMATCH | // Address Match
|
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| 432 | SERCOM_I2CS_INTENSET_DRDY ; // Data Ready
|
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[136] | 433 |
|
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| 434 | while ( sercom->I2CM.SYNCBUSY.bit.SYSOP != 0 )
|
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| 435 | {
|
---|
| 436 | // Wait the SYSOP bit from SYNCBUSY to come back to 0
|
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| 437 | }
|
---|
| 438 | }
|
---|
| 439 |
|
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| 440 | void SERCOM::initMasterWIRE( uint32_t baudrate )
|
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| 441 | {
|
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| 442 | // Initialize the peripheral clock and interruption
|
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| 443 | initClockNVIC() ;
|
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| 444 |
|
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| 445 | resetWIRE() ;
|
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| 446 |
|
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| 447 | // Set master mode and enable SCL Clock Stretch mode (stretch after ACK bit)
|
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[175] | 448 | sercom->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_MODE( I2C_MASTER_OPERATION )/* |
|
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| 449 | SERCOM_I2CM_CTRLA_SCLSM*/ ;
|
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[136] | 450 |
|
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| 451 | // Enable Smart mode and Quick Command
|
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[175] | 452 | //sercom->I2CM.CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN /*| SERCOM_I2CM_CTRLB_QCEN*/ ;
|
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[136] | 453 |
|
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[175] | 454 |
|
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[136] | 455 | // Enable all interrupts
|
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[175] | 456 | // sercom->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB | SERCOM_I2CM_INTENSET_ERROR ;
|
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[136] | 457 |
|
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| 458 | // Synchronous arithmetic baudrate
|
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| 459 | sercom->I2CM.BAUD.bit.BAUD = SystemCoreClock / ( 2 * baudrate) - 1 ;
|
---|
| 460 | }
|
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| 461 |
|
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| 462 | void SERCOM::prepareNackBitWIRE( void )
|
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| 463 | {
|
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[175] | 464 | if(isMasterWIRE()) {
|
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| 465 | // Send a NACK
|
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| 466 | sercom->I2CM.CTRLB.bit.ACKACT = 1;
|
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| 467 | } else {
|
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| 468 | sercom->I2CS.CTRLB.bit.ACKACT = 1;
|
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| 469 | }
|
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[136] | 470 | }
|
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| 471 |
|
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| 472 | void SERCOM::prepareAckBitWIRE( void )
|
---|
| 473 | {
|
---|
[175] | 474 | if(isMasterWIRE()) {
|
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| 475 | // Send an ACK
|
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| 476 | sercom->I2CM.CTRLB.bit.ACKACT = 0;
|
---|
| 477 | } else {
|
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| 478 | sercom->I2CS.CTRLB.bit.ACKACT = 0;
|
---|
| 479 | }
|
---|
[136] | 480 | }
|
---|
| 481 |
|
---|
[175] | 482 | void SERCOM::prepareCommandBitsWire(uint8_t cmd)
|
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[136] | 483 | {
|
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[175] | 484 | if(isMasterWIRE()) {
|
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| 485 | sercom->I2CM.CTRLB.bit.CMD = cmd;
|
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[136] | 486 |
|
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[175] | 487 | while(sercom->I2CM.SYNCBUSY.bit.SYSOP)
|
---|
| 488 | {
|
---|
| 489 | // Waiting for synchronization
|
---|
| 490 | }
|
---|
| 491 | } else {
|
---|
| 492 | sercom->I2CS.CTRLB.bit.CMD = cmd;
|
---|
[136] | 493 | }
|
---|
| 494 | }
|
---|
| 495 |
|
---|
| 496 | bool SERCOM::startTransmissionWIRE(uint8_t address, SercomWireReadWriteFlag flag)
|
---|
| 497 | {
|
---|
| 498 | // 7-bits address + 1-bits R/W
|
---|
| 499 | address = (address << 0x1ul) | flag;
|
---|
| 500 |
|
---|
| 501 |
|
---|
[175] | 502 | // Wait idle or owner bus mode
|
---|
| 503 | while ( !isBusIdleWIRE() && !isBusOwnerWIRE() );
|
---|
| 504 |
|
---|
[136] | 505 | // Send start and address
|
---|
| 506 | sercom->I2CM.ADDR.bit.ADDR = address;
|
---|
[175] | 507 |
|
---|
[136] | 508 |
|
---|
| 509 | // Address Transmitted
|
---|
| 510 | if ( flag == WIRE_WRITE_FLAG ) // Write mode
|
---|
| 511 | {
|
---|
| 512 | while( !sercom->I2CM.INTFLAG.bit.MB )
|
---|
| 513 | {
|
---|
| 514 | // Wait transmission complete
|
---|
| 515 | }
|
---|
| 516 | }
|
---|
| 517 | else // Read mode
|
---|
| 518 | {
|
---|
| 519 | while( !sercom->I2CM.INTFLAG.bit.SB )
|
---|
| 520 | {
|
---|
[175] | 521 | // If the slave NACKS the address, the MB bit will be set.
|
---|
| 522 | // In that case, send a stop condition and return false.
|
---|
| 523 | if (sercom->I2CM.INTFLAG.bit.MB) {
|
---|
| 524 | sercom->I2CM.CTRLB.bit.CMD = 3; // Stop condition
|
---|
| 525 | return false;
|
---|
| 526 | }
|
---|
[136] | 527 | // Wait transmission complete
|
---|
| 528 | }
|
---|
| 529 |
|
---|
| 530 | // Clean the 'Slave on Bus' flag, for further usage.
|
---|
| 531 | //sercom->I2CM.INTFLAG.bit.SB = 0x1ul;
|
---|
| 532 | }
|
---|
| 533 |
|
---|
| 534 |
|
---|
| 535 | //ACK received (0: ACK, 1: NACK)
|
---|
| 536 | if(sercom->I2CM.STATUS.bit.RXNACK)
|
---|
| 537 | {
|
---|
| 538 | return false;
|
---|
| 539 | }
|
---|
| 540 | else
|
---|
| 541 | {
|
---|
| 542 | return true;
|
---|
| 543 | }
|
---|
| 544 | }
|
---|
| 545 |
|
---|
| 546 | bool SERCOM::sendDataMasterWIRE(uint8_t data)
|
---|
| 547 | {
|
---|
[175] | 548 | //Send data
|
---|
| 549 | sercom->I2CM.DATA.bit.DATA = data;
|
---|
[136] | 550 |
|
---|
[175] | 551 | //Wait transmission successful
|
---|
| 552 | while(!sercom->I2CM.INTFLAG.bit.MB) {
|
---|
[136] | 553 |
|
---|
[175] | 554 | // If a bus error occurs, the MB bit may never be set.
|
---|
| 555 | // Check the bus error bit and bail if it's set.
|
---|
| 556 | if (sercom->I2CM.STATUS.bit.BUSERR) {
|
---|
| 557 | return false;
|
---|
| 558 | }
|
---|
| 559 | }
|
---|
| 560 |
|
---|
| 561 | //Problems on line? nack received?
|
---|
| 562 | if(sercom->I2CM.STATUS.bit.RXNACK)
|
---|
| 563 | return false;
|
---|
| 564 | else
|
---|
| 565 | return true;
|
---|
[136] | 566 | }
|
---|
| 567 |
|
---|
| 568 | bool SERCOM::sendDataSlaveWIRE(uint8_t data)
|
---|
| 569 | {
|
---|
[175] | 570 | //Send data
|
---|
| 571 | sercom->I2CS.DATA.bit.DATA = data;
|
---|
[136] | 572 |
|
---|
[175] | 573 | //Wait data transmission successful
|
---|
| 574 | while(!sercom->I2CS.INTFLAG.bit.DRDY);
|
---|
[136] | 575 |
|
---|
[175] | 576 | //Problems on line? nack received?
|
---|
| 577 | if(sercom->I2CS.STATUS.bit.RXNACK)
|
---|
| 578 | return false;
|
---|
| 579 | else
|
---|
| 580 | return true;
|
---|
[136] | 581 | }
|
---|
| 582 |
|
---|
| 583 | bool SERCOM::isMasterWIRE( void )
|
---|
| 584 | {
|
---|
[175] | 585 | return sercom->I2CS.CTRLA.bit.MODE == I2C_MASTER_OPERATION;
|
---|
[136] | 586 | }
|
---|
| 587 |
|
---|
| 588 | bool SERCOM::isSlaveWIRE( void )
|
---|
| 589 | {
|
---|
[175] | 590 | return sercom->I2CS.CTRLA.bit.MODE == I2C_SLAVE_OPERATION;
|
---|
[136] | 591 | }
|
---|
| 592 |
|
---|
| 593 | bool SERCOM::isBusIdleWIRE( void )
|
---|
| 594 | {
|
---|
[175] | 595 | return sercom->I2CM.STATUS.bit.BUSSTATE == WIRE_IDLE_STATE;
|
---|
[136] | 596 | }
|
---|
| 597 |
|
---|
[175] | 598 | bool SERCOM::isBusOwnerWIRE( void )
|
---|
| 599 | {
|
---|
| 600 | return sercom->I2CM.STATUS.bit.BUSSTATE == WIRE_OWNER_STATE;
|
---|
| 601 | }
|
---|
| 602 |
|
---|
[136] | 603 | bool SERCOM::isDataReadyWIRE( void )
|
---|
| 604 | {
|
---|
[175] | 605 | return sercom->I2CS.INTFLAG.bit.DRDY;
|
---|
[136] | 606 | }
|
---|
| 607 |
|
---|
| 608 | bool SERCOM::isStopDetectedWIRE( void )
|
---|
| 609 | {
|
---|
[175] | 610 | return sercom->I2CS.INTFLAG.bit.PREC;
|
---|
[136] | 611 | }
|
---|
| 612 |
|
---|
| 613 | bool SERCOM::isRestartDetectedWIRE( void )
|
---|
| 614 | {
|
---|
[175] | 615 | return sercom->I2CS.STATUS.bit.SR;
|
---|
[136] | 616 | }
|
---|
| 617 |
|
---|
| 618 | bool SERCOM::isAddressMatch( void )
|
---|
| 619 | {
|
---|
[175] | 620 | return sercom->I2CS.INTFLAG.bit.AMATCH;
|
---|
[136] | 621 | }
|
---|
| 622 |
|
---|
| 623 | bool SERCOM::isMasterReadOperationWIRE( void )
|
---|
| 624 | {
|
---|
| 625 | return sercom->I2CS.STATUS.bit.DIR;
|
---|
| 626 | }
|
---|
| 627 |
|
---|
| 628 | bool SERCOM::isRXNackReceivedWIRE( void )
|
---|
| 629 | {
|
---|
| 630 | return sercom->I2CM.STATUS.bit.RXNACK;
|
---|
| 631 | }
|
---|
| 632 |
|
---|
| 633 | int SERCOM::availableWIRE( void )
|
---|
| 634 | {
|
---|
[175] | 635 | if(isMasterWIRE())
|
---|
| 636 | return sercom->I2CM.INTFLAG.bit.SB;
|
---|
| 637 | else
|
---|
| 638 | return sercom->I2CS.INTFLAG.bit.DRDY;
|
---|
[136] | 639 | }
|
---|
| 640 |
|
---|
| 641 | uint8_t SERCOM::readDataWIRE( void )
|
---|
| 642 | {
|
---|
| 643 | if(isMasterWIRE())
|
---|
| 644 | {
|
---|
| 645 | while( sercom->I2CM.INTFLAG.bit.SB == 0 )
|
---|
| 646 | {
|
---|
| 647 | // Waiting complete receive
|
---|
| 648 | }
|
---|
| 649 |
|
---|
| 650 | return sercom->I2CM.DATA.bit.DATA ;
|
---|
| 651 | }
|
---|
| 652 | else
|
---|
| 653 | {
|
---|
| 654 | return sercom->I2CS.DATA.reg ;
|
---|
| 655 | }
|
---|
| 656 | }
|
---|
| 657 |
|
---|
| 658 |
|
---|
| 659 | void SERCOM::initClockNVIC( void )
|
---|
| 660 | {
|
---|
[175] | 661 | uint8_t clockId = 0;
|
---|
| 662 | IRQn_Type IdNvic=PendSV_IRQn ; // Dummy init to intercept potential error later
|
---|
[136] | 663 |
|
---|
[175] | 664 | if(sercom == SERCOM0)
|
---|
| 665 | {
|
---|
| 666 | clockId = GCM_SERCOM0_CORE;
|
---|
| 667 | IdNvic = SERCOM0_IRQn;
|
---|
| 668 | }
|
---|
| 669 | else if(sercom == SERCOM1)
|
---|
| 670 | {
|
---|
| 671 | clockId = GCM_SERCOM1_CORE;
|
---|
| 672 | IdNvic = SERCOM1_IRQn;
|
---|
| 673 | }
|
---|
| 674 | else if(sercom == SERCOM2)
|
---|
| 675 | {
|
---|
| 676 | clockId = GCM_SERCOM2_CORE;
|
---|
| 677 | IdNvic = SERCOM2_IRQn;
|
---|
| 678 | }
|
---|
| 679 | else if(sercom == SERCOM3)
|
---|
| 680 | {
|
---|
| 681 | clockId = GCM_SERCOM3_CORE;
|
---|
| 682 | IdNvic = SERCOM3_IRQn;
|
---|
| 683 | }
|
---|
| 684 | else if(sercom == SERCOM4)
|
---|
| 685 | {
|
---|
| 686 | clockId = GCM_SERCOM4_CORE;
|
---|
| 687 | IdNvic = SERCOM4_IRQn;
|
---|
| 688 | }
|
---|
| 689 | else if(sercom == SERCOM5)
|
---|
| 690 | {
|
---|
| 691 | clockId = GCM_SERCOM5_CORE;
|
---|
| 692 | IdNvic = SERCOM5_IRQn;
|
---|
| 693 | }
|
---|
[136] | 694 |
|
---|
[175] | 695 | if ( IdNvic == PendSV_IRQn )
|
---|
| 696 | {
|
---|
| 697 | // We got a problem here
|
---|
| 698 | return ;
|
---|
| 699 | }
|
---|
[136] | 700 |
|
---|
[175] | 701 | // Setting NVIC
|
---|
| 702 | NVIC_EnableIRQ(IdNvic);
|
---|
| 703 | NVIC_SetPriority (IdNvic, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority */
|
---|
[136] | 704 |
|
---|
[175] | 705 | //Setting clock
|
---|
| 706 | GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( clockId ) | // Generic Clock 0 (SERCOMx)
|
---|
| 707 | GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
|
---|
| 708 | GCLK_CLKCTRL_CLKEN ;
|
---|
[136] | 709 |
|
---|
[175] | 710 | while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
|
---|
| 711 | {
|
---|
| 712 | /* Wait for synchronization */
|
---|
| 713 | }
|
---|
[136] | 714 | }
|
---|