[136] | 1 | #include "SERCOM.h"
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| 2 | #include "variant.h"
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| 3 |
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| 4 | SERCOM::SERCOM(Sercom* s)
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| 5 | {
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| 6 | sercom = s;
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| 7 | }
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| 8 |
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| 9 | /* =========================
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| 10 | * ===== Sercom UART
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| 11 | * =========================
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| 12 | */
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| 13 | void SERCOM::initUART(SercomUartMode mode, SercomUartSampleRate sampleRate, uint32_t baudrate)
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| 14 | {
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| 15 | resetUART();
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| 16 | initClockNVIC();
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| 17 |
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| 18 | //Setting the CTRLA register
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| 19 | sercom->USART.CTRLA.reg = SERCOM_USART_CTRLA_MODE(mode) |
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| 20 | SERCOM_USART_CTRLA_SAMPR(sampleRate);
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| 21 |
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| 22 | //Setting the Interrupt register
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| 23 | sercom->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC | //Received complete
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| 24 | SERCOM_USART_INTENSET_ERROR; //All others errors
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| 25 |
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| 26 | if ( mode == UART_INT_CLOCK )
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| 27 | {
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| 28 | uint16_t sampleRateValue ;
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| 29 |
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| 30 | if ( sampleRate == SAMPLE_RATE_x16 )
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| 31 | {
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| 32 | sampleRateValue = 16 ;
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| 33 | }
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| 34 | else
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| 35 | {
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| 36 | if ( sampleRate == SAMPLE_RATE_x8 )
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| 37 | {
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| 38 | sampleRateValue = 8 ;
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| 39 | }
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| 40 | else
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| 41 | {
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| 42 | sampleRateValue = 3 ;
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| 43 | }
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| 44 | }
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| 45 |
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| 46 | // Asynchronous arithmetic mode
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| 47 | // 65535 * ( 1 - sampleRateValue * baudrate / SystemCoreClock);
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| 48 | // 65535 - 65535 * (sampleRateValue * baudrate / SystemCoreClock));
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| 49 | sercom->USART.BAUD.reg = 65535.0f * ( 1.0f - (float)(sampleRateValue) * (float)(baudrate) / (float)(SystemCoreClock));
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| 50 | }
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| 51 | }
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| 52 | void SERCOM::initFrame(SercomUartCharSize charSize, SercomDataOrder dataOrder, SercomParityMode parityMode, SercomNumberStopBit nbStopBits)
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| 53 | {
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| 54 | //Setting the CTRLA register
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| 55 | sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM( (parityMode == SERCOM_NO_PARITY ? 0 : 1) ) |
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| 56 | dataOrder << SERCOM_USART_CTRLA_DORD_Pos;
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| 57 |
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| 58 | //Setting the CTRLB register
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| 59 | sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(charSize) |
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| 60 | nbStopBits << SERCOM_USART_CTRLB_SBMODE_Pos |
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| 61 | (parityMode == SERCOM_NO_PARITY ? 0 : parityMode) << SERCOM_USART_CTRLB_PMODE_Pos; //If no parity use default value
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| 62 | }
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| 63 |
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| 64 | void SERCOM::initPads(SercomUartTXPad txPad, SercomRXPad rxPad)
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| 65 | {
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| 66 | //Setting the CTRLA register
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| 67 | sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(txPad) |
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| 68 | SERCOM_USART_CTRLA_RXPO(rxPad);
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| 69 |
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| 70 | // Enable Transceiver and Receiver
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| 71 | sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN ;
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| 72 | }
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| 73 |
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| 74 | void SERCOM::resetUART()
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| 75 | {
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| 76 | // Start the Software Reset
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| 77 | sercom->USART.CTRLA.bit.SWRST = 1 ;
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| 78 |
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| 79 | while ( sercom->USART.CTRLA.bit.SWRST || sercom->USART.SYNCBUSY.bit.SWRST )
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| 80 | {
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| 81 | // Wait for both bits Software Reset from CTRLA and SYNCBUSY coming back to 0
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| 82 | }
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| 83 | }
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| 84 |
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| 85 | void SERCOM::enableUART()
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| 86 | {
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| 87 | //Setting the enable bit to 1
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| 88 | sercom->USART.CTRLA.bit.ENABLE = 0x1u;
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| 89 |
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| 90 | //Wait for then enable bit from SYNCBUSY is equal to 0;
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| 91 | while(sercom->USART.SYNCBUSY.bit.ENABLE);
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| 92 | }
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| 93 |
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| 94 | void SERCOM::flushUART()
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| 95 | {
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| 96 | // Wait for transmission to complete
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| 97 | while(sercom->USART.INTFLAG.bit.DRE != SERCOM_USART_INTFLAG_DRE);
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| 98 | }
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| 99 |
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| 100 | void SERCOM::clearStatusUART()
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| 101 | {
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| 102 | //Reset (with 0) the STATUS register
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| 103 | sercom->USART.STATUS.reg = SERCOM_USART_STATUS_RESETVALUE;
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| 104 | }
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| 105 |
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| 106 | bool SERCOM::availableDataUART()
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| 107 | {
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| 108 | //RXC : Receive Complete
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| 109 | return sercom->USART.INTFLAG.bit.RXC;
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| 110 | }
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| 111 |
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| 112 | bool SERCOM::isBufferOverflowErrorUART()
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| 113 | {
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| 114 | //BUFOVF : Buffer Overflow
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| 115 | return sercom->USART.STATUS.bit.BUFOVF;
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| 116 | }
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| 117 |
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| 118 | bool SERCOM::isFrameErrorUART()
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| 119 | {
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| 120 | //FERR : Frame Error
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| 121 | return sercom->USART.STATUS.bit.FERR;
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| 122 | }
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| 123 |
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| 124 | bool SERCOM::isParityErrorUART()
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| 125 | {
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| 126 | //PERR : Parity Error
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| 127 | return sercom->USART.STATUS.bit.PERR;
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| 128 | }
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| 129 |
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| 130 | bool SERCOM::isDataRegisterEmptyUART()
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| 131 | {
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| 132 | //DRE : Data Register Empty
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| 133 | return sercom->USART.INTFLAG.bit.DRE;
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| 134 | }
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| 135 |
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| 136 | uint8_t SERCOM::readDataUART()
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| 137 | {
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| 138 | return sercom->USART.DATA.bit.DATA;
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| 139 | }
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| 140 |
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| 141 | int SERCOM::writeDataUART(uint8_t data)
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| 142 | {
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| 143 | //Flush UART buffer
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| 144 | flushUART();
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| 145 |
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| 146 | //Put data into DATA register
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| 147 | sercom->USART.DATA.reg = (uint16_t)data;
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| 148 | return 1;
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| 149 | }
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| 150 |
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| 151 | /* =========================
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| 152 | * ===== Sercom SPI
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| 153 | * =========================
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| 154 | */
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| 155 | void SERCOM::initSPI(SercomSpiTXPad mosi, SercomRXPad miso, SercomSpiCharSize charSize, SercomDataOrder dataOrder)
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| 156 | {
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| 157 | resetSPI();
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| 158 | initClockNVIC();
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| 159 |
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| 160 | //Setting the CTRLA register
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| 161 | sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE_SPI_MASTER |
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| 162 | SERCOM_SPI_CTRLA_DOPO(mosi) |
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| 163 | SERCOM_SPI_CTRLA_DIPO(miso) |
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| 164 | dataOrder << SERCOM_SPI_CTRLA_DORD_Pos;
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| 165 |
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| 166 | //Setting the CTRLB register
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| 167 | sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(charSize) |
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| 168 | SERCOM_SPI_CTRLB_RXEN; //Active the SPI receiver.
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| 169 |
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| 170 |
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| 171 | }
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| 172 |
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| 173 | void SERCOM::initSPIClock(SercomSpiClockMode clockMode, uint32_t baudrate)
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| 174 | {
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| 175 | //Extract data from clockMode
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| 176 | int cpha, cpol;
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| 177 |
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| 178 | if((clockMode & (0x1ul)) == 0 )
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| 179 | cpha = 0;
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| 180 | else
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| 181 | cpha = 1;
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| 182 |
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| 183 | if((clockMode & (0x2ul)) == 0)
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| 184 | cpol = 0;
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| 185 | else
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| 186 | cpol = 1;
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| 187 |
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| 188 | //Setting the CTRLA register
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| 189 | sercom->SPI.CTRLA.reg |= ( cpha << SERCOM_SPI_CTRLA_CPHA_Pos ) |
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| 190 | ( cpol << SERCOM_SPI_CTRLA_CPOL_Pos );
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| 191 |
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| 192 | //Synchronous arithmetic
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| 193 | sercom->SPI.BAUD.reg = calculateBaudrateSynchronous(baudrate);
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| 194 | }
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| 195 |
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| 196 | void SERCOM::resetSPI()
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| 197 | {
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| 198 | //Setting the Software Reset bit to 1
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| 199 | sercom->SPI.CTRLA.bit.SWRST = 1;
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| 200 |
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| 201 | //Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
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| 202 | while(sercom->SPI.CTRLA.bit.SWRST || sercom->SPI.SYNCBUSY.bit.SWRST);
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| 203 | }
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| 204 |
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| 205 | void SERCOM::enableSPI()
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| 206 | {
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| 207 | //Setting the enable bit to 1
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| 208 | sercom->SPI.CTRLA.bit.ENABLE = 1;
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| 209 |
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| 210 | while(sercom->SPI.SYNCBUSY.bit.ENABLE)
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| 211 | {
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| 212 | //Waiting then enable bit from SYNCBUSY is equal to 0;
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| 213 | }
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| 214 | }
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| 215 |
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| 216 | void SERCOM::disableSPI()
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| 217 | {
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| 218 | //Setting the enable bit to 0
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| 219 | sercom->SPI.CTRLA.bit.ENABLE = 0;
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| 220 |
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| 221 | while(sercom->SPI.SYNCBUSY.bit.ENABLE)
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| 222 | {
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| 223 | //Waiting then enable bit from SYNCBUSY is equal to 0;
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| 224 | }
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| 225 | }
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| 226 |
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| 227 | void SERCOM::setDataOrderSPI(SercomDataOrder dataOrder)
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| 228 | {
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| 229 | //Register enable-protected
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| 230 | disableSPI();
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| 231 |
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| 232 | sercom->SPI.CTRLA.bit.DORD = dataOrder;
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| 233 |
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| 234 | enableSPI();
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| 235 | }
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| 236 |
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| 237 | void SERCOM::setBaudrateSPI(uint8_t divider)
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| 238 | {
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| 239 | //Can't divide by 0
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| 240 | if(divider == 0)
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| 241 | return;
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| 242 |
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| 243 | //Register enable-protected
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| 244 | disableSPI();
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| 245 |
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| 246 | sercom->SPI.BAUD.reg = calculateBaudrateSynchronous( SERCOM_FREQ_REF / divider );
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| 247 |
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| 248 | enableSPI();
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| 249 | }
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| 250 |
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| 251 | void SERCOM::setClockModeSPI(SercomSpiClockMode clockMode)
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| 252 | {
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| 253 | int cpha, cpol;
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| 254 | if((clockMode & (0x1ul)) == 0)
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| 255 | cpha = 0;
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| 256 | else
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| 257 | cpha = 1;
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| 258 |
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| 259 | if((clockMode & (0x2ul)) == 0)
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| 260 | cpol = 0;
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| 261 | else
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| 262 | cpol = 1;
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| 263 |
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| 264 | //Register enable-protected
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| 265 | disableSPI();
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| 266 |
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| 267 | sercom->SPI.CTRLA.bit.CPOL = cpol;
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| 268 | sercom->SPI.CTRLA.bit.CPHA = cpha;
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| 269 |
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| 270 | enableSPI();
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| 271 | }
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| 272 | void SERCOM::writeDataSPI(uint8_t data)
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| 273 | {
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| 274 | while( sercom->SPI.INTFLAG.bit.DRE == 0 )
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| 275 | {
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| 276 | // Waiting Data Registry Empty
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| 277 | }
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| 278 |
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| 279 | sercom->SPI.DATA.bit.DATA = data; // Writing data into Data register
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| 280 |
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| 281 | while( sercom->SPI.INTFLAG.bit.TXC == 0 || sercom->SPI.INTFLAG.bit.DRE == 0 )
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| 282 | {
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| 283 | // Waiting Complete Transmission
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| 284 | }
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| 285 | }
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| 286 |
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| 287 | uint16_t SERCOM::readDataSPI()
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| 288 | {
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| 289 | while( sercom->SPI.INTFLAG.bit.DRE == 0 || sercom->SPI.INTFLAG.bit.RXC == 0 )
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| 290 | {
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| 291 | // Waiting Complete Reception
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| 292 | }
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| 293 |
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| 294 | return sercom->SPI.DATA.bit.DATA; // Reading data
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| 295 | }
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| 296 |
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| 297 | bool SERCOM::isBufferOverflowErrorSPI()
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| 298 | {
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| 299 | return sercom->SPI.STATUS.bit.BUFOVF;
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| 300 | }
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| 301 |
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| 302 | bool SERCOM::isDataRegisterEmptySPI()
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| 303 | {
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| 304 | //DRE : Data Register Empty
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| 305 | return sercom->SPI.INTFLAG.bit.DRE;
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| 306 | }
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| 307 |
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| 308 | uint8_t SERCOM::calculateBaudrateSynchronous(uint32_t baudrate)
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| 309 | {
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| 310 | return SERCOM_FREQ_REF / (2 * baudrate) - 1;
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| 311 | }
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| 312 |
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| 313 |
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| 314 | /* =========================
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| 315 | * ===== Sercom WIRE
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| 316 | * =========================
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| 317 | */
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| 318 |
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| 319 | void SERCOM::resetWIRE()
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| 320 | {
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| 321 | //I2CM OR I2CS, no matter SWRST is the same bit.
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| 322 |
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| 323 | //Setting the Software bit to 1
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| 324 | sercom->I2CM.CTRLA.bit.SWRST = 1;
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| 325 |
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| 326 | //Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
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| 327 | while(sercom->I2CM.CTRLA.bit.SWRST || sercom->I2CM.SYNCBUSY.bit.SWRST);
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| 328 | }
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| 329 |
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| 330 | void SERCOM::enableWIRE()
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| 331 | {
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| 332 | // I2C Master and Slave modes share the ENABLE bit function.
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| 333 |
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| 334 | // Enable the I²C master mode
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| 335 | sercom->I2CM.CTRLA.bit.ENABLE = 1 ;
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| 336 |
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| 337 | while ( sercom->I2CM.SYNCBUSY.bit.ENABLE != 0 )
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| 338 | {
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| 339 | // Waiting the enable bit from SYNCBUSY is equal to 0;
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| 340 | }
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| 341 |
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| 342 | // Setting bus idle mode
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| 343 | sercom->I2CM.STATUS.bit.BUSSTATE = 1 ;
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| 344 |
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| 345 | while ( sercom->I2CM.SYNCBUSY.bit.SYSOP != 0 )
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| 346 | {
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| 347 | // Wait the SYSOP bit from SYNCBUSY coming back to 0
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| 348 | }
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| 349 | }
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| 350 |
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| 351 | void SERCOM::disableWIRE()
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| 352 | {
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| 353 | // I2C Master and Slave modes share the ENABLE bit function.
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| 354 |
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| 355 | // Enable the I²C master mode
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| 356 | sercom->I2CM.CTRLA.bit.ENABLE = 0 ;
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| 357 |
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| 358 | while ( sercom->I2CM.SYNCBUSY.bit.ENABLE != 0 )
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| 359 | {
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| 360 | // Waiting the enable bit from SYNCBUSY is equal to 0;
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| 361 | }
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| 362 | }
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| 363 |
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| 364 | void SERCOM::initSlaveWIRE( uint8_t ucAddress )
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| 365 | {
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| 366 | // Initialize the peripheral clock and interruption
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| 367 | initClockNVIC() ;
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| 368 | resetWIRE() ;
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| 369 |
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| 370 | // Set slave mode
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| 371 | sercom->I2CS.CTRLA.bit.MODE = I2C_SLAVE_OPERATION ;
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| 372 |
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| 373 | // Enable Quick Command
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| 374 | sercom->I2CM.CTRLB.bit.QCEN = 1 ;
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| 375 |
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| 376 | sercom->I2CS.ADDR.reg = SERCOM_I2CS_ADDR_ADDR( ucAddress & 0x7Ful ) | // 0x7F, select only 7 bits
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| 377 | SERCOM_I2CS_ADDR_ADDRMASK( 0x3FFul ) ; // 0x3FF all bits set
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| 378 |
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| 379 | // Set the interrupt register
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| 380 | sercom->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH | // Address Match
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| 381 | SERCOM_I2CS_INTENSET_DRDY ; // Data Ready
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| 382 |
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| 383 | while ( sercom->I2CM.SYNCBUSY.bit.SYSOP != 0 )
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| 384 | {
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| 385 | // Wait the SYSOP bit from SYNCBUSY to come back to 0
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| 386 | }
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| 387 | }
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| 388 |
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| 389 | void SERCOM::initMasterWIRE( uint32_t baudrate )
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| 390 | {
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| 391 | // Initialize the peripheral clock and interruption
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| 392 | initClockNVIC() ;
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| 393 |
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| 394 | resetWIRE() ;
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| 395 |
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| 396 | // Set master mode and enable SCL Clock Stretch mode (stretch after ACK bit)
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| 397 | sercom->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_MODE( I2C_MASTER_OPERATION );
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| 398 |
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| 399 | // Enable Smart mode and Quick Command
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| 400 |
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| 401 | // Enable all interrupts
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| 402 |
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| 403 | // Synchronous arithmetic baudrate
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| 404 | sercom->I2CM.BAUD.bit.BAUD = SystemCoreClock / ( 2 * baudrate) - 1 ;
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| 405 | }
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| 406 |
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| 407 | void SERCOM::prepareNackBitWIRE( void )
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| 408 | {
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| 409 | // Send a NACK
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| 410 | sercom->I2CM.CTRLB.bit.ACKACT = 1;
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| 411 | }
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| 412 |
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| 413 | void SERCOM::prepareAckBitWIRE( void )
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| 414 | {
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| 415 | // Send an ACK
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| 416 | sercom->I2CM.CTRLB.bit.ACKACT = 0;
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| 417 | }
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| 418 |
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| 419 | void SERCOM::prepareCommandBitsWire(SercomMasterCommandWire cmd)
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| 420 | {
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| 421 | sercom->I2CM.CTRLB.bit.CMD = cmd;
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| 422 |
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| 423 | while(sercom->I2CM.SYNCBUSY.bit.SYSOP)
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| 424 | {
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| 425 | // Waiting for synchronization
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| 426 | }
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| 427 | }
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| 428 |
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| 429 | bool SERCOM::startTransmissionWIRE(uint8_t address, SercomWireReadWriteFlag flag)
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| 430 | {
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| 431 | // 7-bits address + 1-bits R/W
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| 432 | address = (address << 0x1ul) | flag;
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| 433 |
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| 434 | // Wait idle bus mode
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| 435 | while ( !isBusIdleWIRE() );
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| 436 |
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| 437 | // Send start and address
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| 438 | sercom->I2CM.ADDR.bit.ADDR = address;
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| 439 |
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| 440 | // Address Transmitted
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| 441 | if ( flag == WIRE_WRITE_FLAG ) // Write mode
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| 442 | {
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| 443 | while( !sercom->I2CM.INTFLAG.bit.MB )
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| 444 | {
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| 445 | // Wait transmission complete
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| 446 | }
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| 447 | }
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| 448 | else // Read mode
|
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| 449 | {
|
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| 450 | while( !sercom->I2CM.INTFLAG.bit.SB )
|
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| 451 | {
|
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| 452 | // Wait transmission complete
|
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| 453 | }
|
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| 454 |
|
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| 455 | // Clean the 'Slave on Bus' flag, for further usage.
|
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| 456 | //sercom->I2CM.INTFLAG.bit.SB = 0x1ul;
|
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| 457 | }
|
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| 458 |
|
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| 459 |
|
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| 460 | //ACK received (0: ACK, 1: NACK)
|
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| 461 | if(sercom->I2CM.STATUS.bit.RXNACK)
|
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| 462 | {
|
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| 463 | return false;
|
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| 464 | }
|
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| 465 | else
|
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| 466 | {
|
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| 467 | return true;
|
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| 468 | }
|
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| 469 | }
|
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| 470 |
|
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| 471 | bool SERCOM::sendDataMasterWIRE(uint8_t data)
|
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| 472 | {
|
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| 473 | //Send data
|
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| 474 | sercom->I2CM.DATA.bit.DATA = data;
|
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| 475 |
|
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| 476 | //Wait transmission successful
|
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| 477 | while(!sercom->I2CM.INTFLAG.bit.MB);
|
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| 478 |
|
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| 479 | //Problems on line? nack received?
|
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| 480 | if(sercom->I2CM.STATUS.bit.RXNACK)
|
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| 481 | return false;
|
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| 482 | else
|
---|
| 483 | return true;
|
---|
| 484 | }
|
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| 485 |
|
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| 486 | bool SERCOM::sendDataSlaveWIRE(uint8_t data)
|
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| 487 | {
|
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| 488 | //Send data
|
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| 489 | sercom->I2CS.DATA.bit.DATA = data;
|
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| 490 |
|
---|
| 491 | //Wait data transmission successful
|
---|
| 492 | while(!sercom->I2CS.INTFLAG.bit.DRDY);
|
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| 493 |
|
---|
| 494 | //Problems on line? nack received?
|
---|
| 495 | if(sercom->I2CS.STATUS.bit.RXNACK)
|
---|
| 496 | return false;
|
---|
| 497 | else
|
---|
| 498 | return true;
|
---|
| 499 | }
|
---|
| 500 |
|
---|
| 501 | bool SERCOM::isMasterWIRE( void )
|
---|
| 502 | {
|
---|
| 503 | return sercom->I2CS.CTRLA.bit.MODE == I2C_MASTER_OPERATION;
|
---|
| 504 | }
|
---|
| 505 |
|
---|
| 506 | bool SERCOM::isSlaveWIRE( void )
|
---|
| 507 | {
|
---|
| 508 | return sercom->I2CS.CTRLA.bit.MODE == I2C_SLAVE_OPERATION;
|
---|
| 509 | }
|
---|
| 510 |
|
---|
| 511 | bool SERCOM::isBusIdleWIRE( void )
|
---|
| 512 | {
|
---|
| 513 | return sercom->I2CM.STATUS.bit.BUSSTATE == WIRE_IDLE_STATE;
|
---|
| 514 | }
|
---|
| 515 |
|
---|
| 516 | bool SERCOM::isDataReadyWIRE( void )
|
---|
| 517 | {
|
---|
| 518 | return sercom->I2CS.INTFLAG.bit.DRDY;
|
---|
| 519 | }
|
---|
| 520 |
|
---|
| 521 | bool SERCOM::isStopDetectedWIRE( void )
|
---|
| 522 | {
|
---|
| 523 | return sercom->I2CS.INTFLAG.bit.PREC;
|
---|
| 524 | }
|
---|
| 525 |
|
---|
| 526 | bool SERCOM::isRestartDetectedWIRE( void )
|
---|
| 527 | {
|
---|
| 528 | return sercom->I2CS.STATUS.bit.SR;
|
---|
| 529 | }
|
---|
| 530 |
|
---|
| 531 | bool SERCOM::isAddressMatch( void )
|
---|
| 532 | {
|
---|
| 533 | return sercom->I2CS.INTFLAG.bit.AMATCH;
|
---|
| 534 | }
|
---|
| 535 |
|
---|
| 536 | bool SERCOM::isMasterReadOperationWIRE( void )
|
---|
| 537 | {
|
---|
| 538 | return sercom->I2CS.STATUS.bit.DIR;
|
---|
| 539 | }
|
---|
| 540 |
|
---|
| 541 | bool SERCOM::isRXNackReceivedWIRE( void )
|
---|
| 542 | {
|
---|
| 543 | return sercom->I2CM.STATUS.bit.RXNACK;
|
---|
| 544 | }
|
---|
| 545 |
|
---|
| 546 | int SERCOM::availableWIRE( void )
|
---|
| 547 | {
|
---|
| 548 | if(isMasterWIRE())
|
---|
| 549 | return sercom->I2CM.INTFLAG.bit.SB;
|
---|
| 550 | else
|
---|
| 551 | return sercom->I2CS.INTFLAG.bit.DRDY;
|
---|
| 552 | }
|
---|
| 553 |
|
---|
| 554 | uint8_t SERCOM::readDataWIRE( void )
|
---|
| 555 | {
|
---|
| 556 | if(isMasterWIRE())
|
---|
| 557 | {
|
---|
| 558 | while( sercom->I2CM.INTFLAG.bit.SB == 0 )
|
---|
| 559 | {
|
---|
| 560 | // Waiting complete receive
|
---|
| 561 | }
|
---|
| 562 |
|
---|
| 563 | return sercom->I2CM.DATA.bit.DATA ;
|
---|
| 564 | }
|
---|
| 565 | else
|
---|
| 566 | {
|
---|
| 567 | return sercom->I2CS.DATA.reg ;
|
---|
| 568 | }
|
---|
| 569 | }
|
---|
| 570 |
|
---|
| 571 |
|
---|
| 572 | void SERCOM::initClockNVIC( void )
|
---|
| 573 | {
|
---|
| 574 | uint8_t clockId = 0;
|
---|
| 575 | IRQn_Type IdNvic;
|
---|
| 576 |
|
---|
| 577 | if(sercom == SERCOM0)
|
---|
| 578 | {
|
---|
| 579 | clockId = GCM_SERCOM0_CORE;
|
---|
| 580 | IdNvic = SERCOM0_IRQn;
|
---|
| 581 | }
|
---|
| 582 | else if(sercom == SERCOM1)
|
---|
| 583 | {
|
---|
| 584 | clockId = GCM_SERCOM1_CORE;
|
---|
| 585 | IdNvic = SERCOM1_IRQn;
|
---|
| 586 | }
|
---|
| 587 | else if(sercom == SERCOM2)
|
---|
| 588 | {
|
---|
| 589 | clockId = GCM_SERCOM2_CORE;
|
---|
| 590 | IdNvic = SERCOM2_IRQn;
|
---|
| 591 | }
|
---|
| 592 | else if(sercom == SERCOM3)
|
---|
| 593 | {
|
---|
| 594 | clockId = GCM_SERCOM3_CORE;
|
---|
| 595 | IdNvic = SERCOM3_IRQn;
|
---|
| 596 | }
|
---|
| 597 | else if(sercom == SERCOM4)
|
---|
| 598 | {
|
---|
| 599 | clockId = GCM_SERCOM4_CORE;
|
---|
| 600 | IdNvic = SERCOM4_IRQn;
|
---|
| 601 | }
|
---|
| 602 | else if(sercom == SERCOM5)
|
---|
| 603 | {
|
---|
| 604 | clockId = GCM_SERCOM5_CORE;
|
---|
| 605 | IdNvic = SERCOM5_IRQn;
|
---|
| 606 | }
|
---|
| 607 |
|
---|
| 608 | // Setting NVIC
|
---|
| 609 | NVIC_EnableIRQ(IdNvic);
|
---|
| 610 | NVIC_SetPriority (IdNvic, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority */
|
---|
| 611 |
|
---|
| 612 | //Setting clock
|
---|
| 613 | GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( clockId ) | // Generic Clock 0 (SERCOMx)
|
---|
| 614 | GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
|
---|
| 615 | GCLK_CLKCTRL_CLKEN ;
|
---|
| 616 |
|
---|
| 617 | while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
|
---|
| 618 | {
|
---|
| 619 | /* Wait for synchronization */
|
---|
| 620 | }
|
---|
| 621 |
|
---|
| 622 | }
|
---|