# TCL File Generated by Component Editor 8.1 # Fri Aug 28 12:47:32 JST 2009 # DO NOT MODIFY # +----------------------------------- # | # | sysver "sysver" v1.0 # | null 2009.08.28.12:47:32 # | # | # | C:/home/nces/os/hw/queuing_lock/1s40_dual_fmp/sysver/sysver.vhd # | # | ./sysver.vhd syn, sim # | # +----------------------------------- # +----------------------------------- # | module sysver # | set_module_property NAME sysver set_module_property VERSION 1.0 set_module_property GROUP Other set_module_property DISPLAY_NAME sysver set_module_property LIBRARIES {ieee.std_logic_1164.all std.standard.all} set_module_property TOP_LEVEL_HDL_FILE sysver.vhd set_module_property TOP_LEVEL_HDL_MODULE sysver set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE false # | # +----------------------------------- # +----------------------------------- # | files # | add_file sysver.vhd {SYNTHESIS SIMULATION} # | # +----------------------------------- # +----------------------------------- # | parameters # | add_parameter VER1_ROM_REG_VALUE STD_LOGIC_VECTOR 0 "" set_parameter_property VER1_ROM_REG_VALUE DISPLAY_NAME VER1_ROM_REG_VALUE set_parameter_property VER1_ROM_REG_VALUE UNITS None set_parameter_property VER1_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295 set_parameter_property VER1_ROM_REG_VALUE DESCRIPTION "" set_parameter_property VER1_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true add_parameter VER2_ROM_REG_VALUE STD_LOGIC_VECTOR 0 "" set_parameter_property VER2_ROM_REG_VALUE DISPLAY_NAME VER2_ROM_REG_VALUE set_parameter_property VER2_ROM_REG_VALUE UNITS None set_parameter_property VER2_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295 set_parameter_property VER2_ROM_REG_VALUE DESCRIPTION "" set_parameter_property VER2_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true add_parameter VER3_ROM_REG_VALUE STD_LOGIC_VECTOR 0 "" set_parameter_property VER3_ROM_REG_VALUE DISPLAY_NAME VER3_ROM_REG_VALUE set_parameter_property VER3_ROM_REG_VALUE UNITS None set_parameter_property VER3_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295 set_parameter_property VER3_ROM_REG_VALUE DESCRIPTION "" set_parameter_property VER3_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true add_parameter VER4_ROM_REG_VALUE STD_LOGIC_VECTOR 0 "" set_parameter_property VER4_ROM_REG_VALUE DISPLAY_NAME VER4_ROM_REG_VALUE set_parameter_property VER4_ROM_REG_VALUE UNITS None set_parameter_property VER4_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295 set_parameter_property VER4_ROM_REG_VALUE DESCRIPTION "" set_parameter_property VER4_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true add_parameter VER5_RAM_REG_VALUE STD_LOGIC_VECTOR 0 "" set_parameter_property VER5_RAM_REG_VALUE DISPLAY_NAME VER5_RAM_REG_VALUE set_parameter_property VER5_RAM_REG_VALUE UNITS None set_parameter_property VER5_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295 set_parameter_property VER5_RAM_REG_VALUE DESCRIPTION "" set_parameter_property VER5_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true add_parameter VER6_RAM_REG_VALUE STD_LOGIC_VECTOR 0 "" set_parameter_property VER6_RAM_REG_VALUE DISPLAY_NAME VER6_RAM_REG_VALUE set_parameter_property VER6_RAM_REG_VALUE UNITS None set_parameter_property VER6_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295 set_parameter_property VER6_RAM_REG_VALUE DESCRIPTION "" set_parameter_property VER6_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true add_parameter VER7_RAM_REG_VALUE STD_LOGIC_VECTOR 0 "" set_parameter_property VER7_RAM_REG_VALUE DISPLAY_NAME VER7_RAM_REG_VALUE set_parameter_property VER7_RAM_REG_VALUE UNITS None set_parameter_property VER7_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295 set_parameter_property VER7_RAM_REG_VALUE DESCRIPTION "" set_parameter_property VER7_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true add_parameter VER8_RAM_REG_VALUE STD_LOGIC_VECTOR 0 "" set_parameter_property VER8_RAM_REG_VALUE DISPLAY_NAME VER8_RAM_REG_VALUE set_parameter_property VER8_RAM_REG_VALUE UNITS None set_parameter_property VER8_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295 set_parameter_property VER8_RAM_REG_VALUE DESCRIPTION "" set_parameter_property VER8_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true # | # +----------------------------------- # +----------------------------------- # | connection point clock_reset # | add_interface clock_reset clock end set_interface_property clock_reset ptfSchematicName "" add_interface_port clock_reset clk clk Input 1 add_interface_port clock_reset reset_n reset_n Input 1 # | # +----------------------------------- # +----------------------------------- # | connection point avalon_slave_0 # | add_interface avalon_slave_0 avalon end set_interface_property avalon_slave_0 addressAlignment DYNAMIC set_interface_property avalon_slave_0 addressSpan 32 set_interface_property avalon_slave_0 bridgesToMaster "" set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false set_interface_property avalon_slave_0 holdTime 0 set_interface_property avalon_slave_0 isMemoryDevice false set_interface_property avalon_slave_0 isNonVolatileStorage false set_interface_property avalon_slave_0 linewrapBursts false set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1 set_interface_property avalon_slave_0 printableDevice false set_interface_property avalon_slave_0 readLatency 0 set_interface_property avalon_slave_0 readWaitTime 1 set_interface_property avalon_slave_0 setupTime 0 set_interface_property avalon_slave_0 timingUnits Cycles set_interface_property avalon_slave_0 writeWaitTime 0 set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset add_interface_port avalon_slave_0 chipselect chipselect Input 1 add_interface_port avalon_slave_0 address address Input 3 add_interface_port avalon_slave_0 write write Input 1 add_interface_port avalon_slave_0 writedata writedata Input 32 add_interface_port avalon_slave_0 read read Input 1 add_interface_port avalon_slave_0 readdata readdata Output 32 add_interface_port avalon_slave_0 byteenable byteenable Input 4 add_interface_port avalon_slave_0 waitrequest waitrequest Output 1 # | # +-----------------------------------