1 | //////////////////////////////////////////////////////////////////////
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2 | //// ////
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3 | //// can_fifo.v ////
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4 | //// ////
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5 | //// ////
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6 | //// This file is part of the CAN Protocol Controller ////
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7 | //// http://www.opencores.org/projects/can/ ////
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8 | //// ////
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9 | //// ////
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10 | //// Author(s): ////
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11 | //// Igor Mohor ////
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12 | //// igorm@opencores.org ////
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13 | //// ////
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14 | //// ////
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15 | //// All additional information is available in the README.txt ////
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16 | //// file. ////
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17 | //// ////
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18 | //////////////////////////////////////////////////////////////////////
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19 | //// ////
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20 | //// Copyright (C) 2002, 2003, 2004 Authors ////
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21 | //// ////
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22 | //// This source file may be used and distributed without ////
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23 | //// restriction provided that this copyright statement is not ////
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24 | //// removed from the file and that any derivative work contains ////
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25 | //// the original copyright notice and the associated disclaimer. ////
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26 | //// ////
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27 | //// This source file is free software; you can redistribute it ////
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28 | //// and/or modify it under the terms of the GNU Lesser General ////
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29 | //// Public License as published by the Free Software Foundation; ////
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30 | //// either version 2.1 of the License, or (at your option) any ////
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31 | //// later version. ////
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32 | //// ////
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33 | //// This source is distributed in the hope that it will be ////
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34 | //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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35 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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36 | //// PURPOSE. See the GNU Lesser General Public License for more ////
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37 | //// details. ////
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38 | //// ////
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39 | //// You should have received a copy of the GNU Lesser General ////
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40 | //// Public License along with this source; if not, download it ////
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41 | //// from http://www.opencores.org/lgpl.shtml ////
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42 | //// ////
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43 | //// The CAN protocol is developed by Robert Bosch GmbH and ////
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44 | //// protected by patents. Anybody who wants to implement this ////
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45 | //// CAN IP core on silicon has to obtain a CAN protocol license ////
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46 | //// from Bosch. ////
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47 | //// ////
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48 | //////////////////////////////////////////////////////////////////////
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49 | //
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50 | // CVS Revision History
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51 | //
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52 | // $Log: can_fifo.v,v $
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53 | // Revision 1.27 2004/11/18 12:39:34 igorm
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54 | // Fixes for compatibility after the SW reset.
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55 | //
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56 | // Revision 1.26 2004/02/08 14:30:57 mohor
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57 | // Header changed.
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58 | //
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59 | // Revision 1.25 2003/10/23 16:52:17 mohor
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60 | // Active high/low problem when Altera devices are used. Bug fixed by
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61 | // Rojhalat Ibrahim.
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62 | //
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63 | // Revision 1.24 2003/10/17 05:55:20 markom
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64 | // mbist signals updated according to newest convention
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65 | //
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66 | // Revision 1.23 2003/09/05 12:46:41 mohor
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67 | // ALTERA_RAM supported.
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68 | //
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69 | // Revision 1.22 2003/08/20 09:59:16 mohor
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70 | // Artisan RAM fixed (when not using BIST).
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71 | //
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72 | // Revision 1.21 2003/08/14 16:04:52 simons
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73 | // Artisan ram instances added.
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74 | //
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75 | // Revision 1.20 2003/07/16 14:00:45 mohor
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76 | // Fixed according to the linter.
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77 | //
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78 | // Revision 1.19 2003/07/03 09:30:44 mohor
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79 | // PCI_BIST replaced with CAN_BIST.
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80 | //
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81 | // Revision 1.18 2003/06/27 22:14:23 simons
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82 | // Overrun fifo implemented with FFs, because it is not possible to create such a memory.
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83 | //
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84 | // Revision 1.17 2003/06/27 20:56:15 simons
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85 | // Virtual silicon ram instances added.
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86 | //
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87 | // Revision 1.16 2003/06/18 23:03:44 mohor
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88 | // Typo fixed.
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89 | //
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90 | // Revision 1.15 2003/06/11 09:37:05 mohor
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91 | // overrun and length_info fifos are initialized at the end of reset.
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92 | //
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93 | // Revision 1.14 2003/03/05 15:02:30 mohor
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94 | // Xilinx RAM added.
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95 | //
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96 | // Revision 1.13 2003/03/01 22:53:33 mohor
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97 | // Actel APA ram supported.
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98 | //
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99 | // Revision 1.12 2003/02/19 14:44:03 mohor
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100 | // CAN core finished. Host interface added. Registers finished.
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101 | // Synchronization to the wishbone finished.
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102 | //
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103 | // Revision 1.11 2003/02/14 20:17:01 mohor
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104 | // Several registers added. Not finished, yet.
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105 | //
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106 | // Revision 1.10 2003/02/11 00:56:06 mohor
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107 | // Wishbone interface added.
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108 | //
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109 | // Revision 1.9 2003/02/09 02:24:33 mohor
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110 | // Bosch license warning added. Error counters finished. Overload frames
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111 | // still need to be fixed.
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112 | //
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113 | // Revision 1.8 2003/01/31 01:13:38 mohor
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114 | // backup.
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115 | //
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116 | // Revision 1.7 2003/01/17 17:44:31 mohor
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117 | // Fifo corrected to be synthesizable.
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118 | //
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119 | // Revision 1.6 2003/01/15 13:16:47 mohor
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120 | // When a frame with "remote request" is received, no data is stored
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121 | // to fifo, just the frame information (identifier, ...). Data length
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122 | // that is stored is the received data length and not the actual data
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123 | // length that is stored to fifo.
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124 | //
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125 | // Revision 1.5 2003/01/14 17:25:09 mohor
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126 | // Addresses corrected to decimal values (previously hex).
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127 | //
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128 | // Revision 1.4 2003/01/14 12:19:35 mohor
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129 | // rx_fifo is now working.
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130 | //
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131 | // Revision 1.3 2003/01/09 21:54:45 mohor
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132 | // rx fifo added. Not 100 % verified, yet.
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133 | //
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134 | // Revision 1.2 2003/01/09 14:46:58 mohor
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135 | // Temporary files (backup).
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136 | //
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137 | // Revision 1.1 2003/01/08 02:10:55 mohor
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138 | // Acceptance filter added.
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139 | //
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140 | //
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141 | //
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142 | //
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143 |
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144 | // synopsys translate_off
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145 | `include "timescale.v"
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146 | // synopsys translate_on
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147 | `include "can_defines.v"
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148 |
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149 | module can_fifo
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150 | (
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151 | clk,
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152 | rst,
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153 |
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154 | wr,
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155 |
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156 | data_in,
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157 | addr,
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158 | data_out,
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159 | fifo_selected,
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160 |
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161 | reset_mode,
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162 | release_buffer,
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163 | extended_mode,
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164 | overrun,
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165 | info_empty,
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166 | info_cnt
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167 |
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168 | `ifdef CAN_BIST
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169 | ,
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170 | mbist_si_i,
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171 | mbist_so_o,
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172 | mbist_ctrl_i
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173 | `endif
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174 | );
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175 |
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176 | parameter Tp = 1;
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177 |
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178 | input clk;
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179 | input rst;
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180 | input wr;
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181 | input [7:0] data_in;
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182 | input [5:0] addr;
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183 | input reset_mode;
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184 | input release_buffer;
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185 | input extended_mode;
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186 | input fifo_selected;
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187 |
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188 | output [7:0] data_out;
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189 | output overrun;
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190 | output info_empty;
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191 | output [6:0] info_cnt;
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192 |
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193 | `ifdef CAN_BIST
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194 | input mbist_si_i;
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195 | output mbist_so_o;
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196 | input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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197 | wire mbist_s_0;
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198 | `endif
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199 |
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200 | `ifdef ALTERA_RAM
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201 | `else
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202 | `ifdef ACTEL_APA_RAM
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203 | `else
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204 | `ifdef XILINX_RAM
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205 | `else
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206 | `ifdef ARTISAN_RAM
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207 | reg overrun_info[0:63];
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208 | `else
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209 | `ifdef VIRTUALSILICON_RAM
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210 | reg overrun_info[0:63];
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211 | `else
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212 | reg [7:0] fifo [0:63];
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213 | reg [3:0] length_fifo[0:63];
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214 | reg overrun_info[0:63];
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215 | `endif
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216 | `endif
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217 | `endif
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218 | `endif
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219 | `endif
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220 |
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221 | reg [5:0] rd_pointer;
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222 | reg [5:0] wr_pointer;
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223 | reg [5:0] read_address;
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224 | reg [5:0] wr_info_pointer;
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225 | reg [5:0] rd_info_pointer;
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226 | reg wr_q;
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227 | reg [3:0] len_cnt;
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228 | reg [6:0] fifo_cnt;
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229 | reg [6:0] info_cnt;
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230 | reg latch_overrun;
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231 | reg initialize_memories;
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232 |
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233 | wire [3:0] length_info;
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234 | wire write_length_info;
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235 | wire fifo_empty;
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236 | wire fifo_full;
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237 | wire info_full;
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238 |
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239 | assign write_length_info = (~wr) & wr_q;
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240 |
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241 | // Delayed write signal
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242 | always @ (posedge clk or posedge rst)
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243 | begin
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244 | if (rst)
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245 | wr_q <=#Tp 1'b0;
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246 | else if (reset_mode)
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247 | wr_q <=#Tp 1'b0;
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248 | else
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249 | wr_q <=#Tp wr;
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250 | end
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251 |
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252 |
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253 | // length counter
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254 | always @ (posedge clk or posedge rst)
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255 | begin
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256 | if (rst)
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257 | len_cnt <= 4'h0;
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258 | else if (reset_mode | write_length_info)
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259 | len_cnt <=#Tp 4'h0;
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260 | else if (wr & (~fifo_full))
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261 | len_cnt <=#Tp len_cnt + 1'b1;
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262 | end
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263 |
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264 |
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265 | // wr_info_pointer
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266 | always @ (posedge clk or posedge rst)
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267 | begin
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268 | if (rst)
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269 | wr_info_pointer <= 6'h0;
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270 | else if (write_length_info & (~info_full) | initialize_memories)
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271 | wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
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272 | else if (reset_mode)
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273 | wr_info_pointer <=#Tp rd_info_pointer;
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274 | end
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275 |
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276 |
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277 |
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278 | // rd_info_pointer
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279 | always @ (posedge clk or posedge rst)
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280 | begin
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281 | if (rst)
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282 | rd_info_pointer <= 6'h0;
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283 | else if (release_buffer & (~fifo_empty))
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284 | rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
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285 | end
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286 |
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287 |
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288 | // rd_pointer
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289 | always @ (posedge clk or posedge rst)
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290 | begin
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291 | if (rst)
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292 | rd_pointer <= 5'h0;
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293 | else if (release_buffer & (~fifo_empty))
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294 | rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
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295 | end
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296 |
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297 |
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298 | // wr_pointer
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299 | always @ (posedge clk or posedge rst)
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300 | begin
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301 | if (rst)
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302 | wr_pointer <= 5'h0;
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303 | else if (reset_mode)
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304 | wr_pointer <=#Tp rd_pointer;
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305 | else if (wr & (~fifo_full))
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306 | wr_pointer <=#Tp wr_pointer + 1'b1;
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307 | end
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308 |
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309 |
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310 | // latch_overrun
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311 | always @ (posedge clk or posedge rst)
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312 | begin
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313 | if (rst)
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314 | latch_overrun <= 1'b0;
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315 | else if (reset_mode | write_length_info)
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316 | latch_overrun <=#Tp 1'b0;
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317 | else if (wr & fifo_full)
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318 | latch_overrun <=#Tp 1'b1;
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319 | end
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320 |
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321 |
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322 | // Counting data in fifo
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323 | always @ (posedge clk or posedge rst)
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324 | begin
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325 | if (rst)
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326 | fifo_cnt <= 7'h0;
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327 | else if (reset_mode)
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328 | fifo_cnt <=#Tp 7'h0;
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329 | else if (wr & (~release_buffer) & (~fifo_full))
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330 | fifo_cnt <=#Tp fifo_cnt + 1'b1;
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331 | else if ((~wr) & release_buffer & (~fifo_empty))
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332 | fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
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333 | else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
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334 | fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
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335 | end
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336 |
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337 | assign fifo_full = fifo_cnt == 7'd64;
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338 | assign fifo_empty = fifo_cnt == 7'd0;
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339 |
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340 |
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341 | // Counting data in length_fifo and overrun_info fifo
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342 | always @ (posedge clk or posedge rst)
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343 | begin
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344 | if (rst)
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345 | info_cnt <=#Tp 7'h0;
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346 | else if (reset_mode)
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347 | info_cnt <=#Tp 7'h0;
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348 | else if (write_length_info ^ release_buffer)
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349 | begin
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350 | if (release_buffer & (~info_empty))
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351 | info_cnt <=#Tp info_cnt - 1'b1;
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352 | else if (write_length_info & (~info_full))
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353 | info_cnt <=#Tp info_cnt + 1'b1;
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354 | end
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355 | end
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356 |
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357 | assign info_full = info_cnt == 7'd64;
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358 | assign info_empty = info_cnt == 7'd0;
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359 |
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360 |
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361 | // Selecting which address will be used for reading data from rx fifo
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362 | always @ (extended_mode or rd_pointer or addr)
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363 | begin
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364 | if (extended_mode) // extended mode
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365 | read_address = rd_pointer + (addr - 6'd16);
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366 | else // normal mode
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367 | read_address = rd_pointer + (addr - 6'd20);
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368 | end
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369 |
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370 |
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371 | always @ (posedge clk or posedge rst)
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372 | begin
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373 | if (rst)
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374 | initialize_memories <= 1'b1;
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375 | else if (&wr_info_pointer)
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376 | initialize_memories <=#Tp 1'b0;
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377 | end
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378 |
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379 |
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380 | `ifdef ALTERA_RAM
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381 | // altera_ram_64x8_sync fifo
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382 | lpm_ram_dp fifo
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383 | (
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384 | .q (data_out),
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385 | .rdclock (clk),
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386 | .wrclock (clk),
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387 | .data (data_in),
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388 | .wren (wr & (~fifo_full)),
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389 | .rden (fifo_selected),
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390 | .wraddress (wr_pointer),
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391 | .rdaddress (read_address)
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392 | );
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393 | defparam fifo.lpm_width = 8;
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394 | defparam fifo.lpm_widthad = 6;
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395 | defparam fifo.lpm_numwords = 64;
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396 |
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397 |
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398 | // altera_ram_64x4_sync info_fifo
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399 | lpm_ram_dp info_fifo
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400 | (
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401 | .q (length_info),
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402 | .rdclock (clk),
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403 | .wrclock (clk),
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404 | .data (len_cnt & {4{~initialize_memories}}),
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405 | .wren (write_length_info & (~info_full) | initialize_memories),
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406 | .wraddress (wr_info_pointer),
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407 | .rdaddress (rd_info_pointer)
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408 | );
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409 | defparam info_fifo.lpm_width = 4;
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410 | defparam info_fifo.lpm_widthad = 6;
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411 | defparam info_fifo.lpm_numwords = 64;
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412 |
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413 |
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414 | // altera_ram_64x1_sync overrun_fifo
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415 | lpm_ram_dp overrun_fifo
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416 | (
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417 | .q (overrun),
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418 | .rdclock (clk),
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419 | .wrclock (clk),
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420 | .data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
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421 | .wren (write_length_info & (~info_full) | initialize_memories),
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422 | .wraddress (wr_info_pointer),
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423 | .rdaddress (rd_info_pointer)
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424 | );
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425 | defparam overrun_fifo.lpm_width = 1;
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426 | defparam overrun_fifo.lpm_widthad = 6;
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427 | defparam overrun_fifo.lpm_numwords = 64;
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428 |
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429 | `else
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430 | `ifdef ACTEL_APA_RAM
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431 | actel_ram_64x8_sync fifo
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432 | (
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433 | .DO (data_out),
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434 | .RCLOCK (clk),
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435 | .WCLOCK (clk),
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436 | .DI (data_in),
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437 | .PO (), // parity not used
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438 | .WRB (~(wr & (~fifo_full))),
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439 | .RDB (~fifo_selected),
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440 | .WADDR (wr_pointer),
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441 | .RADDR (read_address)
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442 | );
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443 |
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444 |
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445 | actel_ram_64x4_sync info_fifo
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446 | (
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447 | .DO (length_info),
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448 | .RCLOCK (clk),
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449 | .WCLOCK (clk),
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450 | .DI (len_cnt & {4{~initialize_memories}}),
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451 | .PO (), // parity not used
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452 | .WRB (~(write_length_info & (~info_full) | initialize_memories)),
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453 | .RDB (1'b0), // always enabled
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454 | .WADDR (wr_info_pointer),
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455 | .RADDR (rd_info_pointer)
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456 | );
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457 |
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458 |
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459 | actel_ram_64x1_sync overrun_fifo
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460 | (
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461 | .DO (overrun),
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---|
462 | .RCLOCK (clk),
|
---|
463 | .WCLOCK (clk),
|
---|
464 | .DI ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
|
---|
465 | .PO (), // parity not used
|
---|
466 | .WRB (~(write_length_info & (~info_full) | initialize_memories)),
|
---|
467 | .RDB (1'b0), // always enabled
|
---|
468 | .WADDR (wr_info_pointer),
|
---|
469 | .RADDR (rd_info_pointer)
|
---|
470 | );
|
---|
471 | `else
|
---|
472 | `ifdef XILINX_RAM
|
---|
473 |
|
---|
474 | RAMB4_S8_S8 fifo
|
---|
475 | (
|
---|
476 | .DOA(),
|
---|
477 | .DOB(data_out),
|
---|
478 | .ADDRA({3'h0, wr_pointer}),
|
---|
479 | .CLKA(clk),
|
---|
480 | .DIA(data_in),
|
---|
481 | .ENA(1'b1),
|
---|
482 | .RSTA(1'b0),
|
---|
483 | .WEA(wr & (~fifo_full)),
|
---|
484 | .ADDRB({3'h0, read_address}),
|
---|
485 | .CLKB(clk),
|
---|
486 | .DIB(8'h0),
|
---|
487 | .ENB(1'b1),
|
---|
488 | .RSTB(1'b0),
|
---|
489 | .WEB(1'b0)
|
---|
490 | );
|
---|
491 |
|
---|
492 |
|
---|
493 | RAMB4_S4_S4 info_fifo
|
---|
494 | (
|
---|
495 | .DOA(),
|
---|
496 | .DOB(length_info),
|
---|
497 | .ADDRA({4'h0, wr_info_pointer}),
|
---|
498 | .CLKA(clk),
|
---|
499 | .DIA(len_cnt & {4{~initialize_memories}}),
|
---|
500 | .ENA(1'b1),
|
---|
501 | .RSTA(1'b0),
|
---|
502 | .WEA(write_length_info & (~info_full) | initialize_memories),
|
---|
503 | .ADDRB({4'h0, rd_info_pointer}),
|
---|
504 | .CLKB(clk),
|
---|
505 | .DIB(4'h0),
|
---|
506 | .ENB(1'b1),
|
---|
507 | .RSTB(1'b0),
|
---|
508 | .WEB(1'b0)
|
---|
509 | );
|
---|
510 |
|
---|
511 |
|
---|
512 | RAMB4_S1_S1 overrun_fifo
|
---|
513 | (
|
---|
514 | .DOA(),
|
---|
515 | .DOB(overrun),
|
---|
516 | .ADDRA({6'h0, wr_info_pointer}),
|
---|
517 | .CLKA(clk),
|
---|
518 | .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
|
---|
519 | .ENA(1'b1),
|
---|
520 | .RSTA(1'b0),
|
---|
521 | .WEA(write_length_info & (~info_full) | initialize_memories),
|
---|
522 | .ADDRB({6'h0, rd_info_pointer}),
|
---|
523 | .CLKB(clk),
|
---|
524 | .DIB(1'h0),
|
---|
525 | .ENB(1'b1),
|
---|
526 | .RSTB(1'b0),
|
---|
527 | .WEB(1'b0)
|
---|
528 | );
|
---|
529 |
|
---|
530 |
|
---|
531 | `else
|
---|
532 | `ifdef VIRTUALSILICON_RAM
|
---|
533 |
|
---|
534 | `ifdef CAN_BIST
|
---|
535 | vs_hdtp_64x8_bist fifo
|
---|
536 | `else
|
---|
537 | vs_hdtp_64x8 fifo
|
---|
538 | `endif
|
---|
539 | (
|
---|
540 | .RCK (clk),
|
---|
541 | .WCK (clk),
|
---|
542 | .RADR (read_address),
|
---|
543 | .WADR (wr_pointer),
|
---|
544 | .DI (data_in),
|
---|
545 | .DOUT (data_out),
|
---|
546 | .REN (~fifo_selected),
|
---|
547 | .WEN (~(wr & (~fifo_full)))
|
---|
548 | `ifdef CAN_BIST
|
---|
549 | ,
|
---|
550 | // debug chain signals
|
---|
551 | .mbist_si_i (mbist_si_i),
|
---|
552 | .mbist_so_o (mbist_s_0),
|
---|
553 | .mbist_ctrl_i (mbist_ctrl_i)
|
---|
554 | `endif
|
---|
555 | );
|
---|
556 |
|
---|
557 | `ifdef CAN_BIST
|
---|
558 | vs_hdtp_64x4_bist info_fifo
|
---|
559 | `else
|
---|
560 | vs_hdtp_64x4 info_fifo
|
---|
561 | `endif
|
---|
562 | (
|
---|
563 | .RCK (clk),
|
---|
564 | .WCK (clk),
|
---|
565 | .RADR (rd_info_pointer),
|
---|
566 | .WADR (wr_info_pointer),
|
---|
567 | .DI (len_cnt & {4{~initialize_memories}}),
|
---|
568 | .DOUT (length_info),
|
---|
569 | .REN (1'b0),
|
---|
570 | .WEN (~(write_length_info & (~info_full) | initialize_memories))
|
---|
571 | `ifdef CAN_BIST
|
---|
572 | ,
|
---|
573 | // debug chain signals
|
---|
574 | .mbist_si_i (mbist_s_0),
|
---|
575 | .mbist_so_o (mbist_so_o),
|
---|
576 | .mbist_ctrl_i (mbist_ctrl_i)
|
---|
577 | `endif
|
---|
578 | );
|
---|
579 |
|
---|
580 | // overrun_info
|
---|
581 | always @ (posedge clk)
|
---|
582 | begin
|
---|
583 | if (write_length_info & (~info_full) | initialize_memories)
|
---|
584 | overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
|
---|
585 | end
|
---|
586 |
|
---|
587 |
|
---|
588 | // reading overrun
|
---|
589 | assign overrun = overrun_info[rd_info_pointer];
|
---|
590 |
|
---|
591 | `else
|
---|
592 | `ifdef ARTISAN_RAM
|
---|
593 |
|
---|
594 | `ifdef CAN_BIST
|
---|
595 | art_hstp_64x8_bist fifo
|
---|
596 | (
|
---|
597 | .CLKR (clk),
|
---|
598 | .CLKW (clk),
|
---|
599 | .AR (read_address),
|
---|
600 | .AW (wr_pointer),
|
---|
601 | .D (data_in),
|
---|
602 | .Q (data_out),
|
---|
603 | .REN (~fifo_selected),
|
---|
604 | .WEN (~(wr & (~fifo_full))),
|
---|
605 | .mbist_si_i (mbist_si_i),
|
---|
606 | .mbist_so_o (mbist_s_0),
|
---|
607 | .mbist_ctrl_i (mbist_ctrl_i)
|
---|
608 | );
|
---|
609 | art_hstp_64x4_bist info_fifo
|
---|
610 | (
|
---|
611 | .CLKR (clk),
|
---|
612 | .CLKW (clk),
|
---|
613 | .AR (rd_info_pointer),
|
---|
614 | .AW (wr_info_pointer),
|
---|
615 | .D (len_cnt & {4{~initialize_memories}}),
|
---|
616 | .Q (length_info),
|
---|
617 | .REN (1'b0),
|
---|
618 | .WEN (~(write_length_info & (~info_full) | initialize_memories)),
|
---|
619 | .mbist_si_i (mbist_s_0),
|
---|
620 | .mbist_so_o (mbist_so_o),
|
---|
621 | .mbist_ctrl_i (mbist_ctrl_i)
|
---|
622 | );
|
---|
623 | `else
|
---|
624 | art_hsdp_64x8 fifo
|
---|
625 | (
|
---|
626 | .CENA (1'b0),
|
---|
627 | .CENB (1'b0),
|
---|
628 | .CLKA (clk),
|
---|
629 | .CLKB (clk),
|
---|
630 | .AA (read_address),
|
---|
631 | .AB (wr_pointer),
|
---|
632 | .DA (8'h00),
|
---|
633 | .DB (data_in),
|
---|
634 | .QA (data_out),
|
---|
635 | .QB (),
|
---|
636 | .OENA (~fifo_selected),
|
---|
637 | .OENB (1'b1),
|
---|
638 | .WENA (1'b1),
|
---|
639 | .WENB (~(wr & (~fifo_full)))
|
---|
640 | );
|
---|
641 | art_hsdp_64x4 info_fifo
|
---|
642 | (
|
---|
643 | .CENA (1'b0),
|
---|
644 | .CENB (1'b0),
|
---|
645 | .CLKA (clk),
|
---|
646 | .CLKB (clk),
|
---|
647 | .AA (rd_info_pointer),
|
---|
648 | .AB (wr_info_pointer),
|
---|
649 | .DA (4'h0),
|
---|
650 | .DB (len_cnt & {4{~initialize_memories}}),
|
---|
651 | .QA (length_info),
|
---|
652 | .QB (),
|
---|
653 | .OENA (1'b0),
|
---|
654 | .OENB (1'b1),
|
---|
655 | .WENA (1'b1),
|
---|
656 | .WENB (~(write_length_info & (~info_full) | initialize_memories))
|
---|
657 | );
|
---|
658 | `endif
|
---|
659 |
|
---|
660 | // overrun_info
|
---|
661 | always @ (posedge clk)
|
---|
662 | begin
|
---|
663 | if (write_length_info & (~info_full) | initialize_memories)
|
---|
664 | overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
|
---|
665 | end
|
---|
666 |
|
---|
667 |
|
---|
668 | // reading overrun
|
---|
669 | assign overrun = overrun_info[rd_info_pointer];
|
---|
670 |
|
---|
671 | `else
|
---|
672 | // writing data to fifo
|
---|
673 | always @ (posedge clk)
|
---|
674 | begin
|
---|
675 | if (wr & (~fifo_full))
|
---|
676 | fifo[wr_pointer] <=#Tp data_in;
|
---|
677 | end
|
---|
678 |
|
---|
679 | // reading from fifo
|
---|
680 | assign data_out = fifo[read_address];
|
---|
681 |
|
---|
682 |
|
---|
683 | // writing length_fifo
|
---|
684 | always @ (posedge clk)
|
---|
685 | begin
|
---|
686 | if (write_length_info & (~info_full) | initialize_memories)
|
---|
687 | length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
|
---|
688 | end
|
---|
689 |
|
---|
690 |
|
---|
691 | // reading length_fifo
|
---|
692 | assign length_info = length_fifo[rd_info_pointer];
|
---|
693 |
|
---|
694 | // overrun_info
|
---|
695 | always @ (posedge clk)
|
---|
696 | begin
|
---|
697 | if (write_length_info & (~info_full) | initialize_memories)
|
---|
698 | overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
|
---|
699 | end
|
---|
700 |
|
---|
701 |
|
---|
702 | // reading overrun
|
---|
703 | assign overrun = overrun_info[rd_info_pointer];
|
---|
704 |
|
---|
705 |
|
---|
706 | `endif
|
---|
707 | `endif
|
---|
708 | `endif
|
---|
709 | `endif
|
---|
710 | `endif
|
---|
711 |
|
---|
712 |
|
---|
713 |
|
---|
714 |
|
---|
715 |
|
---|
716 | endmodule
|
---|