1 | //////////////////////////////////////////////////////////////////////
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2 | //// ////
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3 | //// can_defines.v ////
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4 | //// ////
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5 | //// ////
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6 | //// This file is part of the CAN Protocol Controller ////
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7 | //// http://www.opencores.org/projects/can/ ////
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8 | //// ////
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9 | //// ////
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10 | //// Author(s): ////
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11 | //// Igor Mohor ////
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12 | //// igorm@opencores.org ////
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13 | //// ////
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14 | //// ////
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15 | //// All additional information is available in the README.txt ////
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16 | //// file. ////
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17 | //// ////
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18 | //////////////////////////////////////////////////////////////////////
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19 | //// ////
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20 | //// Copyright (C) 2002, 2003, 2004 Authors ////
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21 | //// ////
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22 | //// This source file may be used and distributed without ////
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23 | //// restriction provided that this copyright statement is not ////
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24 | //// removed from the file and that any derivative work contains ////
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25 | //// the original copyright notice and the associated disclaimer. ////
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26 | //// ////
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27 | //// This source file is free software; you can redistribute it ////
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28 | //// and/or modify it under the terms of the GNU Lesser General ////
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29 | //// Public License as published by the Free Software Foundation; ////
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30 | //// either version 2.1 of the License, or (at your option) any ////
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31 | //// later version. ////
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32 | //// ////
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33 | //// This source is distributed in the hope that it will be ////
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34 | //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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35 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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36 | //// PURPOSE. See the GNU Lesser General Public License for more ////
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37 | //// details. ////
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38 | //// ////
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39 | //// You should have received a copy of the GNU Lesser General ////
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40 | //// Public License along with this source; if not, download it ////
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41 | //// from http://www.opencores.org/lgpl.shtml ////
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42 | //// ////
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43 | //// The CAN protocol is developed by Robert Bosch GmbH and ////
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44 | //// protected by patents. Anybody who wants to implement this ////
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45 | //// CAN IP core on silicon has to obtain a CAN protocol license ////
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46 | //// from Bosch. ////
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47 | //// ////
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48 | //////////////////////////////////////////////////////////////////////
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49 | //
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50 | // CVS Revision History
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51 | //
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52 | // $Log: can_defines.v,v $
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53 | // Revision 1.14 2004/05/12 15:58:41 igorm
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54 | // Core improved to pass all tests with the Bosch VHDL Reference system.
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55 | //
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56 | // Revision 1.13 2004/02/08 14:28:03 mohor
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57 | // Header changed.
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58 | //
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59 | // Revision 1.12 2003/10/17 05:55:20 markom
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60 | // mbist signals updated according to newest convention
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61 | //
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62 | // Revision 1.11 2003/09/05 12:46:42 mohor
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63 | // ALTERA_RAM supported.
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64 | //
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65 | // Revision 1.10 2003/08/14 16:04:52 simons
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66 | // Artisan ram instances added.
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67 | //
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68 | // Revision 1.9 2003/06/27 20:56:15 simons
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69 | // Virtual silicon ram instances added.
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70 | //
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71 | // Revision 1.8 2003/06/09 11:32:36 mohor
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72 | // Ports added for the CAN_BIST.
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73 | //
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74 | // Revision 1.7 2003/03/20 16:51:55 mohor
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75 | // *** empty log message ***
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76 | //
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77 | // Revision 1.6 2003/03/12 04:19:13 mohor
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78 | // 8051 interface added (besides WISHBONE interface). Selection is made in
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79 | // can_defines.v file.
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80 | //
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81 | // Revision 1.5 2003/03/05 15:03:20 mohor
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82 | // Xilinx RAM added.
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83 | //
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84 | // Revision 1.4 2003/03/01 22:52:47 mohor
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85 | // Actel APA ram supported.
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86 | //
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87 | // Revision 1.3 2003/02/09 02:24:33 mohor
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88 | // Bosch license warning added. Error counters finished. Overload frames
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89 | // still need to be fixed.
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90 | //
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91 | // Revision 1.2 2002/12/27 00:12:52 mohor
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92 | // Header changed, testbench improved to send a frame (crc still missing).
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93 | //
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94 | // Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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95 | // Initial
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96 | //
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97 | //
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98 | //
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99 |
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100 |
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101 | // Uncomment following line if you want to use WISHBONE interface. Otherwise
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102 | // 8051 interface is used.
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103 | // `define CAN_WISHBONE_IF
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104 | `define CAN_AVALON_IF
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105 |
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106 | // Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
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107 | // `define ACTEL_APA_RAM
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108 |
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109 | // Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
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110 | //`define ALTERA_RAM
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111 |
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112 | // Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
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113 | // `define XILINX_RAM
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114 |
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115 | // Uncomment the line for the ram used in ASIC implementation
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116 | // `define VIRTUALSILICON_RAM
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117 | // `define ARTISAN_RAM
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118 |
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119 | // Uncomment the following line when RAM BIST is needed (ASIC implementation)
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120 | //`define CAN_BIST // Bist (for ASIC implementation)
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121 |
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122 | /* width of MBIST control bus */
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123 | //`define CAN_MBIST_CTRL_WIDTH 3
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124 |
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