1 | //////////////////////////////////////////////////////////////////////
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2 | //// ////
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3 | //// can_btl.v ////
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4 | //// ////
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5 | //// ////
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6 | //// This file is part of the CAN Protocol Controller ////
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7 | //// http://www.opencores.org/projects/can/ ////
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8 | //// ////
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9 | //// ////
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10 | //// Author(s): ////
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11 | //// Igor Mohor ////
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12 | //// igorm@opencores.org ////
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13 | //// ////
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14 | //// ////
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15 | //// All additional information is available in the README.txt ////
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16 | //// file. ////
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17 | //// ////
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18 | //////////////////////////////////////////////////////////////////////
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19 | //// ////
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20 | //// Copyright (C) 2002, 2003, 2004 Authors ////
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21 | //// ////
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22 | //// This source file may be used and distributed without ////
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23 | //// restriction provided that this copyright statement is not ////
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24 | //// removed from the file and that any derivative work contains ////
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25 | //// the original copyright notice and the associated disclaimer. ////
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26 | //// ////
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27 | //// This source file is free software; you can redistribute it ////
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28 | //// and/or modify it under the terms of the GNU Lesser General ////
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29 | //// Public License as published by the Free Software Foundation; ////
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30 | //// either version 2.1 of the License, or (at your option) any ////
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31 | //// later version. ////
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32 | //// ////
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33 | //// This source is distributed in the hope that it will be ////
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34 | //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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35 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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36 | //// PURPOSE. See the GNU Lesser General Public License for more ////
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37 | //// details. ////
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38 | //// ////
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39 | //// You should have received a copy of the GNU Lesser General ////
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40 | //// Public License along with this source; if not, download it ////
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41 | //// from http://www.opencores.org/lgpl.shtml ////
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42 | //// ////
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43 | //// The CAN protocol is developed by Robert Bosch GmbH and ////
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44 | //// protected by patents. Anybody who wants to implement this ////
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45 | //// CAN IP core on silicon has to obtain a CAN protocol license ////
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46 | //// from Bosch. ////
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47 | //// ////
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48 | //////////////////////////////////////////////////////////////////////
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49 | //
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50 | // CVS Revision History
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51 | //
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52 | // $Log: can_btl.v,v $
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53 | // Revision 1.30 2004/10/27 18:51:37 igorm
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54 | // Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
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55 | //
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56 | // Revision 1.29 2004/05/12 15:58:41 igorm
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57 | // Core improved to pass all tests with the Bosch VHDL Reference system.
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58 | //
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59 | // Revision 1.28 2004/02/08 14:25:26 mohor
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60 | // Header changed.
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61 | //
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62 | // Revision 1.27 2003/09/30 00:55:13 mohor
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63 | // Error counters fixed to be compatible with Bosch VHDL reference model.
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64 | // Small synchronization changes.
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65 | //
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66 | // Revision 1.26 2003/09/25 18:55:49 mohor
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67 | // Synchronization changed, error counters fixed.
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68 | //
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69 | // Revision 1.25 2003/07/16 13:40:35 mohor
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70 | // Fixed according to the linter.
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71 | //
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72 | // Revision 1.24 2003/07/10 15:32:28 mohor
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73 | // Unused signal removed.
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74 | //
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75 | // Revision 1.23 2003/07/10 01:59:04 tadejm
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76 | // Synchronization fixed. In some strange cases it didn't work according to
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77 | // the VHDL reference model.
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78 | //
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79 | // Revision 1.22 2003/07/07 11:21:37 mohor
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80 | // Little fixes (to fix warnings).
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81 | //
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82 | // Revision 1.21 2003/07/03 09:32:20 mohor
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83 | // Synchronization changed.
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84 | //
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85 | // Revision 1.20 2003/06/20 14:51:11 mohor
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86 | // Previous change removed. When resynchronization occurs we go to seg1
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87 | // stage. sync stage does not cause another start of seg1 stage.
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88 | //
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89 | // Revision 1.19 2003/06/20 14:28:20 mohor
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90 | // When hard_sync or resync occure we need to go to seg1 segment. Going to
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91 | // sync segment is in that case blocked.
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92 | //
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93 | // Revision 1.18 2003/06/17 15:53:33 mohor
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94 | // clk_cnt reduced from [8:0] to [6:0].
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95 | //
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96 | // Revision 1.17 2003/06/17 14:32:17 mohor
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97 | // Removed few signals.
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98 | //
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99 | // Revision 1.16 2003/06/16 13:57:58 mohor
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100 | // tx_point generated one clk earlier. rx_i registered. Data corrected when
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101 | // using extended mode.
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102 | //
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103 | // Revision 1.15 2003/06/13 15:02:24 mohor
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104 | // Synchronization is also needed when transmitting a message.
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105 | //
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106 | // Revision 1.14 2003/06/13 14:55:11 mohor
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107 | // Counters width changed.
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108 | //
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109 | // Revision 1.13 2003/06/11 14:21:35 mohor
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110 | // When switching to tx, sync stage is overjumped.
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111 | //
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112 | // Revision 1.12 2003/02/14 20:17:01 mohor
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113 | // Several registers added. Not finished, yet.
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114 | //
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115 | // Revision 1.11 2003/02/09 18:40:29 mohor
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116 | // Overload fixed. Hard synchronization also enabled at the last bit of
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117 | // interframe.
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118 | //
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119 | // Revision 1.10 2003/02/09 02:24:33 mohor
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120 | // Bosch license warning added. Error counters finished. Overload frames
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121 | // still need to be fixed.
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122 | //
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123 | // Revision 1.9 2003/01/31 01:13:38 mohor
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124 | // backup.
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125 | //
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126 | // Revision 1.8 2003/01/10 17:51:34 mohor
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127 | // Temporary version (backup).
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128 | //
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129 | // Revision 1.7 2003/01/08 02:10:53 mohor
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130 | // Acceptance filter added.
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131 | //
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132 | // Revision 1.6 2002/12/28 04:13:23 mohor
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133 | // Backup version.
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134 | //
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135 | // Revision 1.5 2002/12/27 00:12:52 mohor
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136 | // Header changed, testbench improved to send a frame (crc still missing).
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137 | //
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138 | // Revision 1.4 2002/12/26 01:33:05 mohor
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139 | // Tripple sampling supported.
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140 | //
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141 | // Revision 1.3 2002/12/25 23:44:16 mohor
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142 | // Commented lines removed.
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143 | //
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144 | // Revision 1.2 2002/12/25 14:17:00 mohor
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145 | // Synchronization working.
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146 | //
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147 | // Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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148 | // Initial
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149 | //
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150 | //
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151 | //
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152 |
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153 | // synopsys translate_off
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154 | `include "timescale.v"
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155 | // synopsys translate_on
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156 | `include "can_defines.v"
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157 |
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158 | module can_btl
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159 | (
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160 | clk,
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161 | rst,
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162 | rx,
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163 | tx,
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164 |
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165 | /* Bus Timing 0 register */
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166 | baud_r_presc,
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167 | sync_jump_width,
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168 |
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169 | /* Bus Timing 1 register */
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170 | time_segment1,
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171 | time_segment2,
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172 | triple_sampling,
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173 |
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174 | /* Output signals from this module */
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175 | sample_point,
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176 | sampled_bit,
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177 | sampled_bit_q,
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178 | tx_point,
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179 | hard_sync,
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180 |
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181 | /* Output from can_bsp module */
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182 | rx_idle,
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183 | rx_inter,
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184 | transmitting,
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185 | transmitter,
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186 | go_rx_inter,
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187 | tx_next,
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188 |
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189 | go_overload_frame,
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190 | go_error_frame,
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191 | go_tx,
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192 | send_ack,
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193 | node_error_passive
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194 | );
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195 |
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196 | parameter Tp = 1;
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197 |
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198 | input clk;
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199 | input rst;
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200 | input rx;
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201 | input tx;
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202 |
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203 |
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204 | /* Bus Timing 0 register */
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205 | input [5:0] baud_r_presc;
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206 | input [1:0] sync_jump_width;
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207 |
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208 | /* Bus Timing 1 register */
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209 | input [3:0] time_segment1;
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210 | input [2:0] time_segment2;
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211 | input triple_sampling;
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212 |
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213 | /* Output from can_bsp module */
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214 | input rx_idle;
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215 | input rx_inter;
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216 | input transmitting;
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217 | input transmitter;
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218 | input go_rx_inter;
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219 | input tx_next;
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220 |
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221 | input go_overload_frame;
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222 | input go_error_frame;
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223 | input go_tx;
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224 | input send_ack;
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225 | input node_error_passive;
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226 |
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227 | /* Output signals from this module */
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228 | output sample_point;
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229 | output sampled_bit;
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230 | output sampled_bit_q;
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231 | output tx_point;
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232 | output hard_sync;
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233 |
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234 | reg [6:0] clk_cnt;
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235 | reg clk_en;
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236 | reg clk_en_q;
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237 | reg sync_blocked;
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238 | reg hard_sync_blocked;
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239 | reg sampled_bit;
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240 | reg sampled_bit_q;
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241 | reg [4:0] quant_cnt;
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242 | reg [3:0] delay;
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243 | reg sync;
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244 | reg seg1;
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245 | reg seg2;
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246 | reg resync_latched;
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247 | reg sample_point;
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248 | reg [1:0] sample;
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249 | reg tx_point;
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250 | reg tx_next_sp;
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251 |
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252 | wire go_sync;
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253 | wire go_seg1;
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254 | wire go_seg2;
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255 | wire [7:0] preset_cnt;
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256 | wire sync_window;
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257 | wire resync;
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258 |
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259 |
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260 | assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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261 | assign hard_sync = (rx_idle | rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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262 | assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
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263 |
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264 |
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265 |
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266 | /* Generating general enable signal that defines baud rate. */
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267 | always @ (posedge clk or posedge rst)
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268 | begin
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269 | if (rst)
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270 | clk_cnt <= 7'h0;
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271 | else if (clk_cnt >= (preset_cnt-1'b1))
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272 | clk_cnt <=#Tp 7'h0;
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273 | else
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274 | clk_cnt <=#Tp clk_cnt + 1'b1;
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275 | end
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276 |
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277 |
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278 | always @ (posedge clk or posedge rst)
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279 | begin
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280 | if (rst)
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281 | clk_en <= 1'b0;
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282 | else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))
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283 | clk_en <=#Tp 1'b1;
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284 | else
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285 | clk_en <=#Tp 1'b0;
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286 | end
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287 |
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288 |
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289 |
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290 | always @ (posedge clk or posedge rst)
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291 | begin
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292 | if (rst)
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293 | clk_en_q <= 1'b0;
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294 | else
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295 | clk_en_q <=#Tp clk_en;
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296 | end
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297 |
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298 |
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299 |
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300 | /* Changing states */
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301 | assign go_sync = clk_en_q & seg2 & (quant_cnt[2:0] == time_segment2) & (~hard_sync) & (~resync);
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302 | assign go_seg1 = clk_en_q & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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303 | assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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304 |
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305 |
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306 |
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307 | always @ (posedge clk or posedge rst)
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308 | begin
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309 | if (rst)
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310 | tx_point <= 1'b0;
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311 | else
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312 | tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2)
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313 | | (clk_en | clk_en_q) & (resync | hard_sync)
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314 | ); // When transmitter we should transmit as soon as possible.
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315 | end
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316 |
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317 |
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318 |
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319 | /* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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320 | SJW is reached */
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321 | always @ (posedge clk or posedge rst)
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322 | begin
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323 | if (rst)
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324 | resync_latched <= 1'b0;
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325 | else if (resync & seg2 & (~sync_window))
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326 | resync_latched <=#Tp 1'b1;
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327 | else if (go_seg1)
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328 | resync_latched <= 1'b0;
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329 | end
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330 |
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331 |
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332 |
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333 | /* Synchronization stage/segment */
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334 | always @ (posedge clk or posedge rst)
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335 | begin
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336 | if (rst)
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337 | sync <= 1'b0;
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338 | else if (clk_en_q)
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339 | sync <=#Tp go_sync;
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340 | end
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341 |
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342 |
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343 | /* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
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344 | always @ (posedge clk or posedge rst)
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345 | begin
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346 | if (rst)
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347 | seg1 <= 1'b1;
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348 | else if (go_seg1)
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349 | seg1 <=#Tp 1'b1;
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350 | else if (go_seg2)
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351 | seg1 <=#Tp 1'b0;
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352 | end
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353 |
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354 |
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355 | /* Seg2 stage/segment */
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356 | always @ (posedge clk or posedge rst)
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357 | begin
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358 | if (rst)
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359 | seg2 <= 1'b0;
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360 | else if (go_seg2)
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361 | seg2 <=#Tp 1'b1;
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362 | else if (go_sync | go_seg1)
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363 | seg2 <=#Tp 1'b0;
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364 | end
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365 |
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366 |
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367 | /* Quant counter */
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368 | always @ (posedge clk or posedge rst)
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369 | begin
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370 | if (rst)
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371 | quant_cnt <= 5'h0;
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372 | else if (go_sync | go_seg1 | go_seg2)
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373 | quant_cnt <=#Tp 5'h0;
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374 | else if (clk_en_q)
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375 | quant_cnt <=#Tp quant_cnt + 1'b1;
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376 | end
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377 |
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378 |
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379 | /* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
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380 | always @ (posedge clk or posedge rst)
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381 | begin
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382 | if (rst)
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383 | delay <= 4'h0;
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384 | else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx))))) // when transmitting 0 with positive error delay is set to 0
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385 | delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
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386 | else if (go_sync | go_seg1)
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387 | delay <=#Tp 4'h0;
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388 | end
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389 |
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390 |
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391 | // If early edge appears within this window (in seg2 stage), phase error is fully compensated
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392 | assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
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393 |
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394 |
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395 | // Sampling data (memorizing two samples all the time).
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396 | always @ (posedge clk or posedge rst)
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397 | begin
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398 | if (rst)
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399 | sample <= 2'b11;
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400 | else if (clk_en_q)
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401 | sample <= {sample[0], rx};
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402 | end
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403 |
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404 |
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405 | // When enabled, tripple sampling is done here.
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406 | always @ (posedge clk or posedge rst)
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407 | begin
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408 | if (rst)
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409 | begin
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410 | sampled_bit <= 1'b1;
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411 | sampled_bit_q <= 1'b1;
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412 | sample_point <= 1'b0;
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413 | end
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414 | else if (go_error_frame)
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415 | begin
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416 | sampled_bit_q <=#Tp sampled_bit;
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417 | sample_point <=#Tp 1'b0;
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418 | end
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419 | else if (clk_en_q & (~hard_sync))
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420 | begin
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421 | if (seg1 & (quant_cnt == (time_segment1 + delay)))
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422 | begin
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423 | sample_point <=#Tp 1'b1;
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424 | sampled_bit_q <=#Tp sampled_bit;
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425 | if (triple_sampling)
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426 | sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
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427 | else
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428 | sampled_bit <=#Tp rx;
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429 | end
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430 | end
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431 | else
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432 | sample_point <=#Tp 1'b0;
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433 | end
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434 |
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435 |
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436 | // tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
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437 | // need to synchronize (even when we are a transmitter)
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438 | always @ (posedge clk or posedge rst)
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439 | begin
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440 | if (rst)
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441 | tx_next_sp <= 1'b0;
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442 | else if (go_overload_frame | (go_error_frame & (~node_error_passive)) | go_tx | send_ack)
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443 | tx_next_sp <=#Tp 1'b0;
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444 | else if (go_error_frame & node_error_passive)
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445 | tx_next_sp <=#Tp 1'b1;
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446 | else if (sample_point)
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447 | tx_next_sp <=#Tp tx_next;
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448 | end
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449 |
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450 |
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451 |
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452 | /* Blocking synchronization (can occur only once in a bit time) */
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453 |
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454 | always @ (posedge clk or posedge rst)
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455 | begin
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456 | if (rst)
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457 | sync_blocked <=#Tp 1'b1;
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458 | else if (clk_en_q)
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459 | begin
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460 | if (resync)
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461 | sync_blocked <=#Tp 1'b1;
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462 | else if (go_seg2)
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463 | sync_blocked <=#Tp 1'b0;
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464 | end
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465 | end
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466 |
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467 |
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468 | /* Blocking hard synchronization when occurs once or when we are transmitting a msg */
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469 | always @ (posedge clk or posedge rst)
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470 | begin
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471 | if (rst)
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472 | hard_sync_blocked <=#Tp 1'b0;
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473 | else if (hard_sync & clk_en_q | (transmitting & transmitter | go_tx) & tx_point & (~tx_next))
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474 | hard_sync_blocked <=#Tp 1'b1;
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475 | else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization
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476 | hard_sync_blocked <=#Tp 1'b0;
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477 | end
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478 |
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479 |
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480 |
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481 |
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482 |
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483 | endmodule
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484 |
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