source: rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/DE0_Nano.v@ 295

Last change on this file since 295 was 128, checked in by ertl-honda, 9 years ago

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1// --------------------------------------------------------------------
2// Copyright (c) 2011 by Terasic Technologies Inc.
3// --------------------------------------------------------------------
4//
5// Permission:
6//
7// Terasic grants permission to use and modify this code for use
8// in synthesis for all Terasic Development Boards and Altera Development
9// Kits made by Terasic. Other use of this code, including the selling
10// ,duplication, or modification of any portion is strictly prohibited.
11//
12// Disclaimer:
13//
14// This VHDL/Verilog or C/C++ source code is intended as a design reference
15// which illustrates how these types of functions can be implemented.
16// It is the user's responsibility to verify their design for
17// consistency and functionality through the use of formal
18// verification methods. Terasic provides no warranty regarding the use
19// or functionality of this code.
20//
21// --------------------------------------------------------------------
22//
23// Terasic Technologies Inc
24// E. Rd Sec. 1. JhuBei City,
25// HsinChu County, Taiwan
26// 302
27//
28// web: http://www.terasic.com/
29// email: support@terasic.com
30//
31// --------------------------------------------------------------------
32
33module DE0_Nano(
34
35 //////////// CLOCK //////////
36 CLOCK_50,
37
38 //////////// LED //////////
39 LED,
40
41 //////////// KEY //////////
42 KEY,
43
44 //////////// SW //////////
45 SW,
46
47 //////////// SDRAM //////////
48 DRAM_ADDR,
49 DRAM_BA,
50 DRAM_CAS_N,
51 DRAM_CKE,
52 DRAM_CLK,
53 DRAM_CS_N,
54 DRAM_DQ,
55 DRAM_DQM,
56 DRAM_RAS_N,
57 DRAM_WE_N,
58
59 //////////// ECPS //////////
60 EPCS_ASDO,
61 EPCS_DATA0,
62 EPCS_DCLK,
63 EPCS_NCSO,
64
65 //////////// Accelerometer and EEPROM //////////
66 G_SENSOR_CS_N,
67 G_SENSOR_INT,
68 I2C_SCLK,
69 I2C_SDAT,
70
71 //////////// ADC //////////
72 ADC_CS_N,
73 ADC_SADDR,
74 ADC_SCLK,
75 ADC_SDAT,
76
77 //////////// 2x13 GPIO Header //////////
78 GPIO_2,
79 GPIO_2_IN,
80
81 //////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
82 GPIO_0,
83 GPIO_0_IN,
84
85 //////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
86 GPIO_1,
87 GPIO_1_IN
88);
89
90//=======================================================
91// PARAMETER declarations
92//=======================================================
93
94
95//=======================================================
96// PORT declarations
97//=======================================================
98
99//////////// CLOCK //////////
100input CLOCK_50;
101
102//////////// LED //////////
103output [7:0] LED;
104
105//////////// KEY //////////
106input [1:0] KEY;
107
108//////////// SW //////////
109input [3:0] SW;
110
111//////////// SDRAM //////////
112output [12:0] DRAM_ADDR;
113output [1:0] DRAM_BA;
114output DRAM_CAS_N;
115output DRAM_CKE;
116output DRAM_CLK;
117output DRAM_CS_N;
118inout [15:0] DRAM_DQ;
119output [1:0] DRAM_DQM;
120output DRAM_RAS_N;
121output DRAM_WE_N;
122
123//////////// EPCS //////////
124output EPCS_ASDO;
125input EPCS_DATA0;
126output EPCS_DCLK;
127output EPCS_NCSO;
128
129//////////// Accelerometer and EEPROM //////////
130output G_SENSOR_CS_N;
131input G_SENSOR_INT;
132output I2C_SCLK;
133inout I2C_SDAT;
134
135//////////// ADC //////////
136output ADC_CS_N;
137output ADC_SADDR;
138output ADC_SCLK;
139input ADC_SDAT;
140
141//////////// 2x13 GPIO Header //////////
142inout [12:0] GPIO_2;
143input [2:0] GPIO_2_IN;
144
145//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
146inout [33:0] GPIO_0;
147input [1:0] GPIO_0_IN;
148
149//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
150inout [33:0] GPIO_1;
151input [1:0] GPIO_1_IN;
152
153
154//=======================================================
155// REG/WIRE declarations
156//=======================================================
157wire reset_n;
158wire select_i2c_clk;
159wire i2c_clk;
160wire spi_clk;
161
162
163
164//=======================================================
165// Structural coding
166//=======================================================
167
168assign reset_n = 1'b1;
169
170DE0_Nano_SOPC DE0_Nano_SOPC_inst(
171 // 1) global signals:
172 .altpll_io(),
173 .altpll_sdram(DRAM_CLK),
174 .altpll_sys(),
175 .clk_50(CLOCK_50),
176// .clk_50_clk_in_reset_reset_n(reset_n),
177 .clk_50_clk_in_reset_reset_n(KEY[0]),
178
179 // the_select_i2c_clk
180 .out_port_from_the_select_i2c_clk(select_i2c_clk),
181
182
183 // the_adc_spi_read
184 .SPI_CLK_from_the_adc_spi_read(ADC_SCLK),
185 .SPI_CS_n_from_the_adc_spi_read(ADC_CS_N),
186 .SPI_IN_to_the_adc_spi_read(ADC_SDAT),
187 .SPI_OUT_from_the_adc_spi_read(ADC_SADDR),
188
189
190 // the_altpll_0
191 .locked_from_the_altpll_0(),
192 .phasedone_from_the_altpll_0(),
193
194 // the_epcs
195 .data0_to_the_epcs(EPCS_DATA0),
196 .dclk_from_the_epcs(EPCS_DCLK),
197 .sce_from_the_epcs(EPCS_NCSO),
198 .sdo_from_the_epcs(EPCS_ASDO),
199
200
201 // the_gsensor_spi
202 .SPI_CS_n_from_the_gsensor_spi(G_SENSOR_CS_N),
203 .SPI_SCLK_from_the_gsensor_spi(spi_clk),
204 .SPI_SDIO_to_and_from_the_gsensor_spi(I2C_SDAT),
205
206
207 // the_g_sensor_int
208 .in_port_to_the_g_sensor_int(G_SENSOR_INT),
209
210 // the_i2c_scl
211 .out_port_from_the_i2c_scl(i2c_clk),
212
213 // the_i2c_sda
214 .bidir_port_to_and_from_the_i2c_sda(I2C_SDAT),
215
216 // the_key
217 .in_port_to_the_key(KEY),
218
219 // the_led
220 .out_port_from_the_led(LED),
221
222 // the_sdram
223 .zs_addr_from_the_sdram(DRAM_ADDR),
224 .zs_ba_from_the_sdram(DRAM_BA),
225 .zs_cas_n_from_the_sdram(DRAM_CAS_N),
226 .zs_cke_from_the_sdram(DRAM_CKE),
227 .zs_cs_n_from_the_sdram(DRAM_CS_N),
228 .zs_dq_to_and_from_the_sdram(DRAM_DQ),
229 .zs_dqm_from_the_sdram(DRAM_DQM),
230 .zs_ras_n_from_the_sdram(DRAM_RAS_N),
231 .zs_we_n_from_the_sdram(DRAM_WE_N),
232
233 // the_can_top_0-ch1
234 .can_top_0_conduit_end_rx_i(GPIO_2[2]),
235 .can_top_0_conduit_end_tx_o(GPIO_2[0]),
236
237 // the_can_top_1-ch2
238// .can_top_0_conduit_end_rx_i(GPIO_2[6]),
239// .can_top_0_conduit_end_tx_o(GPIO_2[4]),
240
241 // UART-ch1
242 .uart_0_external_connection_rxd(GPIO_2[12]),
243 .uart_0_external_connection_txd(GPIO_2[10]),
244
245 // UART-ch2
246// .uart_1_external_connection_rxd(GPIO_2[3]),
247// .uart_1_external_connection_txd(GPIO_2[1]),
248// .uart_1_external_connection_rxd(GPIO_0[24]),
249// .uart_1_external_connection_txd(GPIO_0[25]),
250 .uart_1_external_connection_rxd(GPIO_1[2]),
251 .uart_1_external_connection_txd(GPIO_1[3]),
252
253// .pio_0_external_connection_export(GPIO_0[7:0]),
254// .pio_0_external_connection_export(GPIO_1[15:8]),
255 .pio_0_external_connection_export(GPIO_1[31:24]),
256
257 .multi_pwm_0_conduit_end_pwm1(GPIO_0[2]),
258 .multi_pwm_0_conduit_end_pwm2(GPIO_0[3]),
259 .multi_pwm_0_conduit_end_pwm3(GPIO_0[4]),
260 .multi_pwm_0_conduit_end_pwm4(GPIO_0[5]),
261 .multi_pwm_0_conduit_end_pwm5(GPIO_0[6]),
262 .multi_pwm_0_conduit_end_pwm6(GPIO_0[7]),
263
264 // the_sw
265 .in_port_to_the_sw(SW)
266 );
267
268
269assign I2C_SCLK = (select_i2c_clk)?i2c_clk:spi_clk;
270
271endmodule
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