source: rc_os_nios2/DE0_Nano_QSYS_DEMO/sysver/sysver_hw.tcl@ 128

Last change on this file since 128 was 128, checked in by ertl-honda, 9 years ago

追加．
File size: 5.9 KB
Line 
1# TCL File Generated by Component Editor 8.1
2# Fri Aug 28 12:47:32 JST 2009
3# DO NOT MODIFY
4
5
6# +-----------------------------------
7# |
8# | sysver "sysver" v1.0
9# | null 2009.08.28.12:47:32
10# |
11# |
12# | C:/home/nces/os/hw/queuing_lock/1s40_dual_fmp/sysver/sysver.vhd
13# |
14# | ./sysver.vhd syn, sim
15# |
16# +-----------------------------------
17
18
19# +-----------------------------------
20# | module sysver
21# |
22set_module_property NAME sysver
23set_module_property VERSION 1.0
24set_module_property GROUP Other
25set_module_property DISPLAY_NAME sysver
26set_module_property LIBRARIES {ieee.std_logic_1164.all std.standard.all}
27set_module_property TOP_LEVEL_HDL_FILE sysver.vhd
28set_module_property TOP_LEVEL_HDL_MODULE sysver
29set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
30set_module_property EDITABLE false
31# |
32# +-----------------------------------
33
34# +-----------------------------------
35# | files
36# |
37add_file sysver.vhd {SYNTHESIS SIMULATION}
38# |
39# +-----------------------------------
40
41# +-----------------------------------
42# | parameters
43# |
44add_parameter VER1_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
45set_parameter_property VER1_ROM_REG_VALUE DISPLAY_NAME VER1_ROM_REG_VALUE
46set_parameter_property VER1_ROM_REG_VALUE UNITS None
47set_parameter_property VER1_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
48set_parameter_property VER1_ROM_REG_VALUE DESCRIPTION ""
49set_parameter_property VER1_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
50add_parameter VER2_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
51set_parameter_property VER2_ROM_REG_VALUE DISPLAY_NAME VER2_ROM_REG_VALUE
52set_parameter_property VER2_ROM_REG_VALUE UNITS None
53set_parameter_property VER2_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
54set_parameter_property VER2_ROM_REG_VALUE DESCRIPTION ""
55set_parameter_property VER2_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
56add_parameter VER3_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
57set_parameter_property VER3_ROM_REG_VALUE DISPLAY_NAME VER3_ROM_REG_VALUE
58set_parameter_property VER3_ROM_REG_VALUE UNITS None
59set_parameter_property VER3_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
60set_parameter_property VER3_ROM_REG_VALUE DESCRIPTION ""
61set_parameter_property VER3_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
62add_parameter VER4_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
63set_parameter_property VER4_ROM_REG_VALUE DISPLAY_NAME VER4_ROM_REG_VALUE
64set_parameter_property VER4_ROM_REG_VALUE UNITS None
65set_parameter_property VER4_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
66set_parameter_property VER4_ROM_REG_VALUE DESCRIPTION ""
67set_parameter_property VER4_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
68add_parameter VER5_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
69set_parameter_property VER5_RAM_REG_VALUE DISPLAY_NAME VER5_RAM_REG_VALUE
70set_parameter_property VER5_RAM_REG_VALUE UNITS None
71set_parameter_property VER5_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
72set_parameter_property VER5_RAM_REG_VALUE DESCRIPTION ""
73set_parameter_property VER5_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
74add_parameter VER6_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
75set_parameter_property VER6_RAM_REG_VALUE DISPLAY_NAME VER6_RAM_REG_VALUE
76set_parameter_property VER6_RAM_REG_VALUE UNITS None
77set_parameter_property VER6_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
78set_parameter_property VER6_RAM_REG_VALUE DESCRIPTION ""
79set_parameter_property VER6_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
80add_parameter VER7_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
81set_parameter_property VER7_RAM_REG_VALUE DISPLAY_NAME VER7_RAM_REG_VALUE
82set_parameter_property VER7_RAM_REG_VALUE UNITS None
83set_parameter_property VER7_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
84set_parameter_property VER7_RAM_REG_VALUE DESCRIPTION ""
85set_parameter_property VER7_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
86add_parameter VER8_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
87set_parameter_property VER8_RAM_REG_VALUE DISPLAY_NAME VER8_RAM_REG_VALUE
88set_parameter_property VER8_RAM_REG_VALUE UNITS None
89set_parameter_property VER8_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
90set_parameter_property VER8_RAM_REG_VALUE DESCRIPTION ""
91set_parameter_property VER8_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
92# |
93# +-----------------------------------
94
95# +-----------------------------------
96# | connection point clock_reset
97# |
98add_interface clock_reset clock end
99set_interface_property clock_reset ptfSchematicName ""
100
101add_interface_port clock_reset clk clk Input 1
102add_interface_port clock_reset reset_n reset_n Input 1
103# |
104# +-----------------------------------
105
106# +-----------------------------------
107# | connection point avalon_slave_0
108# |
109add_interface avalon_slave_0 avalon end
110set_interface_property avalon_slave_0 addressAlignment DYNAMIC
111set_interface_property avalon_slave_0 addressSpan 32
112set_interface_property avalon_slave_0 bridgesToMaster ""
113set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
114set_interface_property avalon_slave_0 holdTime 0
115set_interface_property avalon_slave_0 isMemoryDevice false
116set_interface_property avalon_slave_0 isNonVolatileStorage false
117set_interface_property avalon_slave_0 linewrapBursts false
118set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
119set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
120set_interface_property avalon_slave_0 printableDevice false
121set_interface_property avalon_slave_0 readLatency 0
122set_interface_property avalon_slave_0 readWaitTime 1
123set_interface_property avalon_slave_0 setupTime 0
124set_interface_property avalon_slave_0 timingUnits Cycles
125set_interface_property avalon_slave_0 writeWaitTime 0
126
127set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset
128
129add_interface_port avalon_slave_0 chipselect chipselect Input 1
130add_interface_port avalon_slave_0 address address Input 3
131add_interface_port avalon_slave_0 write write Input 1
132add_interface_port avalon_slave_0 writedata writedata Input 32
133add_interface_port avalon_slave_0 read read Input 1
134add_interface_port avalon_slave_0 readdata readdata Output 32
135add_interface_port avalon_slave_0 byteenable byteenable Input 4
136add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
137# |
138# +-----------------------------------
Note: See TracBrowser for help on using the repository browser.