1 | # TCL File Generated by Component Editor 8.1
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2 | # Fri Aug 28 12:47:32 JST 2009
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3 | # DO NOT MODIFY
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4 |
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5 |
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6 | # +-----------------------------------
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7 | # |
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8 | # | sysver "sysver" v1.0
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9 | # | null 2009.08.28.12:47:32
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10 | # |
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11 | # |
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12 | # | C:/home/nces/os/hw/queuing_lock/1s40_dual_fmp/sysver/sysver.vhd
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13 | # |
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14 | # | ./sysver.vhd syn, sim
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15 | # |
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16 | # +-----------------------------------
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17 |
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18 |
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19 | # +-----------------------------------
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20 | # | module sysver
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21 | # |
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22 | set_module_property NAME sysver
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23 | set_module_property VERSION 1.0
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24 | set_module_property GROUP Other
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25 | set_module_property DISPLAY_NAME sysver
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26 | set_module_property LIBRARIES {ieee.std_logic_1164.all std.standard.all}
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27 | set_module_property TOP_LEVEL_HDL_FILE sysver.vhd
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28 | set_module_property TOP_LEVEL_HDL_MODULE sysver
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29 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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30 | set_module_property EDITABLE false
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31 | # |
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32 | # +-----------------------------------
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33 |
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34 | # +-----------------------------------
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35 | # | files
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36 | # |
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37 | add_file sysver.vhd {SYNTHESIS SIMULATION}
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38 | # |
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39 | # +-----------------------------------
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40 |
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41 | # +-----------------------------------
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42 | # | parameters
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43 | # |
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44 | add_parameter VER1_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
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45 | set_parameter_property VER1_ROM_REG_VALUE DISPLAY_NAME VER1_ROM_REG_VALUE
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46 | set_parameter_property VER1_ROM_REG_VALUE UNITS None
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47 | set_parameter_property VER1_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
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48 | set_parameter_property VER1_ROM_REG_VALUE DESCRIPTION ""
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49 | set_parameter_property VER1_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
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50 | add_parameter VER2_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
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51 | set_parameter_property VER2_ROM_REG_VALUE DISPLAY_NAME VER2_ROM_REG_VALUE
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52 | set_parameter_property VER2_ROM_REG_VALUE UNITS None
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53 | set_parameter_property VER2_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
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54 | set_parameter_property VER2_ROM_REG_VALUE DESCRIPTION ""
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55 | set_parameter_property VER2_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
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56 | add_parameter VER3_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
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57 | set_parameter_property VER3_ROM_REG_VALUE DISPLAY_NAME VER3_ROM_REG_VALUE
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58 | set_parameter_property VER3_ROM_REG_VALUE UNITS None
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59 | set_parameter_property VER3_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
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60 | set_parameter_property VER3_ROM_REG_VALUE DESCRIPTION ""
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61 | set_parameter_property VER3_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
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62 | add_parameter VER4_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
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63 | set_parameter_property VER4_ROM_REG_VALUE DISPLAY_NAME VER4_ROM_REG_VALUE
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64 | set_parameter_property VER4_ROM_REG_VALUE UNITS None
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65 | set_parameter_property VER4_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
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66 | set_parameter_property VER4_ROM_REG_VALUE DESCRIPTION ""
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67 | set_parameter_property VER4_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
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68 | add_parameter VER5_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
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69 | set_parameter_property VER5_RAM_REG_VALUE DISPLAY_NAME VER5_RAM_REG_VALUE
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70 | set_parameter_property VER5_RAM_REG_VALUE UNITS None
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71 | set_parameter_property VER5_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
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72 | set_parameter_property VER5_RAM_REG_VALUE DESCRIPTION ""
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73 | set_parameter_property VER5_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
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74 | add_parameter VER6_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
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75 | set_parameter_property VER6_RAM_REG_VALUE DISPLAY_NAME VER6_RAM_REG_VALUE
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76 | set_parameter_property VER6_RAM_REG_VALUE UNITS None
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77 | set_parameter_property VER6_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
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78 | set_parameter_property VER6_RAM_REG_VALUE DESCRIPTION ""
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79 | set_parameter_property VER6_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
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80 | add_parameter VER7_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
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81 | set_parameter_property VER7_RAM_REG_VALUE DISPLAY_NAME VER7_RAM_REG_VALUE
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82 | set_parameter_property VER7_RAM_REG_VALUE UNITS None
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83 | set_parameter_property VER7_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
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84 | set_parameter_property VER7_RAM_REG_VALUE DESCRIPTION ""
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85 | set_parameter_property VER7_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
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86 | add_parameter VER8_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
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87 | set_parameter_property VER8_RAM_REG_VALUE DISPLAY_NAME VER8_RAM_REG_VALUE
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88 | set_parameter_property VER8_RAM_REG_VALUE UNITS None
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89 | set_parameter_property VER8_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
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90 | set_parameter_property VER8_RAM_REG_VALUE DESCRIPTION ""
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91 | set_parameter_property VER8_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
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92 | # |
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93 | # +-----------------------------------
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94 |
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95 | # +-----------------------------------
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96 | # | connection point clock_reset
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97 | # |
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98 | add_interface clock_reset clock end
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99 | set_interface_property clock_reset ptfSchematicName ""
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100 |
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101 | add_interface_port clock_reset clk clk Input 1
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102 | add_interface_port clock_reset reset_n reset_n Input 1
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103 | # |
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104 | # +-----------------------------------
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105 |
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106 | # +-----------------------------------
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107 | # | connection point avalon_slave_0
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108 | # |
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109 | add_interface avalon_slave_0 avalon end
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110 | set_interface_property avalon_slave_0 addressAlignment DYNAMIC
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111 | set_interface_property avalon_slave_0 addressSpan 32
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112 | set_interface_property avalon_slave_0 bridgesToMaster ""
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113 | set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
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114 | set_interface_property avalon_slave_0 holdTime 0
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115 | set_interface_property avalon_slave_0 isMemoryDevice false
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116 | set_interface_property avalon_slave_0 isNonVolatileStorage false
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117 | set_interface_property avalon_slave_0 linewrapBursts false
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118 | set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
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119 | set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
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120 | set_interface_property avalon_slave_0 printableDevice false
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121 | set_interface_property avalon_slave_0 readLatency 0
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122 | set_interface_property avalon_slave_0 readWaitTime 1
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123 | set_interface_property avalon_slave_0 setupTime 0
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124 | set_interface_property avalon_slave_0 timingUnits Cycles
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125 | set_interface_property avalon_slave_0 writeWaitTime 0
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126 |
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127 | set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset
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128 |
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129 | add_interface_port avalon_slave_0 chipselect chipselect Input 1
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130 | add_interface_port avalon_slave_0 address address Input 3
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131 | add_interface_port avalon_slave_0 write write Input 1
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132 | add_interface_port avalon_slave_0 writedata writedata Input 32
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133 | add_interface_port avalon_slave_0 read read Input 1
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134 | add_interface_port avalon_slave_0 readdata readdata Output 32
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135 | add_interface_port avalon_slave_0 byteenable byteenable Input 4
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136 | add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
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137 | # |
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138 | # +-----------------------------------
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