source: rc_os_nios2/DE0_Nano_QSYS_DEMO/sysver/sysver.vhd@ 128

Last change on this file since 128 was 128, checked in by ertl-honda, 9 years ago

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File size: 4.5 KB
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1----------------------------------------------------------------------
2-- Copyright (c) 2009 Shinya Honda (honda@ertl.jp)
3--
4-- sysver.vhd
5--
6-- @(#) $Id: LoadLStoreCHw.vhd 1465 2009-08-27 05:39:47Z honda $
7----------------------------------------------------------------------
8library IEEE;
9use IEEE.std_logic_1164.all;
10
11entity sysver is
12 generic (
13 VER1_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
14 VER2_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
15 VER3_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
16 VER4_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
17 VER5_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
18 VER6_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
19 VER7_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
20 VER8_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000"
21 );
22 port(
23 clk : in std_logic;
24 reset_n : in std_logic;
25 chipselect : in std_logic;
26 address : in std_logic_vector(2 downto 0);
27 write : in std_logic;
28 writedata : in std_logic_vector(31 downto 0);
29 read : in std_logic;
30 readdata : out std_logic_vector(31 downto 0);
31 byteenable : in std_logic_vector(3 downto 0);
32 waitrequest : out std_logic
33 );
34end sysver;
35
36
37----------------------------------------------------------------------
38-- Architecture section
39----------------------------------------------------------------------
40architecture rtl of sysver is
41 signal ver1_select : std_logic;
42 signal ver2_select : std_logic;
43 signal ver3_select : std_logic;
44 signal ver4_select : std_logic;
45 signal ver5_select : std_logic;
46 signal ver6_select : std_logic;
47 signal ver7_select : std_logic;
48 signal ver8_select : std_logic;
49
50 signal ver5_reg : std_logic_vector(31 downto 0);
51 signal ver6_reg : std_logic_vector(31 downto 0);
52 signal ver7_reg : std_logic_vector(31 downto 0);
53 signal ver8_reg : std_logic_vector(31 downto 0);
54
55begin
56
57 -- –¢Žg—pM†
58 waitrequest <= '0';
59
60 -- ƒZƒŒƒNƒ^
61 process(address, chipselect)
62 begin
63 ver1_select <= '0';
64 ver2_select <= '0';
65 ver3_select <= '0';
66 ver4_select <= '0';
67 ver5_select <= '0';
68 ver6_select <= '0';
69 ver7_select <= '0';
70 ver8_select <= '0';
71
72 if chipselect = '1' then
73 case address is
74 when "000" => ver1_select <= '1'; -- 0x00
75 when "001" => ver2_select <= '1'; -- 0x04
76 when "010" => ver3_select <= '1'; -- 0x08
77 when "011" => ver4_select <= '1'; -- 0x0C
78 when "100" => ver5_select <= '1'; -- 0x10
79 when "101" => ver6_select <= '1'; -- 0x14
80 when "110" => ver7_select <= '1'; -- 0x18
81 when "111" => ver8_select <= '1'; -- 0x1C
82 when others => null;
83 end case;
84 end if;
85 end process;
86
87 -- ƒŠ[ƒhƒ}ƒ‹ƒ`ƒvƒŒƒNƒT
88 process(ver1_select,ver2_select,ver3_select,ver4_select,
89 ver5_select,ver6_select,ver7_select,ver8_select)
90 begin
91 readdata <= (others=>'0');
92 if ver1_select = '1' then
93 readdata <= VER1_ROM_REG_VALUE;
94 elsif ver2_select = '1' then
95 readdata <= VER2_ROM_REG_VALUE;
96 elsif ver3_select = '1' then
97 readdata <= VER3_ROM_REG_VALUE;
98 elsif ver4_select = '1' then
99 readdata <= VER4_ROM_REG_VALUE;
100 elsif ver5_select = '1' then
101 readdata <= ver5_reg;
102 elsif ver6_select = '1' then
103 readdata <= ver6_reg;
104 elsif ver7_select = '1' then
105 readdata <= ver7_reg;
106 elsif ver8_select = '1' then
107 readdata <= ver8_reg;
108 end if;
109 end process;
110
111 process(clk, reset_n)
112 begin
113 if ( reset_n = '0' ) then
114 ver5_reg <= VER5_RAM_REG_VALUE;
115 elsif( clk = '1' and clk'event ) then
116 if (write = '1' and ver5_select = '1') then
117 ver5_reg <= writedata;
118 end if;
119 end if;
120 end process;
121
122 process(clk, reset_n)
123 begin
124 if ( reset_n = '0' ) then
125 ver6_reg <= VER6_RAM_REG_VALUE;
126 elsif( clk = '1' and clk'event ) then
127 if (write = '1' and ver6_select = '1') then
128 ver6_reg <= writedata;
129 end if;
130 end if;
131 end process;
132
133 process(clk, reset_n)
134 begin
135 if ( reset_n = '0' ) then
136 ver7_reg <= VER7_RAM_REG_VALUE;
137 elsif( clk = '1' and clk'event ) then
138 if (write = '1' and ver7_select = '1') then
139 ver7_reg <= writedata;
140 end if;
141 end if;
142 end process;
143
144 process(clk, reset_n)
145 begin
146 if ( reset_n = '0' ) then
147 ver8_reg <= VER8_RAM_REG_VALUE;
148 elsif( clk = '1' and clk'event ) then
149 if (write = '1' and ver8_select = '1') then
150 ver8_reg <= writedata;
151 end if;
152 end if;
153 end process;
154
155
156end rtl;
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