[128] | 1 | ----------------------------------------------------------------------
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| 2 | -- Copyright (c) 2009 Shinya Honda (honda@ertl.jp)
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| 3 | --
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| 4 | -- sysver.vhd
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| 5 | --
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| 6 | -- @(#) $Id: LoadLStoreCHw.vhd 1465 2009-08-27 05:39:47Z honda $
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| 7 | ----------------------------------------------------------------------
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| 8 | library IEEE;
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| 9 | use IEEE.std_logic_1164.all;
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| 10 |
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| 11 | entity sysver is
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| 12 | generic (
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| 13 | VER1_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
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| 14 | VER2_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
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| 15 | VER3_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
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| 16 | VER4_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
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| 17 | VER5_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
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| 18 | VER6_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
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| 19 | VER7_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
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| 20 | VER8_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000"
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| 21 | );
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| 22 | port(
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| 23 | clk : in std_logic;
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| 24 | reset_n : in std_logic;
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| 25 | chipselect : in std_logic;
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| 26 | address : in std_logic_vector(2 downto 0);
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| 27 | write : in std_logic;
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| 28 | writedata : in std_logic_vector(31 downto 0);
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| 29 | read : in std_logic;
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| 30 | readdata : out std_logic_vector(31 downto 0);
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| 31 | byteenable : in std_logic_vector(3 downto 0);
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| 32 | waitrequest : out std_logic
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| 33 | );
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| 34 | end sysver;
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| 35 |
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| 36 |
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| 37 | ----------------------------------------------------------------------
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| 38 | -- Architecture section
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| 39 | ----------------------------------------------------------------------
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| 40 | architecture rtl of sysver is
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| 41 | signal ver1_select : std_logic;
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| 42 | signal ver2_select : std_logic;
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| 43 | signal ver3_select : std_logic;
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| 44 | signal ver4_select : std_logic;
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| 45 | signal ver5_select : std_logic;
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| 46 | signal ver6_select : std_logic;
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| 47 | signal ver7_select : std_logic;
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| 48 | signal ver8_select : std_logic;
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| 49 |
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| 50 | signal ver5_reg : std_logic_vector(31 downto 0);
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| 51 | signal ver6_reg : std_logic_vector(31 downto 0);
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| 52 | signal ver7_reg : std_logic_vector(31 downto 0);
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| 53 | signal ver8_reg : std_logic_vector(31 downto 0);
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| 54 |
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| 55 | begin
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| 56 |
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| 57 | -- ¢gpM
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| 58 | waitrequest <= '0';
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| 59 |
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| 60 | -- ZN^
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| 61 | process(address, chipselect)
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| 62 | begin
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| 63 | ver1_select <= '0';
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| 64 | ver2_select <= '0';
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| 65 | ver3_select <= '0';
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| 66 | ver4_select <= '0';
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| 67 | ver5_select <= '0';
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| 68 | ver6_select <= '0';
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| 69 | ver7_select <= '0';
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| 70 | ver8_select <= '0';
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| 71 |
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| 72 | if chipselect = '1' then
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| 73 | case address is
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| 74 | when "000" => ver1_select <= '1'; -- 0x00
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| 75 | when "001" => ver2_select <= '1'; -- 0x04
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| 76 | when "010" => ver3_select <= '1'; -- 0x08
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| 77 | when "011" => ver4_select <= '1'; -- 0x0C
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| 78 | when "100" => ver5_select <= '1'; -- 0x10
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| 79 | when "101" => ver6_select <= '1'; -- 0x14
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| 80 | when "110" => ver7_select <= '1'; -- 0x18
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| 81 | when "111" => ver8_select <= '1'; -- 0x1C
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| 82 | when others => null;
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| 83 | end case;
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| 84 | end if;
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| 85 | end process;
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| 86 |
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| 87 | -- [h}`vNT
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| 88 | process(ver1_select,ver2_select,ver3_select,ver4_select,
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| 89 | ver5_select,ver6_select,ver7_select,ver8_select)
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| 90 | begin
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| 91 | readdata <= (others=>'0');
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| 92 | if ver1_select = '1' then
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| 93 | readdata <= VER1_ROM_REG_VALUE;
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| 94 | elsif ver2_select = '1' then
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| 95 | readdata <= VER2_ROM_REG_VALUE;
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| 96 | elsif ver3_select = '1' then
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| 97 | readdata <= VER3_ROM_REG_VALUE;
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| 98 | elsif ver4_select = '1' then
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| 99 | readdata <= VER4_ROM_REG_VALUE;
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| 100 | elsif ver5_select = '1' then
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| 101 | readdata <= ver5_reg;
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| 102 | elsif ver6_select = '1' then
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| 103 | readdata <= ver6_reg;
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| 104 | elsif ver7_select = '1' then
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| 105 | readdata <= ver7_reg;
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| 106 | elsif ver8_select = '1' then
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| 107 | readdata <= ver8_reg;
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| 108 | end if;
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| 109 | end process;
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| 110 |
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| 111 | process(clk, reset_n)
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| 112 | begin
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| 113 | if ( reset_n = '0' ) then
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| 114 | ver5_reg <= VER5_RAM_REG_VALUE;
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| 115 | elsif( clk = '1' and clk'event ) then
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| 116 | if (write = '1' and ver5_select = '1') then
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| 117 | ver5_reg <= writedata;
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| 118 | end if;
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| 119 | end if;
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| 120 | end process;
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| 121 |
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| 122 | process(clk, reset_n)
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| 123 | begin
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| 124 | if ( reset_n = '0' ) then
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| 125 | ver6_reg <= VER6_RAM_REG_VALUE;
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| 126 | elsif( clk = '1' and clk'event ) then
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| 127 | if (write = '1' and ver6_select = '1') then
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| 128 | ver6_reg <= writedata;
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| 129 | end if;
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| 130 | end if;
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| 131 | end process;
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| 132 |
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| 133 | process(clk, reset_n)
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| 134 | begin
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| 135 | if ( reset_n = '0' ) then
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| 136 | ver7_reg <= VER7_RAM_REG_VALUE;
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| 137 | elsif( clk = '1' and clk'event ) then
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| 138 | if (write = '1' and ver7_select = '1') then
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| 139 | ver7_reg <= writedata;
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| 140 | end if;
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| 141 | end if;
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| 142 | end process;
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| 143 |
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| 144 | process(clk, reset_n)
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| 145 | begin
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| 146 | if ( reset_n = '0' ) then
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| 147 | ver8_reg <= VER8_RAM_REG_VALUE;
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| 148 | elsif( clk = '1' and clk'event ) then
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| 149 | if (write = '1' and ver8_select = '1') then
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| 150 | ver8_reg <= writedata;
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| 151 | end if;
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| 152 | end if;
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| 153 | end process;
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| 154 |
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| 155 |
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| 156 | end rtl;
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