source: rc_os_nios2/DE0_Nano_QSYS_DEMO/multi_pwm/multi_pwm_hw.tcl@ 128

# TCL File Generated by Component Editor 8.1
# Fri Aug 28 12:47:32 JST 2009
# DO NOT MODIFY


# +-----------------------------------
# | 
# | multi_pwm "multi_pwm" v1.0
# | null 2009.08.28.12:47:32
# | 
# | 
# | C:/home/nces/os/hw/queuing_lock/1s40_dual_fmp/multi_pwm/multi_pwm.vhd
# | 
# |    ./multi_pwm.vhd syn, sim
# | 
# +-----------------------------------


# +-----------------------------------
# | module multi_pwm
# | 
set_module_property NAME multi_pwm
set_module_property VERSION 1.0
set_module_property GROUP Other
set_module_property DISPLAY_NAME multi_pwm
set_module_property LIBRARIES {ieee.std_logic_1164.all std.standard.all}
set_module_property TOP_LEVEL_HDL_FILE multi_pwm.vhd
set_module_property TOP_LEVEL_HDL_MODULE multi_pwm
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE false
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file multi_pwm.vhd {SYNTHESIS SIMULATION}
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
add_parameter W INTEGER 15
set_parameter_property W DEFAULT_VALUE 15
set_parameter_property W DISPLAY_NAME WIDTH
set_parameter_property W UNITS None
set_parameter_property W ALLOWED_RANGES -2147483648:2147483647
set_parameter_property W DISPLAY_HINT ""
set_parameter_property W AFFECTS_GENERATION false
set_parameter_property W HDL_PARAMETER true
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clock_reset
# | 
add_interface clock_reset clock end
set_interface_property clock_reset ptfSchematicName ""

add_interface_port clock_reset clk clk Input 1
add_interface_port clock_reset reset_n reset_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0
# | 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 addressSpan 32
set_interface_property avalon_slave_0 bridgesToMaster ""
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0

set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset

add_interface_port avalon_slave_0 chipselect chipselect Input 1
add_interface_port avalon_slave_0 address address Input 3
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 writedata writedata Input 32
add_interface_port avalon_slave_0 read read Input 1
add_interface_port avalon_slave_0 readdata readdata Output 32
add_interface_port avalon_slave_0 byteenable byteenable Input 4
add_interface_port avalon_slave_0 waitrequest waitrequest Output 1

# +-----------------------------------
# | connection point conduit_end
# | 
add_interface conduit_end conduit end

set_interface_property conduit_end ENABLED true

add_interface_port conduit_end PWM1 export Output 1
add_interface_port conduit_end PWM3 export Output 1
add_interface_port conduit_end PWM2 export Output 1
add_interface_port conduit_end PWM4 export Output 1
add_interface_port conduit_end PWM5 export Output 1
add_interface_port conduit_end PWM6 export Output 1

# | 
# +-----------------------------------