----------------------------------------------------------------------
-- Copyright (c) 2009 Shinya Honda (honda@ertl.jp)
--
-- multi_pwm.vhd
--
-- @(#) $Id: LoadLStoreCHw.vhd 1465 2009-08-27 05:39:47Z honda $
----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity multi_pwm is
	generic (
		 W:integer := 16
	);  
	port(
		clk         : in  std_logic;
		reset_n     : in  std_logic;
		chipselect  : in  std_logic;
		address     : in  std_logic_vector(2 downto 0);
		write       : in  std_logic;
		writedata   : in  std_logic_vector(31 downto 0);
		read        : in  std_logic;
		readdata    : out std_logic_vector(31 downto 0);
		byteenable  : in  std_logic_vector(3 downto 0);
		waitrequest : out std_logic;
		pwm1        : out std_logic;
		pwm2        : out std_logic;
		pwm3        : out std_logic;
		pwm4        : out std_logic;
		pwm5        : out std_logic;
		pwm6        : out std_logic
	);
end multi_pwm;


----------------------------------------------------------------------
-- Architecture section
----------------------------------------------------------------------
architecture rtl of multi_pwm is
	signal ver1_select   : std_logic;
	signal ver2_select   : std_logic;
	signal ver3_select   : std_logic;
	signal ver4_select   : std_logic;
	signal ver5_select   : std_logic;
	signal ver6_select   : std_logic;
	signal ver7_select   : std_logic;
	signal ver8_select   : std_logic;

	signal control_reg : std_logic_vector(31 downto 0);
	signal pwm_counter, pwm_counter_max, pwm_value1, pwm_value2, pwm_value3,
		   pwm_value4, pwm_value5,pwm_value6 : std_logic_vector(W-1 downto 0);

	signal pwm_value1_v, pwm_value2_v, pwm_value3_v,
		   pwm_value4_v, pwm_value5_v, pwm_value6_v : std_logic_vector(W-1 downto 0);

begin

	-- 未使用信号
	waitrequest <= '0';

	-- セレクタ
	process(address, chipselect)
	begin
		ver1_select   <= '0';
		ver2_select   <= '0';
		ver3_select   <= '0';
		ver4_select   <= '0';
		ver5_select   <= '0';
		ver6_select   <= '0';
		ver7_select   <= '0';
		ver8_select   <= '0';
		if chipselect = '1' then
			case  address is 
				when "000" => ver1_select <= '1'; -- 0x00
				when "001" => ver2_select <= '1'; -- 0x04
				when "010" => ver3_select <= '1'; -- 0x08
				when "011" => ver4_select <= '1'; -- 0x0C
				when "100" => ver5_select <= '1'; -- 0x10
				when "101" => ver6_select <= '1'; -- 0x14
				when "110" => ver7_select <= '1'; -- 0x18
				when "111" => ver8_select <= '1'; -- 0x1C
				when others => null;
			end case;
		end if;
	end process;

	-- リードマルチプレクサ
	process(ver1_select,ver2_select,ver3_select,ver4_select,
			ver5_select,ver6_select,ver7_select,ver8_select)
	begin
		readdata <= (others=>'0');
		if ver1_select = '1' then
			readdata <= control_reg;
		elsif ver2_select = '1' then
			readdata(W-1 downto 0) <= pwm_counter_max;
		elsif ver3_select = '1' then
			readdata(W-1 downto 0) <= pwm_value1;
		elsif ver4_select = '1' then
			readdata(W-1 downto 0) <= pwm_value2;
		elsif ver5_select = '1' then
			readdata(W-1 downto 0) <= pwm_value3;
		elsif ver6_select = '1' then
			readdata(W-1 downto 0) <= pwm_value4;
		elsif ver7_select = '1' then
			readdata(W-1 downto 0) <= pwm_value5;
		elsif ver8_select = '1' then
			readdata(W-1 downto 0) <= pwm_value6;
		end if;
	end process;

	process(clk, reset_n)
	begin
		if ( reset_n = '0' ) then
			control_reg <= (others=>'0');
			pwm_counter_max <= (others=>'0');
			pwm_value1 <= (others=>'0');
			pwm_value2 <= (others=>'0');
			pwm_value3 <= (others=>'0');
			pwm_value4 <= (others=>'0');
			pwm_value5 <= (others=>'0');
			pwm_value6 <= (others=>'0');
		elsif( clk = '1' and clk'event ) then

			if (write = '1' and ver1_select = '1') then
				control_reg <= writedata;
			end if; 

			if (write = '1' and ver2_select = '1') then
				pwm_counter_max <= writedata(W-1 downto 0);
			end if; 

			if (write = '1' and ver3_select = '1') then
				pwm_value1 <= writedata(W-1 downto 0);
			end if; 

			if (write = '1' and ver4_select = '1') then
				pwm_value2 <= writedata(W-1 downto 0);
			end if; 

			if (write = '1' and ver5_select = '1') then
				pwm_value3 <= writedata(W-1 downto 0);
			end if; 

			if (write = '1' and ver6_select = '1') then
				pwm_value4 <= writedata(W-1 downto 0);
			end if; 

			if (write = '1' and ver7_select = '1') then
				pwm_value5 <= writedata(W-1 downto 0);
			end if; 

			if (write = '1' and ver8_select = '1') then
				pwm_value6 <= writedata(W-1 downto 0);
			end if; 

		end if;
	end process;

	-- generate pwm
	process(clk, reset_n)
	begin
		if ( reset_n = '0' ) then
			PWM1 <= '0';
			PWM2 <= '0';
			PWM3 <= '0';
			PWM4 <= '0';
			PWM5 <= '0';
			PWM6 <= '0';
			pwm_counter <= (others=>'0');
			pwm_value1_v <= (others=>'0');
			pwm_value2_v <= (others=>'0');
			pwm_value3_v <= (others=>'0');
			pwm_value4_v <= (others=>'0');
			pwm_value5_v <= (others=>'0');
			pwm_value6_v <= (others=>'0');
		elsif( clk = '1' and clk'event ) then

			if (pwm_counter > pwm_counter_max) then
				pwm_counter <= (others=>'0');
				pwm_value1_v <= pwm_value1;
				pwm_value2_v <= pwm_value2;
				pwm_value3_v <= pwm_value3;
				pwm_value4_v <= pwm_value4;
				pwm_value5_v <= pwm_value5;
				pwm_value6_v <= pwm_value6;
			else
				pwm_counter <= pwm_counter + 1;
			end if;

			if ((pwm_counter<pwm_value1_v)and (pwm_value1_v>0)) then
				PWM1<='1';
			else PWM1<='0'; end if; 
			  
			 if ((pwm_counter<pwm_value2_v)and (pwm_value2_v>0)) then
				PWM2<='1';
			else PWM2<='0'; end if; 

			if ((pwm_counter<pwm_value3_v)and (pwm_value3_v>0)) then
				PWM3<='1';
			else PWM3<='0'; end if; 
			  
			if ((pwm_counter<pwm_value4_v)and (pwm_value4_v>0)) then
				PWM4<='1';
			else PWM4<='0'; end if; 
			  
			if ((pwm_counter<pwm_value5_v)and (pwm_value5_v>0)) then
				PWM5<='1';
			else PWM5<='0'; end if; 
			  
			if ((pwm_counter<pwm_value6_v)and (pwm_value6_v>0)) then
				PWM6<='1';
			else PWM6<='0'; end if; 
		end if;
	end process;


end rtl;