source: rc_os_nios2/DE0_Nano_QSYS_DEMO/multi_pwm/multi_pwm.vhd@ 128

Last change on this file since 128 was 128, checked in by ertl-honda, 9 years ago

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File size: 6.1 KB
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1----------------------------------------------------------------------
2-- Copyright (c) 2009 Shinya Honda (honda@ertl.jp)
3--
4-- multi_pwm.vhd
5--
6-- @(#) $Id: LoadLStoreCHw.vhd 1465 2009-08-27 05:39:47Z honda $
7----------------------------------------------------------------------
8library IEEE;
9use IEEE.std_logic_1164.all;
10use IEEE.std_logic_arith.all;
11use IEEE.std_logic_unsigned.all;
12
13entity multi_pwm is
14 generic (
15 W:integer := 16
16 );
17 port(
18 clk : in std_logic;
19 reset_n : in std_logic;
20 chipselect : in std_logic;
21 address : in std_logic_vector(2 downto 0);
22 write : in std_logic;
23 writedata : in std_logic_vector(31 downto 0);
24 read : in std_logic;
25 readdata : out std_logic_vector(31 downto 0);
26 byteenable : in std_logic_vector(3 downto 0);
27 waitrequest : out std_logic;
28 pwm1 : out std_logic;
29 pwm2 : out std_logic;
30 pwm3 : out std_logic;
31 pwm4 : out std_logic;
32 pwm5 : out std_logic;
33 pwm6 : out std_logic
34 );
35end multi_pwm;
36
37
38----------------------------------------------------------------------
39-- Architecture section
40----------------------------------------------------------------------
41architecture rtl of multi_pwm is
42 signal ver1_select : std_logic;
43 signal ver2_select : std_logic;
44 signal ver3_select : std_logic;
45 signal ver4_select : std_logic;
46 signal ver5_select : std_logic;
47 signal ver6_select : std_logic;
48 signal ver7_select : std_logic;
49 signal ver8_select : std_logic;
50
51 signal control_reg : std_logic_vector(31 downto 0);
52 signal pwm_counter, pwm_counter_max, pwm_value1, pwm_value2, pwm_value3,
53 pwm_value4, pwm_value5,pwm_value6 : std_logic_vector(W-1 downto 0);
54
55 signal pwm_value1_v, pwm_value2_v, pwm_value3_v,
56 pwm_value4_v, pwm_value5_v, pwm_value6_v : std_logic_vector(W-1 downto 0);
57
58begin
59
60 -- –¢Žg—pM†
61 waitrequest <= '0';
62
63 -- ƒZƒŒƒNƒ^
64 process(address, chipselect)
65 begin
66 ver1_select <= '0';
67 ver2_select <= '0';
68 ver3_select <= '0';
69 ver4_select <= '0';
70 ver5_select <= '0';
71 ver6_select <= '0';
72 ver7_select <= '0';
73 ver8_select <= '0';
74 if chipselect = '1' then
75 case address is
76 when "000" => ver1_select <= '1'; -- 0x00
77 when "001" => ver2_select <= '1'; -- 0x04
78 when "010" => ver3_select <= '1'; -- 0x08
79 when "011" => ver4_select <= '1'; -- 0x0C
80 when "100" => ver5_select <= '1'; -- 0x10
81 when "101" => ver6_select <= '1'; -- 0x14
82 when "110" => ver7_select <= '1'; -- 0x18
83 when "111" => ver8_select <= '1'; -- 0x1C
84 when others => null;
85 end case;
86 end if;
87 end process;
88
89 -- ƒŠ[ƒhƒ}ƒ‹ƒ`ƒvƒŒƒNƒT
90 process(ver1_select,ver2_select,ver3_select,ver4_select,
91 ver5_select,ver6_select,ver7_select,ver8_select)
92 begin
93 readdata <= (others=>'0');
94 if ver1_select = '1' then
95 readdata <= control_reg;
96 elsif ver2_select = '1' then
97 readdata(W-1 downto 0) <= pwm_counter_max;
98 elsif ver3_select = '1' then
99 readdata(W-1 downto 0) <= pwm_value1;
100 elsif ver4_select = '1' then
101 readdata(W-1 downto 0) <= pwm_value2;
102 elsif ver5_select = '1' then
103 readdata(W-1 downto 0) <= pwm_value3;
104 elsif ver6_select = '1' then
105 readdata(W-1 downto 0) <= pwm_value4;
106 elsif ver7_select = '1' then
107 readdata(W-1 downto 0) <= pwm_value5;
108 elsif ver8_select = '1' then
109 readdata(W-1 downto 0) <= pwm_value6;
110 end if;
111 end process;
112
113 process(clk, reset_n)
114 begin
115 if ( reset_n = '0' ) then
116 control_reg <= (others=>'0');
117 pwm_counter_max <= (others=>'0');
118 pwm_value1 <= (others=>'0');
119 pwm_value2 <= (others=>'0');
120 pwm_value3 <= (others=>'0');
121 pwm_value4 <= (others=>'0');
122 pwm_value5 <= (others=>'0');
123 pwm_value6 <= (others=>'0');
124 elsif( clk = '1' and clk'event ) then
125
126 if (write = '1' and ver1_select = '1') then
127 control_reg <= writedata;
128 end if;
129
130 if (write = '1' and ver2_select = '1') then
131 pwm_counter_max <= writedata(W-1 downto 0);
132 end if;
133
134 if (write = '1' and ver3_select = '1') then
135 pwm_value1 <= writedata(W-1 downto 0);
136 end if;
137
138 if (write = '1' and ver4_select = '1') then
139 pwm_value2 <= writedata(W-1 downto 0);
140 end if;
141
142 if (write = '1' and ver5_select = '1') then
143 pwm_value3 <= writedata(W-1 downto 0);
144 end if;
145
146 if (write = '1' and ver6_select = '1') then
147 pwm_value4 <= writedata(W-1 downto 0);
148 end if;
149
150 if (write = '1' and ver7_select = '1') then
151 pwm_value5 <= writedata(W-1 downto 0);
152 end if;
153
154 if (write = '1' and ver8_select = '1') then
155 pwm_value6 <= writedata(W-1 downto 0);
156 end if;
157
158 end if;
159 end process;
160
161 -- generate pwm
162 process(clk, reset_n)
163 begin
164 if ( reset_n = '0' ) then
165 PWM1 <= '0';
166 PWM2 <= '0';
167 PWM3 <= '0';
168 PWM4 <= '0';
169 PWM5 <= '0';
170 PWM6 <= '0';
171 pwm_counter <= (others=>'0');
172 pwm_value1_v <= (others=>'0');
173 pwm_value2_v <= (others=>'0');
174 pwm_value3_v <= (others=>'0');
175 pwm_value4_v <= (others=>'0');
176 pwm_value5_v <= (others=>'0');
177 pwm_value6_v <= (others=>'0');
178 elsif( clk = '1' and clk'event ) then
179
180 if (pwm_counter > pwm_counter_max) then
181 pwm_counter <= (others=>'0');
182 pwm_value1_v <= pwm_value1;
183 pwm_value2_v <= pwm_value2;
184 pwm_value3_v <= pwm_value3;
185 pwm_value4_v <= pwm_value4;
186 pwm_value5_v <= pwm_value5;
187 pwm_value6_v <= pwm_value6;
188 else
189 pwm_counter <= pwm_counter + 1;
190 end if;
191
192 if ((pwm_counter<pwm_value1_v)and (pwm_value1_v>0)) then
193 PWM1<='1';
194 else PWM1<='0'; end if;
195
196 if ((pwm_counter<pwm_value2_v)and (pwm_value2_v>0)) then
197 PWM2<='1';
198 else PWM2<='0'; end if;
199
200 if ((pwm_counter<pwm_value3_v)and (pwm_value3_v>0)) then
201 PWM3<='1';
202 else PWM3<='0'; end if;
203
204 if ((pwm_counter<pwm_value4_v)and (pwm_value4_v>0)) then
205 PWM4<='1';
206 else PWM4<='0'; end if;
207
208 if ((pwm_counter<pwm_value5_v)and (pwm_value5_v>0)) then
209 PWM5<='1';
210 else PWM5<='0'; end if;
211
212 if ((pwm_counter<pwm_value6_v)and (pwm_value6_v>0)) then
213 PWM6<='1';
214 else PWM6<='0'; end if;
215 end if;
216 end process;
217
218
219end rtl;
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