[128] | 1 | ----------------------------------------------------------------------
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| 2 | -- Copyright (c) 2009 Shinya Honda (honda@ertl.jp)
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| 3 | --
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| 4 | -- multi_pwm.vhd
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| 5 | --
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| 6 | -- @(#) $Id: LoadLStoreCHw.vhd 1465 2009-08-27 05:39:47Z honda $
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| 7 | ----------------------------------------------------------------------
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| 8 | library IEEE;
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| 9 | use IEEE.std_logic_1164.all;
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| 10 | use IEEE.std_logic_arith.all;
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| 11 | use IEEE.std_logic_unsigned.all;
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| 12 |
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| 13 | entity multi_pwm is
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| 14 | generic (
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| 15 | W:integer := 16
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| 16 | );
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| 17 | port(
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| 18 | clk : in std_logic;
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| 19 | reset_n : in std_logic;
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| 20 | chipselect : in std_logic;
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| 21 | address : in std_logic_vector(2 downto 0);
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| 22 | write : in std_logic;
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| 23 | writedata : in std_logic_vector(31 downto 0);
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| 24 | read : in std_logic;
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| 25 | readdata : out std_logic_vector(31 downto 0);
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| 26 | byteenable : in std_logic_vector(3 downto 0);
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| 27 | waitrequest : out std_logic;
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| 28 | pwm1 : out std_logic;
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| 29 | pwm2 : out std_logic;
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| 30 | pwm3 : out std_logic;
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| 31 | pwm4 : out std_logic;
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| 32 | pwm5 : out std_logic;
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| 33 | pwm6 : out std_logic
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| 34 | );
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| 35 | end multi_pwm;
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| 36 |
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| 37 |
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| 38 | ----------------------------------------------------------------------
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| 39 | -- Architecture section
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| 40 | ----------------------------------------------------------------------
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| 41 | architecture rtl of multi_pwm is
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| 42 | signal ver1_select : std_logic;
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| 43 | signal ver2_select : std_logic;
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| 44 | signal ver3_select : std_logic;
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| 45 | signal ver4_select : std_logic;
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| 46 | signal ver5_select : std_logic;
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| 47 | signal ver6_select : std_logic;
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| 48 | signal ver7_select : std_logic;
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| 49 | signal ver8_select : std_logic;
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| 50 |
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| 51 | signal control_reg : std_logic_vector(31 downto 0);
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| 52 | signal pwm_counter, pwm_counter_max, pwm_value1, pwm_value2, pwm_value3,
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| 53 | pwm_value4, pwm_value5,pwm_value6 : std_logic_vector(W-1 downto 0);
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| 54 |
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| 55 | signal pwm_value1_v, pwm_value2_v, pwm_value3_v,
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| 56 | pwm_value4_v, pwm_value5_v, pwm_value6_v : std_logic_vector(W-1 downto 0);
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| 57 |
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| 58 | begin
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| 59 |
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| 60 | -- ¢gpM
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| 61 | waitrequest <= '0';
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| 62 |
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| 63 | -- ZN^
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| 64 | process(address, chipselect)
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| 65 | begin
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| 66 | ver1_select <= '0';
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| 67 | ver2_select <= '0';
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| 68 | ver3_select <= '0';
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| 69 | ver4_select <= '0';
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| 70 | ver5_select <= '0';
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| 71 | ver6_select <= '0';
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| 72 | ver7_select <= '0';
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| 73 | ver8_select <= '0';
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| 74 | if chipselect = '1' then
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| 75 | case address is
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| 76 | when "000" => ver1_select <= '1'; -- 0x00
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| 77 | when "001" => ver2_select <= '1'; -- 0x04
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| 78 | when "010" => ver3_select <= '1'; -- 0x08
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| 79 | when "011" => ver4_select <= '1'; -- 0x0C
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| 80 | when "100" => ver5_select <= '1'; -- 0x10
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| 81 | when "101" => ver6_select <= '1'; -- 0x14
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| 82 | when "110" => ver7_select <= '1'; -- 0x18
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| 83 | when "111" => ver8_select <= '1'; -- 0x1C
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| 84 | when others => null;
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| 85 | end case;
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| 86 | end if;
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| 87 | end process;
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| 88 |
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| 89 | -- [h}`vNT
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| 90 | process(ver1_select,ver2_select,ver3_select,ver4_select,
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| 91 | ver5_select,ver6_select,ver7_select,ver8_select)
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| 92 | begin
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| 93 | readdata <= (others=>'0');
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| 94 | if ver1_select = '1' then
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| 95 | readdata <= control_reg;
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| 96 | elsif ver2_select = '1' then
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| 97 | readdata(W-1 downto 0) <= pwm_counter_max;
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| 98 | elsif ver3_select = '1' then
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| 99 | readdata(W-1 downto 0) <= pwm_value1;
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| 100 | elsif ver4_select = '1' then
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| 101 | readdata(W-1 downto 0) <= pwm_value2;
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| 102 | elsif ver5_select = '1' then
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| 103 | readdata(W-1 downto 0) <= pwm_value3;
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| 104 | elsif ver6_select = '1' then
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| 105 | readdata(W-1 downto 0) <= pwm_value4;
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| 106 | elsif ver7_select = '1' then
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| 107 | readdata(W-1 downto 0) <= pwm_value5;
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| 108 | elsif ver8_select = '1' then
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| 109 | readdata(W-1 downto 0) <= pwm_value6;
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| 110 | end if;
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| 111 | end process;
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| 112 |
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| 113 | process(clk, reset_n)
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| 114 | begin
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| 115 | if ( reset_n = '0' ) then
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| 116 | control_reg <= (others=>'0');
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| 117 | pwm_counter_max <= (others=>'0');
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| 118 | pwm_value1 <= (others=>'0');
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| 119 | pwm_value2 <= (others=>'0');
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| 120 | pwm_value3 <= (others=>'0');
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| 121 | pwm_value4 <= (others=>'0');
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| 122 | pwm_value5 <= (others=>'0');
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| 123 | pwm_value6 <= (others=>'0');
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| 124 | elsif( clk = '1' and clk'event ) then
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| 125 |
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| 126 | if (write = '1' and ver1_select = '1') then
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| 127 | control_reg <= writedata;
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| 128 | end if;
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| 129 |
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| 130 | if (write = '1' and ver2_select = '1') then
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| 131 | pwm_counter_max <= writedata(W-1 downto 0);
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| 132 | end if;
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| 133 |
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| 134 | if (write = '1' and ver3_select = '1') then
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| 135 | pwm_value1 <= writedata(W-1 downto 0);
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| 136 | end if;
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| 137 |
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| 138 | if (write = '1' and ver4_select = '1') then
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| 139 | pwm_value2 <= writedata(W-1 downto 0);
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| 140 | end if;
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| 141 |
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| 142 | if (write = '1' and ver5_select = '1') then
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| 143 | pwm_value3 <= writedata(W-1 downto 0);
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| 144 | end if;
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| 145 |
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| 146 | if (write = '1' and ver6_select = '1') then
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| 147 | pwm_value4 <= writedata(W-1 downto 0);
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| 148 | end if;
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| 149 |
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| 150 | if (write = '1' and ver7_select = '1') then
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| 151 | pwm_value5 <= writedata(W-1 downto 0);
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| 152 | end if;
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| 153 |
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| 154 | if (write = '1' and ver8_select = '1') then
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| 155 | pwm_value6 <= writedata(W-1 downto 0);
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| 156 | end if;
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| 157 |
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| 158 | end if;
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| 159 | end process;
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| 160 |
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| 161 | -- generate pwm
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| 162 | process(clk, reset_n)
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| 163 | begin
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| 164 | if ( reset_n = '0' ) then
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| 165 | PWM1 <= '0';
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| 166 | PWM2 <= '0';
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| 167 | PWM3 <= '0';
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| 168 | PWM4 <= '0';
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| 169 | PWM5 <= '0';
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| 170 | PWM6 <= '0';
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| 171 | pwm_counter <= (others=>'0');
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| 172 | pwm_value1_v <= (others=>'0');
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| 173 | pwm_value2_v <= (others=>'0');
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| 174 | pwm_value3_v <= (others=>'0');
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| 175 | pwm_value4_v <= (others=>'0');
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| 176 | pwm_value5_v <= (others=>'0');
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| 177 | pwm_value6_v <= (others=>'0');
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| 178 | elsif( clk = '1' and clk'event ) then
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| 179 |
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| 180 | if (pwm_counter > pwm_counter_max) then
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| 181 | pwm_counter <= (others=>'0');
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| 182 | pwm_value1_v <= pwm_value1;
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| 183 | pwm_value2_v <= pwm_value2;
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| 184 | pwm_value3_v <= pwm_value3;
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| 185 | pwm_value4_v <= pwm_value4;
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| 186 | pwm_value5_v <= pwm_value5;
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| 187 | pwm_value6_v <= pwm_value6;
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| 188 | else
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| 189 | pwm_counter <= pwm_counter + 1;
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| 190 | end if;
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| 191 |
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| 192 | if ((pwm_counter<pwm_value1_v)and (pwm_value1_v>0)) then
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| 193 | PWM1<='1';
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| 194 | else PWM1<='0'; end if;
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| 195 |
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| 196 | if ((pwm_counter<pwm_value2_v)and (pwm_value2_v>0)) then
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| 197 | PWM2<='1';
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| 198 | else PWM2<='0'; end if;
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| 199 |
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| 200 | if ((pwm_counter<pwm_value3_v)and (pwm_value3_v>0)) then
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| 201 | PWM3<='1';
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| 202 | else PWM3<='0'; end if;
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| 203 |
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| 204 | if ((pwm_counter<pwm_value4_v)and (pwm_value4_v>0)) then
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| 205 | PWM4<='1';
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| 206 | else PWM4<='0'; end if;
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| 207 |
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| 208 | if ((pwm_counter<pwm_value5_v)and (pwm_value5_v>0)) then
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| 209 | PWM5<='1';
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| 210 | else PWM5<='0'; end if;
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| 211 |
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| 212 | if ((pwm_counter<pwm_value6_v)and (pwm_value6_v>0)) then
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| 213 | PWM6<='1';
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| 214 | else PWM6<='0'; end if;
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| 215 | end if;
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| 216 | end process;
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| 217 |
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| 218 |
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| 219 | end rtl;
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