| 1 | //////////////////////////////////////////////////////////////////////
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| 2 | //// ////
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| 3 | //// can_top.v ////
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| 4 | //// ////
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| 5 | //// ////
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| 6 | //// This file is part of the CAN Protocol Controller ////
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| 7 | //// http://www.opencores.org/projects/can/ ////
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| 8 | //// ////
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| 9 | //// ////
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| 10 | //// Author(s): ////
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| 11 | //// Igor Mohor ////
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| 12 | //// igorm@opencores.org ////
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| 13 | //// ////
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| 14 | //// ////
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| 15 | //// All additional information is available in the README.txt ////
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| 16 | //// file. ////
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| 17 | //// ////
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| 18 | //////////////////////////////////////////////////////////////////////
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| 19 | //// ////
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| 20 | //// Copyright (C) 2002, 2003, 2004 Authors ////
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| 21 | //// ////
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| 22 | //// This source file may be used and distributed without ////
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| 23 | //// restriction provided that this copyright statement is not ////
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| 24 | //// removed from the file and that any derivative work contains ////
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| 25 | //// the original copyright notice and the associated disclaimer. ////
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| 26 | //// ////
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| 27 | //// This source file is free software; you can redistribute it ////
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| 28 | //// and/or modify it under the terms of the GNU Lesser General ////
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| 29 | //// Public License as published by the Free Software Foundation; ////
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| 30 | //// either version 2.1 of the License, or (at your option) any ////
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| 31 | //// later version. ////
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| 32 | //// ////
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| 33 | //// This source is distributed in the hope that it will be ////
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| 34 | //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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| 35 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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| 36 | //// PURPOSE. See the GNU Lesser General Public License for more ////
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| 37 | //// details. ////
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| 38 | //// ////
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| 39 | //// You should have received a copy of the GNU Lesser General ////
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| 40 | //// Public License along with this source; if not, download it ////
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| 41 | //// from http://www.opencores.org/lgpl.shtml ////
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| 42 | //// ////
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| 43 | //// The CAN protocol is developed by Robert Bosch GmbH and ////
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| 44 | //// protected by patents. Anybody who wants to implement this ////
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| 45 | //// CAN IP core on silicon has to obtain a CAN protocol license ////
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| 46 | //// from Bosch. ////
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| 47 | //// ////
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| 48 | //////////////////////////////////////////////////////////////////////
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| 49 | //
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| 50 | // CVS Revision History
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| 51 | //
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| 52 | // $Log: can_top.v,v $
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| 53 | // Revision 1.48 2004/10/25 11:44:47 igorm
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| 54 | // Interrupt is always cleared for one clock after the irq register is read.
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| 55 | // This fixes problems when CPU is using IRQs that are edge triggered.
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| 56 | //
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| 57 | // Revision 1.47 2004/02/08 14:53:54 mohor
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| 58 | // Header changed. Address latched to posedge. bus_off_on signal added.
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| 59 | //
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| 60 | // Revision 1.46 2003/10/17 05:55:20 markom
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| 61 | // mbist signals updated according to newest convention
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| 62 | //
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| 63 | // Revision 1.45 2003/09/30 00:55:13 mohor
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| 64 | // Error counters fixed to be compatible with Bosch VHDL reference model.
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| 65 | // Small synchronization changes.
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| 66 | //
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| 67 | // Revision 1.44 2003/09/25 18:55:49 mohor
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| 68 | // Synchronization changed, error counters fixed.
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| 69 | //
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| 70 | // Revision 1.43 2003/08/20 09:57:39 mohor
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| 71 | // Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
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| 72 | // to be joined together on higher level.
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| 73 | //
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| 74 | // Revision 1.42 2003/07/16 15:11:28 mohor
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| 75 | // Fixed according to the linter.
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| 76 | //
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| 77 | // Revision 1.41 2003/07/10 15:32:27 mohor
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| 78 | // Unused signal removed.
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| 79 | //
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| 80 | // Revision 1.40 2003/07/10 01:59:04 tadejm
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| 81 | // Synchronization fixed. In some strange cases it didn't work according to
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| 82 | // the VHDL reference model.
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| 83 | //
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| 84 | // Revision 1.39 2003/07/07 11:21:37 mohor
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| 85 | // Little fixes (to fix warnings).
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| 86 | //
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| 87 | // Revision 1.38 2003/07/03 09:32:20 mohor
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| 88 | // Synchronization changed.
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| 89 | //
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| 90 | // Revision 1.37 2003/06/27 20:56:15 simons
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| 91 | // Virtual silicon ram instances added.
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| 92 | //
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| 93 | // Revision 1.36 2003/06/17 14:30:30 mohor
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| 94 | // "chip select" signal cs_can_i is used only when not using WISHBONE
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| 95 | // interface.
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| 96 | //
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| 97 | // Revision 1.35 2003/06/16 13:57:58 mohor
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| 98 | // tx_point generated one clk earlier. rx_i registered. Data corrected when
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| 99 | // using extended mode.
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| 100 | //
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| 101 | // Revision 1.34 2003/06/13 15:02:24 mohor
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| 102 | // Synchronization is also needed when transmitting a message.
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| 103 | //
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| 104 | // Revision 1.33 2003/06/11 14:21:35 mohor
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| 105 | // When switching to tx, sync stage is overjumped.
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| 106 | //
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| 107 | // Revision 1.32 2003/06/09 11:32:36 mohor
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| 108 | // Ports added for the CAN_BIST.
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| 109 | //
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| 110 | // Revision 1.31 2003/03/26 11:19:46 mohor
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| 111 | // CAN interrupt is active low.
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| 112 | //
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| 113 | // Revision 1.30 2003/03/20 17:01:17 mohor
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| 114 | // unix.
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| 115 | //
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| 116 | // Revision 1.28 2003/03/14 19:36:48 mohor
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| 117 | // can_cs signal used for generation of the cs.
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| 118 | //
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| 119 | // Revision 1.27 2003/03/12 05:56:33 mohor
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| 120 | // Bidirectional port_0_i changed to port_0_io.
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| 121 | // input cs_can changed to cs_can_i.
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| 122 | //
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| 123 | // Revision 1.26 2003/03/12 04:39:40 mohor
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| 124 | // rd_i and wr_i are active high signals. If 8051 is connected, these two signals
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| 125 | // need to be negated one level higher.
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| 126 | //
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| 127 | // Revision 1.25 2003/03/12 04:17:36 mohor
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| 128 | // 8051 interface added (besides WISHBONE interface). Selection is made in
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| 129 | // can_defines.v file.
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| 130 | //
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| 131 | // Revision 1.24 2003/03/10 17:24:40 mohor
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| 132 | // wire declaration added.
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| 133 | //
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| 134 | // Revision 1.23 2003/03/05 15:33:13 mohor
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| 135 | // tx_o is now tristated signal. tx_oen and tx_o combined together.
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| 136 | //
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| 137 | // Revision 1.22 2003/03/05 15:01:56 mohor
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| 138 | // Top level signal names changed.
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| 139 | //
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| 140 | // Revision 1.21 2003/03/01 22:53:33 mohor
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| 141 | // Actel APA ram supported.
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| 142 | //
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| 143 | // Revision 1.20 2003/02/19 15:09:02 mohor
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| 144 | // Incomplete sensitivity list fixed.
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| 145 | //
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| 146 | // Revision 1.19 2003/02/19 15:04:14 mohor
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| 147 | // Typo fixed.
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| 148 | //
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| 149 | // Revision 1.18 2003/02/19 14:44:03 mohor
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| 150 | // CAN core finished. Host interface added. Registers finished.
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| 151 | // Synchronization to the wishbone finished.
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| 152 | //
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| 153 | // Revision 1.17 2003/02/18 00:10:15 mohor
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| 154 | // Most of the registers added. Registers "arbitration lost capture", "error code
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| 155 | // capture" + few more still need to be added.
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| 156 | //
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| 157 | // Revision 1.16 2003/02/14 20:17:01 mohor
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| 158 | // Several registers added. Not finished, yet.
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| 159 | //
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| 160 | // Revision 1.15 2003/02/12 14:25:30 mohor
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| 161 | // abort_tx added.
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| 162 | //
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| 163 | // Revision 1.14 2003/02/11 00:56:06 mohor
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| 164 | // Wishbone interface added.
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| 165 | //
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| 166 | // Revision 1.13 2003/02/09 18:40:29 mohor
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| 167 | // Overload fixed. Hard synchronization also enabled at the last bit of
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| 168 | // interframe.
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| 169 | //
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| 170 | // Revision 1.12 2003/02/09 02:24:33 mohor
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| 171 | // Bosch license warning added. Error counters finished. Overload frames
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| 172 | // still need to be fixed.
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| 173 | //
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| 174 | // Revision 1.11 2003/02/04 14:34:52 mohor
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| 175 | // *** empty log message ***
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| 176 | //
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| 177 | // Revision 1.10 2003/01/31 01:13:38 mohor
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| 178 | // backup.
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| 179 | //
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| 180 | // Revision 1.9 2003/01/15 13:16:48 mohor
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| 181 | // When a frame with "remote request" is received, no data is stored to
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| 182 | // fifo, just the frame information (identifier, ...). Data length that
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| 183 | // is stored is the received data length and not the actual data length
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| 184 | // that is stored to fifo.
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| 185 | //
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| 186 | // Revision 1.8 2003/01/14 17:25:09 mohor
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| 187 | // Addresses corrected to decimal values (previously hex).
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| 188 | //
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| 189 | // Revision 1.7 2003/01/10 17:51:34 mohor
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| 190 | // Temporary version (backup).
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| 191 | //
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| 192 | // Revision 1.6 2003/01/09 21:54:45 mohor
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| 193 | // rx fifo added. Not 100 % verified, yet.
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| 194 | //
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| 195 | // Revision 1.5 2003/01/08 02:10:56 mohor
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| 196 | // Acceptance filter added.
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| 197 | //
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| 198 | // Revision 1.4 2002/12/28 04:13:23 mohor
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| 199 | // Backup version.
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| 200 | //
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| 201 | // Revision 1.3 2002/12/27 00:12:52 mohor
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| 202 | // Header changed, testbench improved to send a frame (crc still missing).
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| 203 | //
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| 204 | // Revision 1.2 2002/12/26 16:00:34 mohor
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| 205 | // Testbench define file added. Clock divider register added.
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| 206 | //
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| 207 | // Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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| 208 | // Initial
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| 209 | //
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| 210 | //
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| 211 | //
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| 212 |
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| 213 | // synopsys translate_off
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| 214 | `include "timescale.v"
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| 215 | // synopsys translate_on
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| 216 | `include "can_defines.v"
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| 217 |
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| 218 | module can_top
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| 219 | (
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| 220 | `ifdef CAN_WISHBONE_IF
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| 221 | wb_clk_i,
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| 222 | wb_rst_i,
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| 223 | wb_dat_i,
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| 224 | wb_dat_o,
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| 225 | wb_cyc_i,
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| 226 | wb_stb_i,
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| 227 | wb_we_i,
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| 228 | wb_adr_i,
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| 229 | wb_ack_o,
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| 230 | `else
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| 231 | `ifdef CAN_AVALON_IF
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| 232 | av_rst_i,
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| 233 | av_cs_i,
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| 234 | av_wr_i,
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| 235 | av_adr_i,
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| 236 | av_dat_i,
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| 237 | av_dat_o,
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| 238 | `else
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| 239 | rst_i,
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| 240 | ale_i,
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| 241 | rd_i,
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| 242 | wr_i,
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| 243 | port_0_io,
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| 244 | cs_can_i,
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| 245 | `endif
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| 246 | `endif
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| 247 | clk_i,
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| 248 | rx_i,
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| 249 | tx_o,
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| 250 | bus_off_on,
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| 251 | irq_on,
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| 252 | clkout_o
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| 253 |
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| 254 | // Bist
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| 255 | `ifdef CAN_BIST
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| 256 | ,
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| 257 | // debug chain signals
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| 258 | mbist_si_i, // bist scan serial in
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| 259 | mbist_so_o, // bist scan serial out
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| 260 | mbist_ctrl_i // bist chain shift control
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| 261 | `endif
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| 262 | );
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| 263 |
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| 264 | parameter Tp = 1;
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| 265 | parameter TXMBOX_DEPTH = 1; /* 2(Min=4) - 4(Max=16) */
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| 266 | parameter RXMBOX_DEPTH = 4; /* 2(Min=4) - 5(Max=32) */
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| 267 |
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| 268 |
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| 269 | `ifdef CAN_WISHBONE_IF
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| 270 | input wb_clk_i;
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| 271 | input wb_rst_i;
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| 272 | input [31:0] wb_dat_i;
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| 273 | output [31:0] wb_dat_o;
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| 274 | input wb_cyc_i;
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| 275 | input wb_stb_i;
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| 276 | input wb_we_i;
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| 277 | input [7:0] wb_adr_i;
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| 278 | output wb_ack_o;
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| 279 |
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| 280 | reg wb_ack_o;
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| 281 | reg cs_sync1;
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| 282 | reg cs_sync2;
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| 283 | reg cs_sync3;
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| 284 |
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| 285 | reg cs_ack1;
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| 286 | reg cs_ack2;
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| 287 | reg cs_ack3;
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| 288 | reg cs_sync_rst1;
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| 289 | reg cs_sync_rst2;
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| 290 | wire cs_can_i;
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| 291 | `else
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| 292 | `ifdef CAN_AVALON_IF
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| 293 | input av_rst_i;
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| 294 | input av_cs_i;
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| 295 | input av_wr_i;
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| 296 | input [31:0] av_dat_i;
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| 297 | output [31:0] av_dat_o;
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| 298 | input [7:0] av_adr_i;
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| 299 |
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| 300 | wire av_cs_i;
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| 301 | `else
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| 302 | input rst_i;
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| 303 | input ale_i;
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| 304 | input rd_i;
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| 305 | input wr_i;
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| 306 | inout [31:0] port_0_io;
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| 307 | input cs_can_i;
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| 308 |
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| 309 | reg [9:0] addr_latched;
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| 310 | reg wr_i_q;
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| 311 | reg rd_i_q;
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| 312 | `endif
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| 313 | `endif
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| 314 |
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| 315 | input clk_i;
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| 316 | input rx_i;
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| 317 | output tx_o;
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| 318 | output bus_off_on;
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| 319 | output irq_on;
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| 320 | output clkout_o;
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| 321 |
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| 322 | // Bist
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| 323 | `ifdef CAN_BIST
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| 324 | input mbist_si_i; // bist scan serial in
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| 325 | output mbist_so_o; // bist scan serial out
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| 326 | input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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| 327 | `endif
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| 328 |
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| 329 | reg data_out_fifo_selected;
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| 330 |
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| 331 |
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| 332 | wire [7:0] data_out_fifo;
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| 333 | wire [31:0] data_out_regs;
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| 334 |
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| 335 |
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| 336 | /* Mode register */
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| 337 | wire reset_mode;
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| 338 | wire listen_only_mode;
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| 339 | wire acceptance_filter_mode;
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| 340 | wire self_test_mode;
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| 341 |
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| 342 | /* Command register */
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| 343 | wire release_buffer;
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| 344 | wire tx_request;
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| 345 | wire abort_tx;
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| 346 | wire self_rx_request;
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| 347 | wire single_shot_transmission;
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| 348 | wire tx_state;
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| 349 | wire tx_state_q;
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| 350 | wire overload_request;
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| 351 | wire overload_frame;
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| 352 |
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| 353 |
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| 354 | /* Arbitration Lost Capture Register */
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| 355 | wire read_arbitration_lost_capture_reg;
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| 356 |
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| 357 | /* Error Code Capture Register */
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| 358 | wire read_error_code_capture_reg;
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| 359 | wire [7:0] error_capture_code;
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| 360 |
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| 361 | /* Bus Timing 0 register */
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| 362 | wire [5:0] baud_r_presc;
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| 363 | wire [1:0] sync_jump_width;
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| 364 |
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| 365 | /* Bus Timing 1 register */
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| 366 | wire [3:0] time_segment1;
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| 367 | wire [2:0] time_segment2;
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| 368 | wire triple_sampling;
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| 369 |
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| 370 | /* Error Warning Limit register */
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| 371 | wire [7:0] error_warning_limit;
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| 372 |
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| 373 | /* Rx Error Counter register */
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| 374 | wire we_rx_err_cnt;
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| 375 |
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| 376 | /* Tx Error Counter register */
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| 377 | wire we_tx_err_cnt;
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| 378 |
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| 379 | /* Clock Divider register */
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| 380 | wire extended_mode;
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| 381 |
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| 382 | /* This section is for BASIC and EXTENDED mode */
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| 383 | /* Acceptance code register */
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| 384 | wire [7:0] acceptance_code_0;
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| 385 |
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| 386 | /* Acceptance mask register */
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| 387 | wire [7:0] acceptance_mask_0;
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| 388 | /* End: This section is for BASIC and EXTENDED mode */
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| 389 |
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| 390 |
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| 391 | /* This section is for EXTENDED mode */
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| 392 | /* Acceptance code register */
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| 393 | wire [7:0] acceptance_code_1;
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| 394 | wire [7:0] acceptance_code_2;
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| 395 | wire [7:0] acceptance_code_3;
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| 396 |
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| 397 | /* Acceptance mask register */
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| 398 | wire [7:0] acceptance_mask_1;
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| 399 | wire [7:0] acceptance_mask_2;
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| 400 | wire [7:0] acceptance_mask_3;
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| 401 | /* End: This section is for EXTENDED mode */
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| 402 |
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| 403 | /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
|---|
| 404 | wire [7:0] tx_data_0;
|
|---|
| 405 | wire [7:0] tx_data_1;
|
|---|
| 406 | wire [7:0] tx_data_2;
|
|---|
| 407 | wire [7:0] tx_data_3;
|
|---|
| 408 | wire [7:0] tx_data_4;
|
|---|
| 409 | wire [7:0] tx_data_5;
|
|---|
| 410 | wire [7:0] tx_data_6;
|
|---|
| 411 | wire [7:0] tx_data_7;
|
|---|
| 412 | wire [7:0] tx_data_8;
|
|---|
| 413 | wire [7:0] tx_data_9;
|
|---|
| 414 | wire [7:0] tx_data_10;
|
|---|
| 415 | wire [7:0] tx_data_11;
|
|---|
| 416 | wire [7:0] tx_data_12;
|
|---|
| 417 | /* End: Tx data registers */
|
|---|
| 418 | wire [127:0] rx_dt;
|
|---|
| 419 | wire rx_we;
|
|---|
| 420 |
|
|---|
| 421 | wire cs;
|
|---|
| 422 |
|
|---|
| 423 | /* Output signals from can_btl module */
|
|---|
| 424 | wire sample_point;
|
|---|
| 425 | wire sampled_bit;
|
|---|
| 426 | wire sampled_bit_q;
|
|---|
| 427 | wire tx_point;
|
|---|
| 428 | wire hard_sync;
|
|---|
| 429 |
|
|---|
| 430 | /* output from can_bsp module */
|
|---|
| 431 | wire rx_idle;
|
|---|
| 432 | wire transmitting;
|
|---|
| 433 | wire transmitter;
|
|---|
| 434 | wire go_rx_inter;
|
|---|
| 435 | wire not_first_bit_of_inter;
|
|---|
| 436 | wire set_reset_mode;
|
|---|
| 437 | wire node_bus_off;
|
|---|
| 438 | wire error_status;
|
|---|
| 439 | wire [7:0] rx_err_cnt;
|
|---|
| 440 | wire [7:0] tx_err_cnt;
|
|---|
| 441 | wire rx_err_cnt_dummy; // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
|
|---|
| 442 | wire tx_err_cnt_dummy; // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
|
|---|
| 443 | wire transmit_status;
|
|---|
| 444 | wire receive_status;
|
|---|
| 445 | wire tx_successful;
|
|---|
| 446 | wire need_to_tx;
|
|---|
| 447 | wire overrun;
|
|---|
| 448 | wire info_empty;
|
|---|
| 449 | wire set_bus_error_irq;
|
|---|
| 450 | wire set_arbitration_lost_irq;
|
|---|
| 451 | wire [4:0] arbitration_lost_capture;
|
|---|
| 452 | wire node_error_passive;
|
|---|
| 453 | wire node_error_active;
|
|---|
| 454 | wire [6:0] rx_message_counter;
|
|---|
| 455 | wire tx_next;
|
|---|
| 456 |
|
|---|
| 457 | wire go_overload_frame;
|
|---|
| 458 | wire go_error_frame;
|
|---|
| 459 | wire go_tx;
|
|---|
| 460 | wire send_ack;
|
|---|
| 461 |
|
|---|
| 462 | wire rst;
|
|---|
| 463 | wire we;
|
|---|
| 464 | wire [9:0] addr;
|
|---|
| 465 | wire [31:0] data_in;
|
|---|
| 466 | wire [31:0] data_out;
|
|---|
| 467 | reg rx_sync_tmp;
|
|---|
| 468 | reg rx_sync;
|
|---|
| 469 |
|
|---|
| 470 | /* Connecting can_registers module */
|
|---|
| 471 | //can_registers i_can_registers
|
|---|
| 472 | can_registers #(.TXMBOX_DEPTH(TXMBOX_DEPTH), .RXMBOX_DEPTH(RXMBOX_DEPTH)) i_can_registers
|
|---|
| 473 |
|
|---|
| 474 | (
|
|---|
| 475 | .clk(clk_i),
|
|---|
| 476 | .rst(rst),
|
|---|
| 477 | .cs(cs),
|
|---|
| 478 | .we(we),
|
|---|
| 479 | .addr(addr),
|
|---|
| 480 | .data_in(data_in),
|
|---|
| 481 | .data_out(data_out),
|
|---|
| 482 | .irq_n(irq_on),
|
|---|
| 483 |
|
|---|
| 484 | .sample_point(sample_point),
|
|---|
| 485 | .transmitting(transmitting),
|
|---|
| 486 | .set_reset_mode(set_reset_mode),
|
|---|
| 487 | .node_bus_off(node_bus_off),
|
|---|
| 488 | .error_status(error_status),
|
|---|
| 489 | .rx_err_cnt(rx_err_cnt),
|
|---|
| 490 | .tx_err_cnt(tx_err_cnt),
|
|---|
| 491 | .transmit_status(transmit_status),
|
|---|
| 492 | .receive_status(receive_status),
|
|---|
| 493 | .tx_successful(tx_successful),
|
|---|
| 494 | .need_to_tx(need_to_tx),
|
|---|
| 495 | .overrun(overrun),
|
|---|
| 496 | .info_empty(info_empty),
|
|---|
| 497 | .set_bus_error_irq(set_bus_error_irq),
|
|---|
| 498 | .set_arbitration_lost_irq(set_arbitration_lost_irq),
|
|---|
| 499 | .arbitration_lost_capture(arbitration_lost_capture),
|
|---|
| 500 | .node_error_passive(node_error_passive),
|
|---|
| 501 | .node_error_active(node_error_active),
|
|---|
| 502 | .rx_message_counter(rx_message_counter),
|
|---|
| 503 |
|
|---|
| 504 |
|
|---|
| 505 | /* Mode register */
|
|---|
| 506 | .reset_mode(reset_mode),
|
|---|
| 507 | .listen_only_mode(listen_only_mode),
|
|---|
| 508 | .acceptance_filter_mode(acceptance_filter_mode),
|
|---|
| 509 | .self_test_mode(self_test_mode),
|
|---|
| 510 |
|
|---|
| 511 | /* Command register */
|
|---|
| 512 | .clear_data_overrun(),
|
|---|
| 513 | .release_buffer(release_buffer),
|
|---|
| 514 | .abort_tx(abort_tx),
|
|---|
| 515 | .tx_request(tx_request),
|
|---|
| 516 | .self_rx_request(self_rx_request),
|
|---|
| 517 | .single_shot_transmission(single_shot_transmission),
|
|---|
| 518 | .tx_state(tx_state),
|
|---|
| 519 | .tx_state_q(tx_state_q),
|
|---|
| 520 | .overload_request(overload_request),
|
|---|
| 521 | .overload_frame(overload_frame),
|
|---|
| 522 |
|
|---|
| 523 | /* Arbitration Lost Capture Register */
|
|---|
| 524 | .read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
|
|---|
| 525 |
|
|---|
| 526 | /* Error Code Capture Register */
|
|---|
| 527 | .read_error_code_capture_reg(read_error_code_capture_reg),
|
|---|
| 528 | .error_capture_code(error_capture_code),
|
|---|
| 529 |
|
|---|
| 530 | /* Bus Timing 0 register */
|
|---|
| 531 | .baud_r_presc(baud_r_presc),
|
|---|
| 532 | .sync_jump_width(sync_jump_width),
|
|---|
| 533 |
|
|---|
| 534 | /* Bus Timing 1 register */
|
|---|
| 535 | .time_segment1(time_segment1),
|
|---|
| 536 | .time_segment2(time_segment2),
|
|---|
| 537 | .triple_sampling(triple_sampling),
|
|---|
| 538 |
|
|---|
| 539 | /* Error Warning Limit register */
|
|---|
| 540 | .error_warning_limit(error_warning_limit),
|
|---|
| 541 |
|
|---|
| 542 | /* Rx Error Counter register */
|
|---|
| 543 | .we_rx_err_cnt(we_rx_err_cnt),
|
|---|
| 544 |
|
|---|
| 545 | /* Tx Error Counter register */
|
|---|
| 546 | .we_tx_err_cnt(we_tx_err_cnt),
|
|---|
| 547 |
|
|---|
| 548 | /* Clock Divider register */
|
|---|
| 549 | .extended_mode(extended_mode),
|
|---|
| 550 | .clkout(clkout_o),
|
|---|
| 551 |
|
|---|
| 552 | /* This section is for BASIC and EXTENDED mode */
|
|---|
| 553 | /* Acceptance code register */
|
|---|
| 554 | .acceptance_code_0(acceptance_code_0),
|
|---|
| 555 |
|
|---|
| 556 | /* Acceptance mask register */
|
|---|
| 557 | .acceptance_mask_0(acceptance_mask_0),
|
|---|
| 558 | /* End: This section is for BASIC and EXTENDED mode */
|
|---|
| 559 |
|
|---|
| 560 | /* This section is for EXTENDED mode */
|
|---|
| 561 | /* Acceptance code register */
|
|---|
| 562 | .acceptance_code_1(acceptance_code_1),
|
|---|
| 563 | .acceptance_code_2(acceptance_code_2),
|
|---|
| 564 | .acceptance_code_3(acceptance_code_3),
|
|---|
| 565 |
|
|---|
| 566 | /* Acceptance mask register */
|
|---|
| 567 | .acceptance_mask_1(acceptance_mask_1),
|
|---|
| 568 | .acceptance_mask_2(acceptance_mask_2),
|
|---|
| 569 | .acceptance_mask_3(acceptance_mask_3),
|
|---|
| 570 | /* End: This section is for EXTENDED mode */
|
|---|
| 571 |
|
|---|
| 572 | .rx_dt(rx_dt),
|
|---|
| 573 | .rx_we(rx_we),
|
|---|
| 574 | /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
|---|
| 575 | .tx_data_0(tx_data_0),
|
|---|
| 576 | .tx_data_1(tx_data_1),
|
|---|
| 577 | .tx_data_2(tx_data_2),
|
|---|
| 578 | .tx_data_3(tx_data_3),
|
|---|
| 579 | .tx_data_4(tx_data_4),
|
|---|
| 580 | .tx_data_5(tx_data_5),
|
|---|
| 581 | .tx_data_6(tx_data_6),
|
|---|
| 582 | .tx_data_7(tx_data_7),
|
|---|
| 583 | .tx_data_8(tx_data_8),
|
|---|
| 584 | .tx_data_9(tx_data_9),
|
|---|
| 585 | .tx_data_10(tx_data_10),
|
|---|
| 586 | .tx_data_11(tx_data_11),
|
|---|
| 587 | .tx_data_12(tx_data_12)
|
|---|
| 588 | /* End: Tx data registers */
|
|---|
| 589 | );
|
|---|
| 590 |
|
|---|
| 591 |
|
|---|
| 592 |
|
|---|
| 593 |
|
|---|
| 594 | /* Connecting can_btl module */
|
|---|
| 595 | can_btl i_can_btl
|
|---|
| 596 | (
|
|---|
| 597 | .clk(clk_i),
|
|---|
| 598 | .rst(rst),
|
|---|
| 599 | .rx(rx_sync),
|
|---|
| 600 | .tx(tx_o),
|
|---|
| 601 |
|
|---|
| 602 | /* Bus Timing 0 register */
|
|---|
| 603 | .baud_r_presc(baud_r_presc),
|
|---|
| 604 | .sync_jump_width(sync_jump_width),
|
|---|
| 605 |
|
|---|
| 606 | /* Bus Timing 1 register */
|
|---|
| 607 | .time_segment1(time_segment1),
|
|---|
| 608 | .time_segment2(time_segment2),
|
|---|
| 609 | .triple_sampling(triple_sampling),
|
|---|
| 610 |
|
|---|
| 611 | /* Output signals from this module */
|
|---|
| 612 | .sample_point(sample_point),
|
|---|
| 613 | .sampled_bit(sampled_bit),
|
|---|
| 614 | .sampled_bit_q(sampled_bit_q),
|
|---|
| 615 | .tx_point(tx_point),
|
|---|
| 616 | .hard_sync(hard_sync),
|
|---|
| 617 |
|
|---|
| 618 |
|
|---|
| 619 | /* output from can_bsp module */
|
|---|
| 620 | .rx_idle(rx_idle),
|
|---|
| 621 | .rx_inter(rx_inter),
|
|---|
| 622 | .transmitting(transmitting),
|
|---|
| 623 | .transmitter(transmitter),
|
|---|
| 624 | .go_rx_inter(go_rx_inter),
|
|---|
| 625 | .tx_next(tx_next),
|
|---|
| 626 |
|
|---|
| 627 | .go_overload_frame(go_overload_frame),
|
|---|
| 628 | .go_error_frame(go_error_frame),
|
|---|
| 629 | .go_tx(go_tx),
|
|---|
| 630 | .send_ack(send_ack),
|
|---|
| 631 | .node_error_passive(node_error_passive)
|
|---|
| 632 |
|
|---|
| 633 |
|
|---|
| 634 |
|
|---|
| 635 | );
|
|---|
| 636 |
|
|---|
| 637 |
|
|---|
| 638 |
|
|---|
| 639 | can_bsp i_can_bsp
|
|---|
| 640 | (
|
|---|
| 641 | .clk(clk_i),
|
|---|
| 642 | .rst(rst),
|
|---|
| 643 |
|
|---|
| 644 | /* From btl module */
|
|---|
| 645 | .sample_point(sample_point),
|
|---|
| 646 | .sampled_bit(sampled_bit),
|
|---|
| 647 | .sampled_bit_q(sampled_bit_q),
|
|---|
| 648 | .tx_point(tx_point),
|
|---|
| 649 | .hard_sync(hard_sync),
|
|---|
| 650 |
|
|---|
| 651 | .addr(8'h0),
|
|---|
| 652 | .data_in(data_in),
|
|---|
| 653 | .data_out(data_out_fifo),
|
|---|
| 654 | .fifo_selected(data_out_fifo_selected),
|
|---|
| 655 |
|
|---|
| 656 | /* Mode register */
|
|---|
| 657 | .reset_mode(reset_mode),
|
|---|
| 658 | .listen_only_mode(listen_only_mode),
|
|---|
| 659 | .acceptance_filter_mode(acceptance_filter_mode),
|
|---|
| 660 | .self_test_mode(self_test_mode),
|
|---|
| 661 |
|
|---|
| 662 | /* Command register */
|
|---|
| 663 | .release_buffer(release_buffer),
|
|---|
| 664 | .tx_request(tx_request),
|
|---|
| 665 | .abort_tx(abort_tx),
|
|---|
| 666 | .self_rx_request(self_rx_request),
|
|---|
| 667 | .single_shot_transmission(single_shot_transmission),
|
|---|
| 668 | .tx_state(tx_state),
|
|---|
| 669 | .tx_state_q(tx_state_q),
|
|---|
| 670 | .overload_request(overload_request),
|
|---|
| 671 | .overload_frame(overload_frame),
|
|---|
| 672 |
|
|---|
| 673 | /* Arbitration Lost Capture Register */
|
|---|
| 674 | .read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
|
|---|
| 675 |
|
|---|
| 676 | /* Error Code Capture Register */
|
|---|
| 677 | .read_error_code_capture_reg(read_error_code_capture_reg),
|
|---|
| 678 | .error_capture_code(error_capture_code),
|
|---|
| 679 |
|
|---|
| 680 | /* Error Warning Limit register */
|
|---|
| 681 | .error_warning_limit(error_warning_limit),
|
|---|
| 682 |
|
|---|
| 683 | /* Rx Error Counter register */
|
|---|
| 684 | .we_rx_err_cnt(we_rx_err_cnt),
|
|---|
| 685 |
|
|---|
| 686 | /* Tx Error Counter register */
|
|---|
| 687 | .we_tx_err_cnt(we_tx_err_cnt),
|
|---|
| 688 |
|
|---|
| 689 | /* Clock Divider register */
|
|---|
| 690 | .extended_mode(extended_mode),
|
|---|
| 691 |
|
|---|
| 692 | /* output from can_bsp module */
|
|---|
| 693 | .rx_idle(rx_idle),
|
|---|
| 694 | .transmitting(transmitting),
|
|---|
| 695 | .transmitter(transmitter),
|
|---|
| 696 | .go_rx_inter(go_rx_inter),
|
|---|
| 697 | .not_first_bit_of_inter(not_first_bit_of_inter),
|
|---|
| 698 | .rx_inter(rx_inter),
|
|---|
| 699 | .set_reset_mode(set_reset_mode),
|
|---|
| 700 | .node_bus_off(node_bus_off),
|
|---|
| 701 | .error_status(error_status),
|
|---|
| 702 | .rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}), // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
|
|---|
| 703 | .tx_err_cnt({tx_err_cnt_dummy, tx_err_cnt[7:0]}), // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
|
|---|
| 704 | .transmit_status(transmit_status),
|
|---|
| 705 | .receive_status(receive_status),
|
|---|
| 706 | .tx_successful(tx_successful),
|
|---|
| 707 | .need_to_tx(need_to_tx),
|
|---|
| 708 | .overrun(overrun),
|
|---|
| 709 | .info_empty(info_empty),
|
|---|
| 710 | .set_bus_error_irq(set_bus_error_irq),
|
|---|
| 711 | .set_arbitration_lost_irq(set_arbitration_lost_irq),
|
|---|
| 712 | .arbitration_lost_capture(arbitration_lost_capture),
|
|---|
| 713 | .node_error_passive(node_error_passive),
|
|---|
| 714 | .node_error_active(node_error_active),
|
|---|
| 715 | .rx_message_counter(rx_message_counter),
|
|---|
| 716 |
|
|---|
| 717 | /* This section is for BASIC and EXTENDED mode */
|
|---|
| 718 | /* Acceptance code register */
|
|---|
| 719 | .acceptance_code_0(acceptance_code_0),
|
|---|
| 720 |
|
|---|
| 721 | /* Acceptance mask register */
|
|---|
| 722 | .acceptance_mask_0(acceptance_mask_0),
|
|---|
| 723 | /* End: This section is for BASIC and EXTENDED mode */
|
|---|
| 724 |
|
|---|
| 725 | /* This section is for EXTENDED mode */
|
|---|
| 726 | /* Acceptance code register */
|
|---|
| 727 | .acceptance_code_1(acceptance_code_1),
|
|---|
| 728 | .acceptance_code_2(acceptance_code_2),
|
|---|
| 729 | .acceptance_code_3(acceptance_code_3),
|
|---|
| 730 |
|
|---|
| 731 | /* Acceptance mask register */
|
|---|
| 732 | .acceptance_mask_1(acceptance_mask_1),
|
|---|
| 733 | .acceptance_mask_2(acceptance_mask_2),
|
|---|
| 734 | .acceptance_mask_3(acceptance_mask_3),
|
|---|
| 735 | /* End: This section is for EXTENDED mode */
|
|---|
| 736 |
|
|---|
| 737 | /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
|---|
| 738 | .tx_data_0(tx_data_0),
|
|---|
| 739 | .tx_data_1(tx_data_1),
|
|---|
| 740 | .tx_data_2(tx_data_2),
|
|---|
| 741 | .tx_data_3(tx_data_3),
|
|---|
| 742 | .tx_data_4(tx_data_4),
|
|---|
| 743 | .tx_data_5(tx_data_5),
|
|---|
| 744 | .tx_data_6(tx_data_6),
|
|---|
| 745 | .tx_data_7(tx_data_7),
|
|---|
| 746 | .tx_data_8(tx_data_8),
|
|---|
| 747 | .tx_data_9(tx_data_9),
|
|---|
| 748 | .tx_data_10(tx_data_10),
|
|---|
| 749 | .tx_data_11(tx_data_11),
|
|---|
| 750 | .tx_data_12(tx_data_12),
|
|---|
| 751 | /* End: Tx data registers */
|
|---|
| 752 | .rx_dt(rx_dt),
|
|---|
| 753 | .rx_we(rx_we),
|
|---|
| 754 |
|
|---|
| 755 | /* Tx signal */
|
|---|
| 756 | .tx(tx_o),
|
|---|
| 757 | .tx_next(tx_next),
|
|---|
| 758 | .bus_off_on(bus_off_on),
|
|---|
| 759 |
|
|---|
| 760 | .go_overload_frame(go_overload_frame),
|
|---|
| 761 | .go_error_frame(go_error_frame),
|
|---|
| 762 | .go_tx(go_tx),
|
|---|
| 763 | .send_ack(send_ack)
|
|---|
| 764 |
|
|---|
| 765 |
|
|---|
| 766 | `ifdef CAN_BIST
|
|---|
| 767 | ,
|
|---|
| 768 | /* BIST signals */
|
|---|
| 769 | .mbist_si_i(mbist_si_i),
|
|---|
| 770 | .mbist_so_o(mbist_so_o),
|
|---|
| 771 | .mbist_ctrl_i(mbist_ctrl_i)
|
|---|
| 772 | `endif
|
|---|
| 773 | );
|
|---|
| 774 |
|
|---|
| 775 | assign extended_mode_o = extended_mode;
|
|---|
| 776 |
|
|---|
| 777 | // Multiplexing wb_dat_o from registers and rx fifo
|
|---|
| 778 | always @ (extended_mode or addr or reset_mode)
|
|---|
| 779 | begin
|
|---|
| 780 | if (extended_mode & (~reset_mode) & ((addr >= 10'd16) && (addr <= 10'd28)) | (~extended_mode) & ((addr >= 10'd20) && (addr <= 10'd29)))
|
|---|
| 781 | data_out_fifo_selected = 1'b1;
|
|---|
| 782 | else
|
|---|
| 783 | data_out_fifo_selected = 1'b0;
|
|---|
| 784 | end
|
|---|
| 785 |
|
|---|
| 786 |
|
|---|
| 787 | //always @ (posedge clk_i or posedge rst)
|
|---|
| 788 | //begin
|
|---|
| 789 | // if (rst)
|
|---|
| 790 | // begin
|
|---|
| 791 | // data_out <= 0;
|
|---|
| 792 | // end
|
|---|
| 793 | // else if (cs & (~we))
|
|---|
| 794 | // begin
|
|---|
| 795 | // if (data_out_fifo_selected)
|
|---|
| 796 | // data_out <=#Tp data_out_fifo;
|
|---|
| 797 | // else
|
|---|
| 798 | // data_out <=#Tp data_out_regs;
|
|---|
| 799 | // end
|
|---|
| 800 | //end
|
|---|
| 801 |
|
|---|
| 802 |
|
|---|
| 803 |
|
|---|
| 804 | always @ (posedge clk_i or posedge rst)
|
|---|
| 805 | begin
|
|---|
| 806 | if (rst)
|
|---|
| 807 | begin
|
|---|
| 808 | rx_sync_tmp <= 1'b1;
|
|---|
| 809 | rx_sync <= 1'b1;
|
|---|
| 810 | end
|
|---|
| 811 | else
|
|---|
| 812 | begin
|
|---|
| 813 | rx_sync_tmp <=#Tp rx_i;
|
|---|
| 814 | rx_sync <=#Tp rx_sync_tmp;
|
|---|
| 815 | end
|
|---|
| 816 | end
|
|---|
| 817 |
|
|---|
| 818 |
|
|---|
| 819 |
|
|---|
| 820 | `ifdef CAN_WISHBONE_IF
|
|---|
| 821 |
|
|---|
| 822 | assign cs_can_i = 1'b1;
|
|---|
| 823 |
|
|---|
| 824 | // Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
|
|---|
| 825 | always @ (posedge clk_i or posedge rst)
|
|---|
| 826 | begin
|
|---|
| 827 | if (rst)
|
|---|
| 828 | begin
|
|---|
| 829 | cs_sync1 <= 1'b0;
|
|---|
| 830 | cs_sync2 <= 1'b0;
|
|---|
| 831 | cs_sync3 <= 1'b0;
|
|---|
| 832 | cs_sync_rst1 <= 1'b0;
|
|---|
| 833 | cs_sync_rst2 <= 1'b0;
|
|---|
| 834 | end
|
|---|
| 835 | else
|
|---|
| 836 | begin
|
|---|
| 837 | cs_sync1 <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_can_i;
|
|---|
| 838 | cs_sync2 <=#Tp cs_sync1 & (~cs_sync_rst2);
|
|---|
| 839 | cs_sync3 <=#Tp cs_sync2 & (~cs_sync_rst2);
|
|---|
| 840 | cs_sync_rst1 <=#Tp cs_ack3;
|
|---|
| 841 | cs_sync_rst2 <=#Tp cs_sync_rst1;
|
|---|
| 842 | end
|
|---|
| 843 | end
|
|---|
| 844 |
|
|---|
| 845 |
|
|---|
| 846 | assign cs = cs_sync2 & (~cs_sync3);
|
|---|
| 847 |
|
|---|
| 848 |
|
|---|
| 849 | always @ (posedge wb_clk_i)
|
|---|
| 850 | begin
|
|---|
| 851 | cs_ack1 <=#Tp cs_sync3;
|
|---|
| 852 | cs_ack2 <=#Tp cs_ack1;
|
|---|
| 853 | cs_ack3 <=#Tp cs_ack2;
|
|---|
| 854 | end
|
|---|
| 855 |
|
|---|
| 856 |
|
|---|
| 857 |
|
|---|
| 858 | // Generating acknowledge signal
|
|---|
| 859 | always @ (posedge wb_clk_i)
|
|---|
| 860 | begin
|
|---|
| 861 | wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
|
|---|
| 862 | end
|
|---|
| 863 |
|
|---|
| 864 |
|
|---|
| 865 | assign rst = wb_rst_i;
|
|---|
| 866 | assign we = wb_we_i;
|
|---|
| 867 | assign addr = wb_adr_i;
|
|---|
| 868 | assign data_in = wb_dat_i;
|
|---|
| 869 | assign wb_dat_o = data_out;
|
|---|
| 870 |
|
|---|
| 871 |
|
|---|
| 872 | `else
|
|---|
| 873 | `ifdef CAN_AVALON_IF
|
|---|
| 874 |
|
|---|
| 875 | assign rst = av_rst_i;
|
|---|
| 876 | assign cs = av_cs_i;
|
|---|
| 877 | assign we = av_wr_i;
|
|---|
| 878 | assign addr = {av_adr_i,2'h0};
|
|---|
| 879 | assign data_in = av_dat_i;
|
|---|
| 880 | assign av_dat_o = data_out;
|
|---|
| 881 |
|
|---|
| 882 | `else
|
|---|
| 883 |
|
|---|
| 884 | // Latching address
|
|---|
| 885 | always @ (posedge clk_i or posedge rst)
|
|---|
| 886 | begin
|
|---|
| 887 | if (rst)
|
|---|
| 888 | addr_latched <= 10'h0;
|
|---|
| 889 | else if (ale_i)
|
|---|
| 890 | addr_latched <=#Tp port_0_io;
|
|---|
| 891 | end
|
|---|
| 892 |
|
|---|
| 893 |
|
|---|
| 894 | // Generating delayed wr_i and rd_i signals
|
|---|
| 895 | always @ (posedge clk_i or posedge rst)
|
|---|
| 896 | begin
|
|---|
| 897 | if (rst)
|
|---|
| 898 | begin
|
|---|
| 899 | wr_i_q <= 1'b0;
|
|---|
| 900 | rd_i_q <= 1'b0;
|
|---|
| 901 | end
|
|---|
| 902 | else
|
|---|
| 903 | begin
|
|---|
| 904 | wr_i_q <=#Tp wr_i;
|
|---|
| 905 | rd_i_q <=#Tp rd_i;
|
|---|
| 906 | end
|
|---|
| 907 | end
|
|---|
| 908 |
|
|---|
| 909 |
|
|---|
| 910 | assign cs = ((wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q))) & cs_can_i;
|
|---|
| 911 |
|
|---|
| 912 |
|
|---|
| 913 | assign rst = rst_i;
|
|---|
| 914 | assign we = wr_i;
|
|---|
| 915 | assign addr = addr_latched;
|
|---|
| 916 | assign data_in = port_0_io;
|
|---|
| 917 | assign port_0_io = (cs_can_i & rd_i)? data_out : {4{8'hz}};
|
|---|
| 918 |
|
|---|
| 919 | `endif
|
|---|
| 920 | `endif
|
|---|
| 921 |
|
|---|
| 922 |
|
|---|
| 923 | endmodule
|
|---|
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