source: rc_os_nios2/DE0_Nano_QSYS_DEMO/canc/hdl/can_rxmboxacf.v@ 128

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1//////////////////////////////////////////////////////////////////////
2//// ////
3//// can_rxmboxacf.v ////
4//// ////
5//// ////
6//// This file is part of the CAN Protocol Controller ////
7//// ////
8//// ////
9//// Author(s): ////
10//// Center for Embedded Computing Systems ////
11//// Graduate School of Information Science, Nagoya Univ., JAPAN ////
12//// ////
13//// ////
14//// All additional information is available in the README.txt ////
15//// file. ////
16//// ////
17//////////////////////////////////////////////////////////////////////
18//// ////
19//// Copyright (C) 2011-2013 Authors ////
20//// ////
21//// This source file may be used and distributed without ////
22//// restriction provided that this copyright statement is not ////
23//// removed from the file and that any derivative work contains ////
24//// the original copyright notice and the associated disclaimer. ////
25//// ////
26//// This source file is free software; you can redistribute it ////
27//// and/or modify it under the terms of the GNU Lesser General ////
28//// Public License as published by the Free Software Foundation; ////
29//// either version 2.1 of the License, or (at your option) any ////
30//// later version. ////
31//// ////
32//// This source is distributed in the hope that it will be ////
33//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
34//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
35//// PURPOSE. See the GNU Lesser General Public License for more ////
36//// details. ////
37//// ////
38//// You should have received a copy of the GNU Lesser General ////
39//// Public License along with this source; if not, download it ////
40//// from http://www.opencores.org/lgpl.shtml ////
41//// ////
42//// The CAN protocol is developed by Robert Bosch GmbH and ////
43//// protected by patents. Anybody who wants to implement this ////
44//// CAN IP core on silicon has to obtain a CAN protocol license ////
45//// from Bosch. ////
46//// ////
47//////////////////////////////////////////////////////////////////////
48//
49
50// synopsys translate_off
51`include "timescale.v"
52// synopsys translate_on
53`include "can_defines.v"
54
55module can_rxmboxacf(
56 clk,
57 rst,
58 sample_point,
59
60 rxwait,
61 rxcmp,
62
63 reset_mode,
64 acceptance_filter_mode,
65 extended_mode,
66
67 rxmask,
68 rxcode,
69
70 rxdatawin,
71
72 rx_dt,
73 rx_we,
74
75 rxmsgdata,
76 rx_we_ff
77// input wire clk,
78// input wire rst,
79// input wire sample_point,
80//
81// input wire [31:0] rxwait,
82// input wire [31:0] rxcmp,
83//
84// input wire reset_mode,
85// input wire acceptance_filter_mode,
86// input wire extended_mode,
87//
88// input wire [1023:0] rxmask,
89// input wire [1023:0] rxcode,
90//
91// input wire [ 4:0] rxdatawin,
92//
93// input wire [ 127:0] rx_dt,
94// input rx_we,
95//
96// output reg [ 127:0] rxmsgdata,
97// output wire [ 31:0] rx_we_ff
98);
99
100parameter Tp = 1;
101parameter TXMBOX_DEPTH = 1; /* 1(Min=2) - 4(Max=16) */
102parameter RXMBOX_DEPTH = 1; /* 1(Min=2) - 5(Max=32) */
103localparam TXMBOX_BITS = (TXMBOX_DEPTH > 4) ? 16 : (2**TXMBOX_DEPTH);
104localparam RXMBOX_BITS = (RXMBOX_DEPTH > 5) ? 32 :(2**RXMBOX_DEPTH);
105
106input wire clk;
107input wire rst;
108input wire sample_point;
109
110input wire [RXMBOX_BITS-1:0] rxwait;
111input wire [RXMBOX_BITS-1:0] rxcmp;
112
113input wire reset_mode;
114input wire acceptance_filter_mode;
115input wire extended_mode;
116
117//input wire [RXMBOX_BITS*32-1:0] rxmask;
118//input wire [RXMBOX_BITS*32-1:0] rxcode;
119input wire [1023:0] rxmask;
120input wire [1023:0] rxcode;
121
122input wire [RXMBOX_DEPTH-1:0] rxdatawin;
123//input wire [ 4:0] rxdatawin;
124
125input wire [ 127:0] rx_dt;
126input rx_we;
127
128output reg [ 127:0] rxmsgdata;
129//output wire [31:0] rx_we_ff;
130output wire [RXMBOX_BITS-1:0] rx_we_ff;
131
132wire id_ok;
133reg [RXMBOX_BITS-1:0] rx_we_on,rx_we_on_q;
134//reg [31:0] rx_we_on,rx_we_on_q;
135wire [RXMBOX_BITS-1:0] rx_we_off;
136//wire [31:0] rx_we_off;
137reg [2:0] cnt;
138reg [RXMBOX_BITS-1:0] rx_en;
139//reg [31:0] rx_en;
140reg [31:0] rxcode_in;
141reg [31:0] rxmask_in;
142reg timovr;
143reg [RXMBOX_DEPTH-1:0] rmbox_cnt;
144//reg [4:0] rmbox_cnt;
145wire [28:0] id;
146
147always @ (posedge clk or posedge rst)
148begin
149 if(rst) rmbox_cnt <= {(RXMBOX_DEPTH){1'h0}};
150 else if(rx_we) rmbox_cnt <=#Tp 1'b1;
151 else if(~|rmbox_cnt) rmbox_cnt <=#Tp rmbox_cnt;
152 else rmbox_cnt <=#Tp rmbox_cnt + 1'b1;
153// if(rst) rmbox_cnt <= 5'h0;
154// else if(rx_we) rmbox_cnt <=#Tp 5'h1;
155// else if(~|rmbox_cnt) rmbox_cnt <=#Tp rmbox_cnt;
156// else rmbox_cnt <=#Tp rmbox_cnt+ 5'h1;
157end
158
159wire no_byte0 = rx_dt[1*32+4] | (rx_dt[1*32+3:1*32]<4'h1); //rtr1 | (data_len<4'h1);
160wire no_byte1 = rx_dt[1*32+4] | (rx_dt[1*32+3:1*32]<4'h2); //rtr1 | (data_len<4'h2);
161assign id = (rx_dt[0*32+31])? rx_dt[0*32+28:0*32]: {18'h0,rx_dt[0*32+28:0*32+18]};
162
163always @ (*) begin
164 if (rmbox_cnt == 0) begin rxcode_in = rxcode[ 0*32+31: 0*32]; rxmask_in = rxmask[ 0*32+31: 0*32]; end
165 else if (rmbox_cnt == 1) begin rxcode_in = rxcode[ 1*32+31: 1*32]; rxmask_in = rxmask[ 1*32+31: 1*32]; end
166 else if (rmbox_cnt == 2) begin rxcode_in = rxcode[ 2*32+31: 2*32]; rxmask_in = rxmask[ 2*32+31: 2*32]; end
167 else if (rmbox_cnt == 3) begin rxcode_in = rxcode[ 3*32+31: 3*32]; rxmask_in = rxmask[ 3*32+31: 3*32]; end
168 else if (rmbox_cnt == 4) begin rxcode_in = rxcode[ 4*32+31: 4*32]; rxmask_in = rxmask[ 4*32+31: 4*32]; end
169 else if (rmbox_cnt == 5) begin rxcode_in = rxcode[ 5*32+31: 5*32]; rxmask_in = rxmask[ 5*32+31: 5*32]; end
170 else if (rmbox_cnt == 6) begin rxcode_in = rxcode[ 6*32+31: 6*32]; rxmask_in = rxmask[ 6*32+31: 6*32]; end
171 else if (rmbox_cnt == 7) begin rxcode_in = rxcode[ 7*32+31: 7*32]; rxmask_in = rxmask[ 7*32+31: 7*32]; end
172 else if (rmbox_cnt == 8) begin rxcode_in = rxcode[ 8*32+31: 8*32]; rxmask_in = rxmask[ 8*32+31: 8*32]; end
173 else if (rmbox_cnt == 9) begin rxcode_in = rxcode[ 9*32+31: 9*32]; rxmask_in = rxmask[ 9*32+31: 9*32]; end
174 else if (rmbox_cnt == 10) begin rxcode_in = rxcode[10*32+31:10*32]; rxmask_in = rxmask[10*32+31:10*32]; end
175 else if (rmbox_cnt == 11) begin rxcode_in = rxcode[11*32+31:11*32]; rxmask_in = rxmask[11*32+31:11*32]; end
176 else if (rmbox_cnt == 12) begin rxcode_in = rxcode[12*32+31:12*32]; rxmask_in = rxmask[12*32+31:12*32]; end
177 else if (rmbox_cnt == 13) begin rxcode_in = rxcode[13*32+31:13*32]; rxmask_in = rxmask[13*32+31:13*32]; end
178 else if (rmbox_cnt == 14) begin rxcode_in = rxcode[14*32+31:14*32]; rxmask_in = rxmask[14*32+31:14*32]; end
179 else if (rmbox_cnt == 15) begin rxcode_in = rxcode[15*32+31:15*32]; rxmask_in = rxmask[15*32+31:15*32]; end
180 else if (rmbox_cnt == 16) begin rxcode_in = rxcode[16*32+31:16*32]; rxmask_in = rxmask[16*32+31:16*32]; end
181 else if (rmbox_cnt == 17) begin rxcode_in = rxcode[17*32+31:17*32]; rxmask_in = rxmask[17*32+31:17*32]; end
182 else if (rmbox_cnt == 18) begin rxcode_in = rxcode[18*32+31:18*32]; rxmask_in = rxmask[18*32+31:18*32]; end
183 else if (rmbox_cnt == 19) begin rxcode_in = rxcode[19*32+31:19*32]; rxmask_in = rxmask[19*32+31:19*32]; end
184 else if (rmbox_cnt == 20) begin rxcode_in = rxcode[20*32+31:20*32]; rxmask_in = rxmask[20*32+31:20*32]; end
185 else if (rmbox_cnt == 21) begin rxcode_in = rxcode[21*32+31:21*32]; rxmask_in = rxmask[21*32+31:21*32]; end
186 else if (rmbox_cnt == 22) begin rxcode_in = rxcode[22*32+31:22*32]; rxmask_in = rxmask[22*32+31:22*32]; end
187 else if (rmbox_cnt == 23) begin rxcode_in = rxcode[23*32+31:23*32]; rxmask_in = rxmask[23*32+31:23*32]; end
188 else if (rmbox_cnt == 24) begin rxcode_in = rxcode[24*32+31:24*32]; rxmask_in = rxmask[24*32+31:24*32]; end
189 else if (rmbox_cnt == 25) begin rxcode_in = rxcode[25*32+31:25*32]; rxmask_in = rxmask[25*32+31:25*32]; end
190 else if (rmbox_cnt == 26) begin rxcode_in = rxcode[26*32+31:26*32]; rxmask_in = rxmask[26*32+31:26*32]; end
191 else if (rmbox_cnt == 27) begin rxcode_in = rxcode[27*32+31:27*32]; rxmask_in = rxmask[27*32+31:27*32]; end
192 else if (rmbox_cnt == 28) begin rxcode_in = rxcode[28*32+31:28*32]; rxmask_in = rxmask[28*32+31:28*32]; end
193 else if (rmbox_cnt == 29) begin rxcode_in = rxcode[29*32+31:29*32]; rxmask_in = rxmask[29*32+31:29*32]; end
194 else if (rmbox_cnt == 30) begin rxcode_in = rxcode[30*32+31:30*32]; rxmask_in = rxmask[30*32+31:30*32]; end
195 else if (rmbox_cnt == 31) begin rxcode_in = rxcode[31*32+31:31*32]; rxmask_in = rxmask[31*32+31:31*32]; end
196 else if (rmbox_cnt == 32) begin rxcode_in = rxcode[32*32+31:32*32]; rxmask_in = rxmask[32*32+31:32*32]; end
197end
198
199//always @ (*)
200//begin
201// case(rmbox_cnt)
202// 5'h00: begin rxcode_in = rxcode[ 0*32+31: 0*32]; rxmask_in = rxmask[ 0*32+31: 0*32]; end
203// 5'h01: begin rxcode_in = rxcode[ 1*32+31: 1*32]; rxmask_in = rxmask[ 1*32+31: 1*32]; end
204// 5'h02: begin rxcode_in = rxcode[ 2*32+31: 2*32]; rxmask_in = rxmask[ 2*32+31: 2*32]; end
205// 5'h03: begin rxcode_in = rxcode[ 3*32+31: 3*32]; rxmask_in = rxmask[ 3*32+31: 3*32]; end
206// 5'h04: begin rxcode_in = rxcode[ 4*32+31: 4*32]; rxmask_in = rxmask[ 4*32+31: 4*32]; end
207// 5'h05: begin rxcode_in = rxcode[ 5*32+31: 5*32]; rxmask_in = rxmask[ 5*32+31: 5*32]; end
208// 5'h06: begin rxcode_in = rxcode[ 6*32+31: 6*32]; rxmask_in = rxmask[ 6*32+31: 6*32]; end
209// 5'h07: begin rxcode_in = rxcode[ 7*32+31: 7*32]; rxmask_in = rxmask[ 7*32+31: 7*32]; end
210// 5'h08: begin rxcode_in = rxcode[ 8*32+31: 8*32]; rxmask_in = rxmask[ 8*32+31: 8*32]; end
211// 5'h09: begin rxcode_in = rxcode[ 9*32+31: 9*32]; rxmask_in = rxmask[ 9*32+31: 9*32]; end
212// 5'h0A: begin rxcode_in = rxcode[10*32+31:10*32]; rxmask_in = rxmask[10*32+31:10*32]; end
213// 5'h0B: begin rxcode_in = rxcode[11*32+31:11*32]; rxmask_in = rxmask[11*32+31:11*32]; end
214// 5'h0C: begin rxcode_in = rxcode[12*32+31:12*32]; rxmask_in = rxmask[12*32+31:12*32]; end
215// 5'h0D: begin rxcode_in = rxcode[13*32+31:13*32]; rxmask_in = rxmask[13*32+31:13*32]; end
216// 5'h0E: begin rxcode_in = rxcode[14*32+31:14*32]; rxmask_in = rxmask[14*32+31:14*32]; end
217// 5'h0F: begin rxcode_in = rxcode[15*32+31:15*32]; rxmask_in = rxmask[15*32+31:15*32]; end
218// 5'h10: begin rxcode_in = rxcode[16*32+31:16*32]; rxmask_in = rxmask[16*32+31:16*32]; end
219// 5'h11: begin rxcode_in = rxcode[17*32+31:17*32]; rxmask_in = rxmask[17*32+31:17*32]; end
220// 5'h12: begin rxcode_in = rxcode[18*32+31:18*32]; rxmask_in = rxmask[18*32+31:18*32]; end
221// 5'h13: begin rxcode_in = rxcode[19*32+31:19*32]; rxmask_in = rxmask[19*32+31:19*32]; end
222// 5'h14: begin rxcode_in = rxcode[20*32+31:20*32]; rxmask_in = rxmask[20*32+31:20*32]; end
223// 5'h15: begin rxcode_in = rxcode[21*32+31:21*32]; rxmask_in = rxmask[21*32+31:21*32]; end
224// 5'h16: begin rxcode_in = rxcode[22*32+31:22*32]; rxmask_in = rxmask[22*32+31:22*32]; end
225// 5'h17: begin rxcode_in = rxcode[23*32+31:23*32]; rxmask_in = rxmask[23*32+31:23*32]; end
226// 5'h18: begin rxcode_in = rxcode[24*32+31:24*32]; rxmask_in = rxmask[24*32+31:24*32]; end
227// 5'h19: begin rxcode_in = rxcode[25*32+31:25*32]; rxmask_in = rxmask[25*32+31:25*32]; end
228// 5'h1A: begin rxcode_in = rxcode[26*32+31:26*32]; rxmask_in = rxmask[26*32+31:26*32]; end
229// 5'h1B: begin rxcode_in = rxcode[27*32+31:27*32]; rxmask_in = rxmask[27*32+31:27*32]; end
230// 5'h1C: begin rxcode_in = rxcode[28*32+31:28*32]; rxmask_in = rxmask[28*32+31:28*32]; end
231// 5'h1D: begin rxcode_in = rxcode[29*32+31:29*32]; rxmask_in = rxmask[29*32+31:29*32]; end
232// 5'h1E: begin rxcode_in = rxcode[30*32+31:30*32]; rxmask_in = rxmask[30*32+31:30*32]; end
233// 5'h1F: begin rxcode_in = rxcode[31*32+31:31*32]; rxmask_in = rxmask[31*32+31:31*32]; end
234// endcase
235//end
236
237
238can_acf i_can_acf
239(
240 .clk(clk),
241 .rst(rst),
242
243 .id(id),
244
245 /* Mode register */
246 .reset_mode(1'h0),
247 .acceptance_filter_mode(acceptance_filter_mode),
248
249 // Clock Divider register
250 .extended_mode(extended_mode),
251
252 /* This section is for BASIC and EXTENDED mode */
253 /* Acceptance code register */
254 .acceptance_code_0(rxcode_in[3*8+7:3*8]),
255
256 /* Acceptance mask register */
257 .acceptance_mask_0(rxmask_in[3*8+7:3*8]),
258 /* End: This section is for BASIC and EXTENDED mode */
259
260 /* This section is for EXTENDED mode */
261 /* Acceptance code register */
262 .acceptance_code_1(rxcode_in[2*8+7:2*8]),
263 .acceptance_code_2(rxcode_in[1*8+7:1*8]),
264 .acceptance_code_3(rxcode_in[0*8+7:0*8]),
265
266 /* Acceptance mask register */
267 .acceptance_mask_1(rxmask_in[2*8+7:2*8]),
268 .acceptance_mask_2(rxmask_in[1*8+7:1*8]),
269 .acceptance_mask_3(rxmask_in[0*8+7:0*8]),
270 /* End: This section is for EXTENDED mode */
271
272 .go_rx_crc_lim(1'h1),
273 .go_rx_inter(1'h0),
274 .go_error_frame(1'h0),
275
276 .data0(rx_dt[2*32+0*8+7:2*32+0*8]),
277 .data1(rx_dt[2*32+1*8+7:2*32+1*8]),
278 .rtr1(rx_dt[1*32+4]),
279 .rtr2(rx_dt[1*32+4]),
280 .ide(rx_dt[0*32+31]),
281 .no_byte0(no_byte0),
282 .no_byte1(no_byte1),
283
284 .id_ok(id_ok)
285
286);
287
288generate
289 genvar i;
290
291 for (i=0; i<RXMBOX_BITS; i=i+1) begin :msgbox_afc
292// for (i=0; i<32; i=i+1) begin :msgbox_afc
293
294 assign rx_we_off[i] = rx_we_on[i] & (timovr | ~rxcmp[i]| (rxcmp[i] & ~rxwait[i]));
295
296 if(i==0)
297 begin
298 always @ (posedge clk or posedge rst)
299 begin
300 if(rst) rx_we_on[i] <= 1'h0;
301 else if(id_ok & rx_en[i]) rx_we_on[i] <=#Tp 1'h1;
302 else if(rx_we_off[i]) rx_we_on[i] <=#Tp 1'h0;
303 end
304 end
305 else
306 begin
307 always @ (posedge clk or posedge rst)
308 begin
309 if(rst) rx_we_on[i] <= 1'h0;
310 else if(id_ok & rx_en[i]) rx_we_on[i] <=#Tp 1'h1;
311 else if(rx_we_off[i]) rx_we_on[i] <=#Tp (|rx_we_off[i-1:0])? rx_we_on[i]: 1'h0;
312 end
313 end
314
315 end //for
316
317endgenerate
318
319reg [127:0] rx_dt_ff;
320always @ (posedge clk)
321begin
322 rx_dt_ff <=#Tp (rx_we)? rx_dt: rx_dt_ff;
323 rx_en <=#Tp {rx_en[RXMBOX_BITS-2:0],rx_we};
324// rx_en <=#Tp {rx_en[30:0],rx_we};
325 rx_we_on_q <=#Tp rx_we_on;
326end
327
328always @ (posedge clk or posedge rst)
329begin
330 if(rst) cnt <= 3'h0;
331 else if(rx_en[0]) cnt <=#Tp 3'h1;
332 else if(cnt == 0) cnt <=#Tp 3'h0;
333 else if(~|rx_we_on) cnt <=#Tp 3'h0;
334 else if(sample_point) cnt <=#Tp cnt+3'h1;
335end
336
337assign rx_we_ff = (reset_mode)? {(RXMBOX_BITS-1){1'h0}}: ~rx_we_on & rx_we_on_q;
338//assign rx_we_ff = (reset_mode)? 32'h0: ~rx_we_on & rx_we_on_q;
339
340
341always @ (posedge clk or posedge rst)
342begin
343 if(rst) timovr <= 1'h0;
344 else if(rx_we) timovr <=#Tp 1'h0;
345 else if(~|cnt & sample_point) timovr <=#Tp 1'h1;
346end
347
348reg [127:0] rxdata [0:RXMBOX_BITS-1];
349//reg [127:0] rxdata [0:31];
350reg [4:0] waddr;
351
352function [4:0] match_lower_number;
353 input [RXMBOX_BITS-1:0] x;
354 reg [7:0] i;
355begin
356 match_lower_number = 0;
357 for (i=0; i<RXMBOX_BITS; i=i+1) begin
358 if (x[i] && match_lower_number == 0) begin
359 match_lower_number = i;
360 end
361 end
362end
363endfunction
364
365always @ (*)
366begin
367 waddr = match_lower_number(rx_we_ff);
368end
369
370//always @ (*)
371//begin
372// if(rx_we_ff[00]) waddr = 5'h00;
373// else if(rx_we_ff[01]) waddr = 5'h01;
374// else if(rx_we_ff[02]) waddr = 5'h02;
375// else if(rx_we_ff[03]) waddr = 5'h03;
376// else if(rx_we_ff[04]) waddr = 5'h04;
377// else if(rx_we_ff[05]) waddr = 5'h05;
378// else if(rx_we_ff[06]) waddr = 5'h06;
379// else if(rx_we_ff[07]) waddr = 5'h07;
380// else if(rx_we_ff[08]) waddr = 5'h08;
381// else if(rx_we_ff[09]) waddr = 5'h09;
382// else if(rx_we_ff[10]) waddr = 5'h0A;
383// else if(rx_we_ff[11]) waddr = 5'h0B;
384// else if(rx_we_ff[12]) waddr = 5'h0C;
385// else if(rx_we_ff[13]) waddr = 5'h0D;
386// else if(rx_we_ff[14]) waddr = 5'h0E;
387// else if(rx_we_ff[15]) waddr = 5'h0F;
388// else if(rx_we_ff[16]) waddr = 5'h10;
389// else if(rx_we_ff[17]) waddr = 5'h11;
390// else if(rx_we_ff[18]) waddr = 5'h12;
391// else if(rx_we_ff[19]) waddr = 5'h13;
392// else if(rx_we_ff[20]) waddr = 5'h14;
393// else if(rx_we_ff[21]) waddr = 5'h15;
394// else if(rx_we_ff[22]) waddr = 5'h16;
395// else if(rx_we_ff[23]) waddr = 5'h17;
396// else if(rx_we_ff[24]) waddr = 5'h18;
397// else if(rx_we_ff[25]) waddr = 5'h19;
398// else if(rx_we_ff[26]) waddr = 5'h1A;
399// else if(rx_we_ff[27]) waddr = 5'h1B;
400// else if(rx_we_ff[28]) waddr = 5'h1C;
401// else if(rx_we_ff[29]) waddr = 5'h1D;
402// else if(rx_we_ff[30]) waddr = 5'h1E;
403// else if(rx_we_ff[31]) waddr = 5'h1F;
404// else waddr = 5'h00;
405//end
406
407
408integer j;
409initial begin
410// for(j=0;j<32;j=j+1) rxdata[j]=0;
411 for(j=0;j<RXMBOX_BITS;j=j+1) rxdata[j]=0;
412end
413
414
415always @ (posedge clk)
416begin
417 if(|rx_we_ff) rxdata[waddr] <=#Tp rx_dt_ff;
418 rxmsgdata <=#Tp rxdata[rxdatawin];
419end
420
421
422endmodule
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