source: rc_os_nios2/DE0_Nano_QSYS_DEMO/canc/hdl/can_defines.v@ 128

Last change on this file since 128 was 128, checked in by ertl-honda, 9 years ago

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1//////////////////////////////////////////////////////////////////////
2//// ////
3//// can_defines.v ////
4//// ////
5//// ////
6//// This file is part of the CAN Protocol Controller ////
7//// http://www.opencores.org/projects/can/ ////
8//// ////
9//// ////
10//// Author(s): ////
11//// Igor Mohor ////
12//// igorm@opencores.org ////
13//// ////
14//// ////
15//// All additional information is available in the README.txt ////
16//// file. ////
17//// ////
18//////////////////////////////////////////////////////////////////////
19//// ////
20//// Copyright (C) 2002, 2003, 2004 Authors ////
21//// ////
22//// This source file may be used and distributed without ////
23//// restriction provided that this copyright statement is not ////
24//// removed from the file and that any derivative work contains ////
25//// the original copyright notice and the associated disclaimer. ////
26//// ////
27//// This source file is free software; you can redistribute it ////
28//// and/or modify it under the terms of the GNU Lesser General ////
29//// Public License as published by the Free Software Foundation; ////
30//// either version 2.1 of the License, or (at your option) any ////
31//// later version. ////
32//// ////
33//// This source is distributed in the hope that it will be ////
34//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
35//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
36//// PURPOSE. See the GNU Lesser General Public License for more ////
37//// details. ////
38//// ////
39//// You should have received a copy of the GNU Lesser General ////
40//// Public License along with this source; if not, download it ////
41//// from http://www.opencores.org/lgpl.shtml ////
42//// ////
43//// The CAN protocol is developed by Robert Bosch GmbH and ////
44//// protected by patents. Anybody who wants to implement this ////
45//// CAN IP core on silicon has to obtain a CAN protocol license ////
46//// from Bosch. ////
47//// ////
48//////////////////////////////////////////////////////////////////////
49//
50// CVS Revision History
51//
52// $Log: can_defines.v,v $
53// Revision 1.14 2004/05/12 15:58:41 igorm
54// Core improved to pass all tests with the Bosch VHDL Reference system.
55//
56// Revision 1.13 2004/02/08 14:28:03 mohor
57// Header changed.
58//
59// Revision 1.12 2003/10/17 05:55:20 markom
60// mbist signals updated according to newest convention
61//
62// Revision 1.11 2003/09/05 12:46:42 mohor
63// ALTERA_RAM supported.
64//
65// Revision 1.10 2003/08/14 16:04:52 simons
66// Artisan ram instances added.
67//
68// Revision 1.9 2003/06/27 20:56:15 simons
69// Virtual silicon ram instances added.
70//
71// Revision 1.8 2003/06/09 11:32:36 mohor
72// Ports added for the CAN_BIST.
73//
74// Revision 1.7 2003/03/20 16:51:55 mohor
75// *** empty log message ***
76//
77// Revision 1.6 2003/03/12 04:19:13 mohor
78// 8051 interface added (besides WISHBONE interface). Selection is made in
79// can_defines.v file.
80//
81// Revision 1.5 2003/03/05 15:03:20 mohor
82// Xilinx RAM added.
83//
84// Revision 1.4 2003/03/01 22:52:47 mohor
85// Actel APA ram supported.
86//
87// Revision 1.3 2003/02/09 02:24:33 mohor
88// Bosch license warning added. Error counters finished. Overload frames
89// still need to be fixed.
90//
91// Revision 1.2 2002/12/27 00:12:52 mohor
92// Header changed, testbench improved to send a frame (crc still missing).
93//
94// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
95// Initial
96//
97//
98//
99
100
101// Uncomment following line if you want to use WISHBONE interface. Otherwise
102// 8051 interface is used.
103// `define CAN_WISHBONE_IF
104`define CAN_AVALON_IF
105
106// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
107// `define ACTEL_APA_RAM
108
109// Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
110//`define ALTERA_RAM
111
112// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
113// `define XILINX_RAM
114
115// Uncomment the line for the ram used in ASIC implementation
116// `define VIRTUALSILICON_RAM
117// `define ARTISAN_RAM
118
119// Uncomment the following line when RAM BIST is needed (ASIC implementation)
120//`define CAN_BIST // Bist (for ASIC implementation)
121
122/* width of MBIST control bus */
123//`define CAN_MBIST_CTRL_WIDTH 3
124
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