source: azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_inithook.c@ 453

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1/*
2 * TOPPERS/ASP Kernel
3 * Toyohashi Open Platform for Embedded Real-Time Systems/
4 * Advanced Standard Profile Kernel
5 *
6 * Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
7 * Graduate School of Information Science, Nagoya Univ., JAPAN
8 * Copyright (C) 2015 by 3rd Designing Center
9 * Imageing System Development Division RICOH COMPANY, LTD.
10 * Copyright (C) 2017-2019 by TOPPERS PROJECT Educational Working Group.
11 *
12 * 上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
13 * ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
14 * 変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
15 * (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
16 * 権表示，この利用条件および下記の無保証規定が，そのままの形でソー
17 * スコード中に含まれていること．
18 * (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
19 * 用できる形で再配布する場合には，再配布に伴うドキュメント（利用
20 * 者マニュアルなど）に，上記の著作権表示，この利用条件および下記
21 * の無保証規定を掲載すること．
22 * (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
23 * 用できない形で再配布する場合には，次のいずれかの条件を満たすこ
24 * と．
25 * (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
26 * 作権表示，この利用条件および下記の無保証規定を掲載すること．
27 * (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
28 * 報告すること．
29 * (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
30 * 害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
31 * また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
32 * 由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
33 * 免責すること．
34 *
35 * 本ソフトウェアは，無保証で提供されているものである．上記著作権者お
36 * よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
37 * に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
38 * アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
39 * の責任を負わない．
40 *
41 * @(#) $Id$
42 */
43
44/* Copyright 2018 Canaan Inc.
45 *
46 * Licensed under the Apache License, Version 2.0 (the "License");
47 * you may not use this file except in compliance with the License.
48 * You may obtain a copy of the License at
49 *
50 * http://www.apache.org/licenses/LICENSE-2.0
51 *
52 * Unless required by applicable law or agreed to in writing, software
53 * distributed under the License is distributed on an "AS IS" BASIS,
54 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
55 * See the License for the specific language governing permissions and
56 * limitations under the License.
57 */
58
59#include <string.h>
60#include "kendryte-k210.h"
61#include "target_syssvc.h"
62
63/*
64 * SIL関数のマクロ定義
65 */
66#define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b))
67#define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
68#define sil_modw_mem(a, b, c) sil_wrw_mem((a), (sil_rew_mem(a) & (~b)) | (c))
69
70/*
71 * PLL定義
72 */
73#define SYSCTL_PLL0 0
74#define SYSCTL_PLL1 1
75#define SYSCTL_PLL2 2
76
77/*
78 * 初期化プログラム（K210用）
79 */
80#define FPIOA_TIE_EN 0x01000000
81#define FPIOA_TIE_VAL 0x02000000
82
83
84static const uint32_t function_config[FUNC_MAX] = {
85 (0x00900000+FUNC_JTAG_TCLK),
86 (0x00900000+FUNC_JTAG_TDI),
87 (0x00900000+FUNC_JTAG_TMS),
88 (0x00001f00+FUNC_JTAG_TDO),
89 (0x00b03f00+FUNC_SPI0_D0),
90 (0x00b03f00+FUNC_SPI0_D1),
91 (0x00b03f00+FUNC_SPI0_D2),
92 (0x00b03f00+FUNC_SPI0_D3),
93 (0x00b03f00+FUNC_SPI0_D4),
94 (0x00b03f00+FUNC_SPI0_D5),
95 (0x00b03f00+FUNC_SPI0_D6),
96 (0x00b03f00+FUNC_SPI0_D7),
97 (0x00001f00+FUNC_SPI0_SS0),
98 (0x00001f00+FUNC_SPI0_SS1),
99 (0x00001f00+FUNC_SPI0_SS2),
100 (0x00001f00+FUNC_SPI0_SS3),
101 (0x03900000+FUNC_SPI0_ARB),
102 (0x00001f00+FUNC_SPI0_SCLK),
103 (0x00900000+FUNC_UARTHS_RX),
104 (0x00001f00+FUNC_UARTHS_TX),
105 (0x00900000+FUNC_RESV6),
106 (0x00900000+FUNC_RESV7),
107 (0x00001f00+FUNC_CLK_SPI1),
108 (0x00001f00+FUNC_CLK_I2C1),
109 (0x00901f00+FUNC_GPIOHS0),
110 (0x00901f00+FUNC_GPIOHS1),
111 (0x00901f00+FUNC_GPIOHS2),
112 (0x00901f00+FUNC_GPIOHS3),
113 (0x00901f00+FUNC_GPIOHS4),
114 (0x00901f00+FUNC_GPIOHS5),
115 (0x00901f00+FUNC_GPIOHS6),
116 (0x00901f00+FUNC_GPIOHS7),
117
118 (0x00901f00+FUNC_GPIOHS8),
119 (0x00901f00+FUNC_GPIOHS9),
120 (0x00901f00+FUNC_GPIOHS10),
121 (0x00901f00+FUNC_GPIOHS11),
122 (0x00901f00+FUNC_GPIOHS12),
123 (0x00901f00+FUNC_GPIOHS13),
124 (0x00901f00+FUNC_GPIOHS14),
125 (0x00901f00+FUNC_GPIOHS15),
126 (0x00901f00+FUNC_GPIOHS16),
127 (0x00901f00+FUNC_GPIOHS17),
128 (0x00901f00+FUNC_GPIOHS18),
129 (0x00901f00+FUNC_GPIOHS19),
130 (0x00901f00+FUNC_GPIOHS20),
131 (0x00901f00+FUNC_GPIOHS21),
132 (0x00901f00+FUNC_GPIOHS22),
133 (0x00901f00+FUNC_GPIOHS23),
134 (0x00901f00+FUNC_GPIOHS24),
135 (0x00901f00+FUNC_GPIOHS25),
136 (0x00901f00+FUNC_GPIOHS26),
137 (0x00901f00+FUNC_GPIOHS27),
138 (0x00901f00+FUNC_GPIOHS28),
139 (0x00901f00+FUNC_GPIOHS29),
140 (0x00901f00+FUNC_GPIOHS30),
141 (0x00901f00+FUNC_GPIOHS31),
142 (0x00901f00+FUNC_GPIO0),
143 (0x00901f00+FUNC_GPIO1),
144 (0x00901f00+FUNC_GPIO2),
145 (0x00901f00+FUNC_GPIO3),
146 (0x00901f00+FUNC_GPIO4),
147 (0x00901f00+FUNC_GPIO5),
148 (0x00901f00+FUNC_GPIO6),
149 (0x00901f00+FUNC_GPIO7),
150
151 (0x00900000+FUNC_UART1_RX),
152 (0x00001f00+FUNC_UART1_TX),
153 (0x00900000+FUNC_UART2_RX),
154 (0x00001f00+FUNC_UART2_TX),
155 (0x00900000+FUNC_UART3_RX),
156 (0x00001f00+FUNC_UART3_TX),
157 (0x00b03f00+FUNC_SPI1_D0),
158 (0x00b03f00+FUNC_SPI1_D1),
159 (0x00b03f00+FUNC_SPI1_D2),
160 (0x00b03f00+FUNC_SPI1_D3),
161 (0x00b03f00+FUNC_SPI1_D4),
162 (0x00b03f00+FUNC_SPI1_D5),
163 (0x00b03f00+FUNC_SPI1_D6),
164 (0x00b03f00+FUNC_SPI1_D7),
165 (0x00001f00+FUNC_SPI1_SS0),
166 (0x00001f00+FUNC_SPI1_SS1),
167 (0x00001f00+FUNC_SPI1_SS2),
168 (0x00001f00+FUNC_SPI1_SS3),
169 (0x03900000+FUNC_SPI1_ARB),
170 (0x00001f00+FUNC_SPI1_SCLK),
171 (0x00b03f00+FUNC_SPI_SLAVE_D0),
172 (0x00900000+FUNC_SPI_SLAVE_SS),
173 (0x00900000+FUNC_SPI_SLAVE_SCLK),
174 (0x00001f00+FUNC_I2S0_MCLK),
175 (0x00001f00+FUNC_I2S0_SCLK),
176 (0x00001f00+FUNC_I2S0_WS),
177 (0x00900000+FUNC_I2S0_IN_D0),
178 (0x00900000+FUNC_I2S0_IN_D1),
179 (0x00900000+FUNC_I2S0_IN_D2),
180 (0x00900000+FUNC_I2S0_IN_D3),
181 (0x00001f00+FUNC_I2S0_OUT_D0),
182 (0x00001f00+FUNC_I2S0_OUT_D1),
183
184 (0x00001f00+FUNC_I2S0_OUT_D2),
185 (0x00001f00+FUNC_I2S0_OUT_D3),
186 (0x00001f00+FUNC_I2S1_MCLK),
187 (0x00001f00+FUNC_I2S1_SCLK),
188 (0x00001f00+FUNC_I2S1_WS),
189 (0x00900000+FUNC_I2S1_IN_D0),
190 (0x00900000+FUNC_I2S1_IN_D1),
191 (0x00900000+FUNC_I2S1_IN_D2),
192 (0x00900000+FUNC_I2S1_IN_D3),
193 (0x00001f00+FUNC_I2S1_OUT_D0),
194 (0x00001f00+FUNC_I2S1_OUT_D1),
195 (0x00001f00+FUNC_I2S1_OUT_D2),
196 (0x00001f00+FUNC_I2S1_OUT_D3),
197 (0x00001f00+FUNC_I2S2_MCLK),
198 (0x00001f00+FUNC_I2S2_SCLK),
199 (0x00001f00+FUNC_I2S2_WS),
200 (0x00900000+FUNC_I2S2_IN_D0),
201 (0x00900000+FUNC_I2S2_IN_D1),
202 (0x00900000+FUNC_I2S2_IN_D2),
203 (0x00900000+FUNC_I2S2_IN_D3),
204 (0x00001f00+FUNC_I2S2_OUT_D0),
205 (0x00001f00+FUNC_I2S2_OUT_D1),
206 (0x00001f00+FUNC_I2S2_OUT_D2),
207 (0x00001f00+FUNC_I2S2_OUT_D3),
208 (0x00000000+FUNC_RESV0),
209 (0x00000000+FUNC_RESV1),
210 (0x00000000+FUNC_RESV2),
211 (0x00000000+FUNC_RESV3),
212 (0x00000000+FUNC_RESV4),
213 (0x00000000+FUNC_RESV5),
214 (0x00991000+FUNC_I2C0_SCLK),
215 (0x00991000+FUNC_I2C0_SDA),
216
217 (0x00991000+FUNC_I2C1_SCLK),
218 (0x00991000+FUNC_I2C1_SDA),
219 (0x00991000+FUNC_I2C2_SCLK),
220 (0x00991000+FUNC_I2C2_SDA),
221 (0x00001f00+FUNC_CMOS_XCLK),
222 (0x00001f00+FUNC_CMOS_RST),
223 (0x00001f00+FUNC_CMOS_PWDN),
224 (0x00900000+FUNC_CMOS_VSYNC),
225 (0x00900000+FUNC_CMOS_HREF),
226 (0x00900000+FUNC_CMOS_PCLK),
227 (0x00900000+FUNC_CMOS_D0),
228 (0x00900000+FUNC_CMOS_D1),
229 (0x00900000+FUNC_CMOS_D2),
230 (0x00900000+FUNC_CMOS_D3),
231 (0x00900000+FUNC_CMOS_D4),
232 (0x00900000+FUNC_CMOS_D5),
233 (0x00900000+FUNC_CMOS_D6),
234 (0x00900000+FUNC_CMOS_D7),
235 (0x00993000+FUNC_SCCB_SCLK),
236 (0x00993000+FUNC_SCCB_SDA),
237 (0x00900000+FUNC_UART1_CTS),
238 (0x00900000+FUNC_UART1_DSR),
239 (0x00900000+FUNC_UART1_DCD),
240 (0x00900000+FUNC_UART1_RI),
241 (0x00900000+FUNC_UART1_SIR_IN),
242 (0x00001f00+FUNC_UART1_DTR),
243 (0x00001f00+FUNC_UART1_RTS),
244 (0x00001f00+FUNC_UART1_OUT2),
245 (0x00001f00+FUNC_UART1_OUT1),
246 (0x00001f00+FUNC_UART1_SIR_OUT),
247 (0x00001f00+FUNC_UART1_BAUD),
248 (0x00001f00+FUNC_UART1_RE),
249
250 (0x00001f00+FUNC_UART1_DE),
251 (0x00001f00+FUNC_UART1_RS485_EN),
252 (0x00900000+FUNC_UART2_CTS),
253 (0x00900000+FUNC_UART2_DSR),
254 (0x00900000+FUNC_UART2_DCD),
255 (0x00900000+FUNC_UART2_RI),
256 (0x00900000+FUNC_UART2_SIR_IN),
257 (0x00001f00+FUNC_UART2_DTR),
258 (0x00001f00+FUNC_UART2_RTS),
259 (0x00001f00+FUNC_UART2_OUT2),
260 (0x00001f00+FUNC_UART2_OUT1),
261 (0x00001f00+FUNC_UART2_SIR_OUT),
262 (0x00001f00+FUNC_UART2_BAUD),
263 (0x00001f00+FUNC_UART2_RE),
264 (0x00001f00+FUNC_UART2_DE),
265 (0x00001f00+FUNC_UART2_RS485_EN),
266 (0x00900000+FUNC_UART3_CTS),
267 (0x00900000+FUNC_UART3_DSR),
268 (0x00900000+FUNC_UART3_DCD),
269 (0x00900000+FUNC_UART3_RI),
270 (0x00900000+FUNC_UART3_SIR_IN),
271 (0x00001f00+FUNC_UART3_DTR),
272 (0x00001f00+FUNC_UART3_RTS),
273 (0x00001f00+FUNC_UART3_OUT2),
274 (0x00001f00+FUNC_UART3_OUT1),
275 (0x00001f00+FUNC_UART3_SIR_OUT),
276 (0x00001f00+FUNC_UART3_BAUD),
277 (0x00001f00+FUNC_UART3_RE),
278 (0x00001f00+FUNC_UART3_DE),
279 (0x00001f00+FUNC_UART3_RS485_EN),
280 (0x00001f00+FUNC_TIMER0_TOGGLE1),
281 (0x00001f00+FUNC_TIMER0_TOGGLE2),
282
283 (0x00001f00+FUNC_TIMER0_TOGGLE3),
284 (0x00001f00+FUNC_TIMER0_TOGGLE4),
285 (0x00001f00+FUNC_TIMER1_TOGGLE1),
286 (0x00001f00+FUNC_TIMER1_TOGGLE2),
287 (0x00001f00+FUNC_TIMER1_TOGGLE3),
288 (0x00001f00+FUNC_TIMER1_TOGGLE4),
289 (0x00001f00+FUNC_TIMER2_TOGGLE1),
290 (0x00001f00+FUNC_TIMER2_TOGGLE2),
291 (0x00001f00+FUNC_TIMER2_TOGGLE3),
292 (0x00001f00+FUNC_TIMER2_TOGGLE4),
293 (0x00001f00+FUNC_CLK_SPI2),
294 (0x00001f00+FUNC_CLK_I2C2),
295 (0x00001f00+FUNC_INTERNAL0),
296 (0x00001f00+FUNC_INTERNAL1),
297 (0x00001f00+FUNC_INTERNAL2),
298 (0x00001f00+FUNC_INTERNAL3),
299 (0x00001f00+FUNC_INTERNAL4),
300 (0x00001f00+FUNC_INTERNAL5),
301 (0x00001f00+FUNC_INTERNAL6),
302 (0x00001f00+FUNC_INTERNAL7),
303 (0x00001f00+FUNC_INTERNAL8),
304 (0x00900000+FUNC_INTERNAL9),
305 (0x00900000+FUNC_INTERNAL10),
306 (0x00900000+FUNC_INTERNAL11),
307 (0x00900000+FUNC_INTERNAL12),
308 (0x00910000+FUNC_INTERNAL13),
309 (0x00991f00+FUNC_INTERNAL14),
310 (0x00900000+FUNC_INTERNAL15),
311 (0x00900000+FUNC_INTERNAL16),
312 (0x00900000+FUNC_INTERNAL17),
313 (0x00000000+FUNC_CONSTANT),
314 (0x00900000+FUNC_INTERNAL18),
315
316 (0x00001f00+FUNC_DEBUG0),
317 (0x00001f00+FUNC_DEBUG1),
318 (0x00001f00+FUNC_DEBUG2),
319 (0x00001f00+FUNC_DEBUG3),
320 (0x00001f00+FUNC_DEBUG4),
321 (0x00001f00+FUNC_DEBUG5),
322 (0x00001f00+FUNC_DEBUG6),
323 (0x00001f00+FUNC_DEBUG7),
324 (0x00001f00+FUNC_DEBUG8),
325 (0x00001f00+FUNC_DEBUG9),
326 (0x00001f00+FUNC_DEBUG10),
327 (0x00001f00+FUNC_DEBUG11),
328 (0x00001f00+FUNC_DEBUG12),
329 (0x00001f00+FUNC_DEBUG13),
330 (0x00001f00+FUNC_DEBUG14),
331 (0x00001f00+FUNC_DEBUG15),
332 (0x00001f00+FUNC_DEBUG16),
333 (0x00001f00+FUNC_DEBUG17),
334 (0x00001f00+FUNC_DEBUG18),
335 (0x00001f00+FUNC_DEBUG19),
336 (0x00001f00+FUNC_DEBUG20),
337 (0x00001f00+FUNC_DEBUG21),
338 (0x00001f00+FUNC_DEBUG22),
339 (0x00001f00+FUNC_DEBUG23),
340 (0x00001f00+FUNC_DEBUG24),
341 (0x00001f00+FUNC_DEBUG25),
342 (0x00001f00+FUNC_DEBUG26),
343 (0x00001f00+FUNC_DEBUG27),
344 (0x00001f00+FUNC_DEBUG28),
345 (0x00001f00+FUNC_DEBUG29),
346 (0x00001f00+FUNC_DEBUG30),
347 (0x00001f00+FUNC_DEBUG31),
348};
349
350static const uint8_t pll_table[3][4] = {
351 {1, 62, 2, 62}, /* PLL 0 */
352 {1, 46, 4, 46}, /* PLL 1 */
353 {1, 26, 15, 26}, /* PLL 0 */
354};
355
356/*
357 * FPIOA初期化
358 */
359static ER
360fpioa_init(void)
361{
362 int i = 0;
363 uint32_t en[FUNC_MAX / 32];
364 uint32_t val[FUNC_MAX / 32];
365
366 /* Enable fpioa clock in system controller */
367 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB0_CLK_EN);
368 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), SYSCTL_CLK_EN_PERI_FPIOA_CLK_EN);
369
370 /* Initialize tie */
371 memset(en, 0, FUNC_MAX/8);
372 memset(val, 0, FUNC_MAX/8);
373
374 /* Set tie enable and tie value */
375 for(i = 0; i < FUNC_MAX; i++){
376 if((function_config[i] & FPIOA_TIE_EN) != 0)
377 en[i / 32] |= 1 << (i % 32);
378 if((function_config[i] & FPIOA_TIE_VAL) != 0)
379 val[i / 32] |= 1 << (i % 32);
380 }
381
382 /* Atomic write every 32bit register to fpioa function */
383 for(i = 0; i < FUNC_MAX / 32; i++){
384 /* Set value before enable */
385 sil_wrw_mem((uint32_t *)(TADR_FPIOA_BASE+TOFF_FPIOA_TIE_EN+i*4), en[i]);
386 sil_wrw_mem((uint32_t *)(TADR_FPIOA_BASE+TOFF_FPIOA_TIE_VAL+i*4), val[i]);
387 }
388 return E_OK;
389}
390
391/*
392 * FPIOAハードウェア設定
393 */
394static ER
395fpioa_set_function_raw(int number, uint8_t function)
396{
397 uint32_t *p = (uint32_t *)&function_config[function];
398 uint32_t off = TOFF_FPIOA_IO + number * sizeof(uint32_t);
399
400 /* Check parameters */
401 if(number < 0 || number >= FPIOA_NUM_IO || function >= FUNC_MAX)
402 return E_PAR;
403 sil_modw_mem((uint32_t *)(TADR_FPIOA_BASE+off), 0x00FFFFFF, (*p & 0x00FFFFFF));
404 return E_OK;
405}
406
407/*
408 * FPIOAにファンクションを設定する
409 * param1 number The IO number
410 * param2 function The function enum number
411 * return 0-OK
412 */
413ER
414fpioa_set_function(int number, uint8_t function)
415{
416 uint8_t i = 0;
417 /* Check parameters */
418 if(number < 0 || number >= FPIOA_NUM_IO || function >= FUNC_MAX)
419 return E_PAR;
420 if(function == FUNC_RESV0){
421 return fpioa_set_function_raw(number, FUNC_RESV0);
422 }
423 /* Compare all IO */
424 for(i = 0 ; i < FPIOA_NUM_IO ; i++){
425 if(((sil_rew_mem((uint32_t *)(TADR_FPIOA_BASE+TOFF_FPIOA_IO+i*4)) & FPIOA_CH_SEL) == function) && (i != number))
426 fpioa_set_function_raw(i, FUNC_RESV0);
427 }
428 return fpioa_set_function_raw(number, function);
429}
430
431/*
432 * PLLクロック取得
433 */
434uint32_t
435get_pll_clock(uint8_t no)
436{
437 uint32_t pll, freq_in = 0, freq_out = 0;
438 uint32_t nr = 0, nf = 0, od = 0;
439 uint32_t select = 0;
440
441 switch(no){
442 case 0: /* PLL0 */
443 pll = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_PLL0));
444 freq_in = SYSCTRL_CLOCK_FREQ_IN0;
445 nr = (pll & SYSCTL_PLL_CLKR0) + 1;
446 nf = ((pll & SYSCTL_PLL_CLKF0) >> 4) + 1;
447 od = ((pll & SYSCTL_PLL_CLKOD0) >> 10) + 1;
448 break;
449 case 1: /* PLL1 */
450 pll = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_PLL1));
451 freq_in = SYSCTRL_CLOCK_FREQ_IN0;
452 nr = (pll & SYSCTL_PLL_CLKR1) + 1;
453 nf = ((pll & SYSCTL_PLL_CLKF1) >> 4) + 1;
454 od = ((pll & SYSCTL_PLL_CLKOD1) >> 10) + 1;
455 break;
456 case 2: /* PLL2 */
457 pll = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_PLL2));
458 select = (pll & SYSCTL_PLL_CKIN_SEL2) >> 26;
459 if(select == 0)
460 freq_in = SYSCTRL_CLOCK_FREQ_IN0;
461 else if(select == 1)
462 freq_in = get_pll_clock(0);
463 else if(select == 2)
464 freq_in = get_pll_clock(1);
465 nr = (pll & SYSCTL_PLL_CLKR2) + 1;
466 nf = ((pll & SYSCTL_PLL_CLKF2) >> 4) + 1;
467 od = ((pll & SYSCTL_PLL_CLKOD2) >> 10) + 1;
468 break;
469 default:
470 break;
471 }
472 freq_out = (uint64_t)freq_in * nf / nr / od;
473 return freq_out;
474}
475
476/*
477 * PLLロック判定
478 */
479static int
480pll_is_lock(uint8_t pll)
481{
482 uint32_t pll_lock = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_PLL_LOCK));
483 if(pll == SYSCTL_PLL0)
484 return (pll_lock & SYSCTL_PLL_LOCK_LOCK0) == 3;
485 else if(pll == SYSCTL_PLL1)
486 return (pll_lock >> 8) & 1;
487 else if(pll == SYSCTL_PLL2)
488 return (pll_lock >> 16) & 1;
489 else
490 return 0;
491}
492
493/*
494 * PLL設定
495 */
496static uint32_t
497pll_set_freq(uint8_t pll, const uint8_t *conf)
498{
499 unsigned long base = TADR_SYSCTL_BASE;
500 uint32_t voff = TOFF_SYSCTL_PLL0;
501 uint32_t pll_value;
502
503 switch(pll){
504 case SYSCTL_PLL0:
505 voff = TOFF_SYSCTL_PLL0;
506 break;
507 case SYSCTL_PLL1:
508 voff = TOFF_SYSCTL_PLL1;
509 break;
510 case SYSCTL_PLL2:
511 voff = TOFF_SYSCTL_PLL2;
512 break;
513 default:
514 return 0;
515 break;
516 }
517
518 /*
519 * PLL0設定ならば、ACLKをINOに変更
520 */
521 if(pll == SYSCTL_PLL0)
522 sil_modw_mem((uint32_t *)(base+TOFF_CLK_SEL0), SYSCTL_CLK_SEL0_ACLK_SEL, SYSCTL_CLK_SEL0_SOURCE_IN0);
523
524 /*
525 * PLL出力停止
526 */
527 sil_andw_mem((uint32_t *)(base+voff), SYSCTL_PLL_OUT_EN0);
528
529 /*
530 * PLLパワーオフ
531 */
532 sil_andw_mem((uint32_t *)(base+voff), SYSCTL_PLL_PWRD0);
533
534 /*
535 * PLL設定変更
536 */
537 pll_value = sil_rew_mem((uint32_t *)(base+TOFF_SYSCTL_PLL0+pll*4));
538 if(pll == SYSCTL_PLL2){
539 pll_value &= SYSCTL_PLL_CKIN_SEL2;
540 pll_value |= SYSCTL_CLK_SEL0_SOURCE_IN0 << 22;
541 }
542 pll_value &= ~(SYSCTL_PLL_CLKR0 | SYSCTL_PLL_CLKF0 | SYSCTL_PLL_CLKOD0 | SYSCTL_PLL_BWADJ0);
543 pll_value |= conf[0] - 1;
544 pll_value |= (conf[1] - 1) << 4;
545 pll_value |= (conf[2] - 1) << 10;
546 pll_value |= (conf[3] - 1) << 14;
547 sil_wrw_mem((uint32_t *)(base+TOFF_SYSCTL_PLL0+pll*4), pll_value);
548
549 /*
550 * PLLパワーオン
551 */
552 sil_orw_mem((uint32_t *)(base+voff), SYSCTL_PLL_PWRD0);
553 sil_dly_nse(1000);
554
555 /*
556 * PLLリセット
557 */
558 sil_andw_mem((uint32_t *)(base+voff), SYSCTL_PLL_RESET0);
559 sil_orw_mem((uint32_t *)(base+voff), SYSCTL_PLL_RESET0);
560 sil_dly_nse(1000);
561 sil_andw_mem((uint32_t *)(base+voff), SYSCTL_PLL_RESET0);
562
563 /*
564 * PLLロック解除
565 */
566 while (pll_is_lock(pll) == 0){
567 sil_orw_mem((uint32_t *)(base+TOFF_SYSCTL_PLL_LOCK), (SYSCTL_PLL_LOCK_SLIP_CLEAR0 << (pll*8)));
568 }
569
570 /*
571 * PLL出力開始
572 */
573 sil_orw_mem((uint32_t *)(base+voff), SYSCTL_PLL_OUT_EN0);
574
575 /*
576 * PLL0設定ならば、ACLKをPLL0に変更
577 */
578 if(pll == SYSCTL_PLL0)
579 sil_modw_mem((uint32_t *)(base+TOFF_CLK_SEL0), SYSCTL_CLK_SEL0_ACLK_SEL, SYSCTL_CLK_SEL0_SOURCE_PLL0);
580
581 return get_pll_clock(pll);
582}
583
584
585/*
586 * 低レベルのターゲット依存の初期化
587 *
588 * スタートアップモジュールの中で，メモリの初期化の前に呼び出される．
589 */
590void hardware_init_hook(void)
591{
592 /*
593 * PLL設定
594 */
595 pll_set_freq(SYSCTL_PLL0, &pll_table[SYSCTL_PLL0][0]); /* 800000000 */
596 pll_set_freq(SYSCTL_PLL1, &pll_table[SYSCTL_PLL1][0]); /* 300000000 */
597 pll_set_freq(SYSCTL_PLL2, &pll_table[SYSCTL_PLL2][0]); /* 45158400 */
598
599 /*
600 * BANK6,7を1.8Vに設定
601 */
602 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_POWER_SEL),
603 SYSCTL_POWER_SEL_POWER_MODE_6);
604 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_POWER_SEL),
605 SYSCTL_POWER_SEL_POWER_MODE_7);
606 /* Init FPIOA */
607 fpioa_init();
608 /*
609 * SYSCTLステータスをリセット
610 */
611 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_RST_STATUS),
612 SYSCTL_RST_STATUS_RESET_STS_CLR);
613}
614
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