1 | /*
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2 | * This file is part of the OpenMV project.
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3 | * Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
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4 | * This work is licensed under the MIT license, see the file LICENSE for details.
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5 | *
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6 | * OV2640 register definitions.
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7 | */
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8 |
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9 | #ifndef __REG_REGS_H__
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10 | #define __REG_REGS_H__
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11 |
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12 | /* DSP register bank FF=0x00*/
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13 |
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14 | #define QS 0x44
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15 | #define HSIZE 0x51
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16 | #define VSIZE 0x52
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17 | #define XOFFL 0x53
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18 | #define YOFFL 0x54
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19 | #define VHYX 0x55
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20 | #define DPRP 0x56
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21 | #define TEST 0x57
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22 | #define ZMOW 0x5A
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23 | #define ZMOH 0x5B
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24 | #define ZMHH 0x5C
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25 | #define BPADDR 0x7C
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26 | #define BPDATA 0x7D
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27 | #define SIZEL 0x8C
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28 | #define HSIZE8 0xC0
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29 | #define VSIZE8 0xC1
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30 | #define CTRL1 0xC3
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31 | #define MS_SP 0xF0
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32 | #define SS_ID 0xF7
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33 | #define SS_CTRL 0xF7
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34 | #define MC_AL 0xFA
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35 | #define MC_AH 0xFB
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36 | #define MC_D 0xFC
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37 | #define P_CMD 0xFD
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38 | #define P_STATUS 0xFE
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39 |
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40 | #define CTRLI 0x50
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41 | #define CTRLI_LP_DP 0x80
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42 | #define CTRLI_ROUND 0x40
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43 |
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44 | #define CTRL0 0xC2
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45 | #define CTRL0_AEC_EN 0x80
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46 | #define CTRL0_AEC_SEL 0x40
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47 | #define CTRL0_STAT_SEL 0x20
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48 | #define CTRL0_VFIRST 0x10
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49 | #define CTRL0_YUV422 0x08
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50 | #define CTRL0_YUV_EN 0x04
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51 | #define CTRL0_RGB_EN 0x02
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52 | #define CTRL0_RAW_EN 0x01
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53 |
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54 | #define CTRL2 0x86
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55 | #define CTRL2_DCW_EN 0x20
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56 | #define CTRL2_SDE_EN 0x10
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57 | #define CTRL2_UV_ADJ_EN 0x08
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58 | #define CTRL2_UV_AVG_EN 0x04
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59 | #define CTRL2_CMX_EN 0x01
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60 |
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61 | #define CTRL3 0x87
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62 | #define CTRL3_BPC_EN 0x80
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63 | #define CTRL3_WPC_EN 0x40
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64 | #define R_DVP_SP 0xD3
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65 | #define R_DVP_SP_AUTO_MODE 0x80
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66 |
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67 | #define R_BYPASS 0x05
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68 | #define R_BYPASS_DSP_EN 0x00
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69 | #define R_BYPASS_DSP_BYPAS 0x01
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70 |
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71 | #define IMAGE_MODE 0xDA
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72 | #define IMAGE_MODE_Y8_DVP_EN 0x40
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73 | #define IMAGE_MODE_JPEG_EN 0x10
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74 | #define IMAGE_MODE_YUV422 0x00
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75 | #define IMAGE_MODE_RAW10 0x04
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76 | #define IMAGE_MODE_RGB565 0x08
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77 | #define IMAGE_MODE_HREF_VSYNC 0x02
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78 | #define IMAGE_MODE_LBYTE_FIRST 0x01
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79 | #define IMAGE_MODE_GET_FMT(x) ((x)&0xC)
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80 |
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81 | #define RESET 0xE0
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82 | #define RESET_MICROC 0x40
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83 | #define RESET_SCCB 0x20
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84 | #define RESET_JPEG 0x10
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85 | #define RESET_DVP 0x04
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86 | #define RESET_IPU 0x02
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87 | #define RESET_CIF 0x01
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88 |
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89 | #define MC_BIST 0xF9
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90 | #define MC_BIST_RESET 0x80
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91 | #define MC_BIST_BOOT_ROM_SEL 0x40
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92 | #define MC_BIST_12KB_SEL 0x20
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93 | #define MC_BIST_12KB_MASK 0x30
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94 | #define MC_BIST_512KB_SEL 0x08
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95 | #define MC_BIST_512KB_MASK 0x0C
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96 | #define MC_BIST_BUSY_BIT_R 0x02
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97 | #define MC_BIST_MC_RES_ONE_SH_W 0x02
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98 | #define MC_BIST_LAUNCH 0x01
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99 |
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100 | #define BANK_SEL 0xFF
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101 | #define BANK_SEL_DSP 0x00
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102 | #define BANK_SEL_SENSOR 0x01
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103 |
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104 | /* Sensor register bank FF=0x01*/
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105 |
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106 | #define GAIN 0x00
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107 | #define COM1 0x03
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108 | #define REG_PID 0x0A
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109 | #define REG_VER 0x0B
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110 | #define COM4 0x0D
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111 | #define AEC 0x10
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112 |
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113 | #define CLKRC 0x11
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114 | #define CLKRC_DOUBLE 0x80
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115 | #define CLKRC_DIVIDER_MASK 0x3F
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116 |
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117 | #define COM10 0x15
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118 | #define HSTART 0x17
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119 | #define HSTOP 0x18
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120 | #define VSTART 0x19
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121 | #define VSTOP 0x1A
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122 | #define MIDH 0x1C
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123 | #define MIDL 0x1D
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124 | #define AEW 0x24
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125 | #define AEB 0x25
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126 | #define REG2A 0x2A
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127 | #define FRARL 0x2B
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128 | #define ADDVSL 0x2D
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129 | #define ADDVSH 0x2E
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130 | #define YAVG 0x2F
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131 | #define HSDY 0x30
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132 | #define HEDY 0x31
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133 | #define ARCOM2 0x34
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134 | #define REG45 0x45
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135 | #define FLL 0x46
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136 | #define FLH 0x47
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137 | #define COM19 0x48
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138 | #define ZOOMS 0x49
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139 | #define COM22 0x4B
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140 | #define COM25 0x4E
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141 | #define BD50 0x4F
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142 | #define BD60 0x50
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143 | #define REG5D 0x5D
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144 | #define REG5E 0x5E
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145 | #define REG5F 0x5F
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146 | #define REG60 0x60
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147 | #define HISTO_LOW 0x61
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148 | #define HISTO_HIGH 0x62
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149 |
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150 | #define REG04 0x04
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151 | #define REG04_DEFAULT 0x28
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152 | #define REG04_HFLIP_IMG 0x80
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153 | #define REG04_VFLIP_IMG 0x40
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154 | #define REG04_VREF_EN 0x10
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155 | #define REG04_HREF_EN 0x08
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156 | #define REG04_SET(x) (REG04_DEFAULT|x)
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157 |
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158 | #define REG08 0x08
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159 | #define COM2 0x09
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160 | #define COM2_STDBY 0x10
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161 | #define COM2_OUT_DRIVE_1x 0x00
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162 | #define COM2_OUT_DRIVE_2x 0x01
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163 | #define COM2_OUT_DRIVE_3x 0x02
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164 | #define COM2_OUT_DRIVE_4x 0x03
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165 |
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166 | #define COM3 0x0C
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167 | #define COM3_DEFAULT 0x38
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168 | #define COM3_BAND_50Hz 0x04
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169 | #define COM3_BAND_60Hz 0x00
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170 | #define COM3_BAND_AUTO 0x02
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171 | #define COM3_BAND_SET(x) (COM3_DEFAULT|x)
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172 |
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173 | #define COM7 0x12
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174 | #define COM7_SRST 0x80
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175 | #define COM7_RES_UXGA 0x00 /* UXGA */
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176 | #define COM7_RES_SVGA 0x40 /* SVGA */
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177 | #define COM7_RES_CIF 0x20 /* CIF */
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178 | #define COM7_ZOOM_EN 0x04 /* Enable Zoom */
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179 | #define COM7_COLOR_BAR 0x02 /* Enable Color Bar Test */
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180 | #define COM7_GET_RES(x) ((x)&0x70)
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181 |
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182 | #define COM8 0x13
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183 | #define COM8_DEFAULT 0xC0
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184 | #define COM8_BNDF_EN 0x20 /* Enable Banding filter */
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185 | #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
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186 | #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
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187 | #define COM8_SET(x) (COM8_DEFAULT|x)
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188 | #define COM8_SET_AEC(r,x) (((r)&0xFE)|((x)&1))
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189 |
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190 | #define COM9 0x14 /* AGC gain ceiling */
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191 | #define COM9_DEFAULT 0x08
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192 | #define COM9_AGC_GAIN_2x 0x00 /* AGC: 2x */
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193 | #define COM9_AGC_GAIN_4x 0x01 /* AGC: 4x */
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194 | #define COM9_AGC_GAIN_8x 0x02 /* AGC: 8x */
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195 | #define COM9_AGC_GAIN_16x 0x03 /* AGC: 16x */
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196 | #define COM9_AGC_GAIN_32x 0x04 /* AGC: 32x */
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197 | #define COM9_AGC_GAIN_64x 0x05 /* AGC: 64x */
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198 | #define COM9_AGC_GAIN_128x 0x06 /* AGC: 128x */
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199 | #define COM9_AGC_SET(x) (COM9_DEFAULT|(x<<5))
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200 |
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201 | #define CTRL1_AWB 0x08 /* Enable AWB */
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202 |
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203 | #define VV 0x26
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204 | #define VV_AGC_TH_SET(h,l) ((h<<4)|(l&0x0F))
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205 |
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206 | #define REG32 0x32
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207 | #define REG32_UXGA 0x36
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208 | #define REG32_SVGA 0x09
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209 | #define REG32_CIF 0x00
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210 |
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211 | #endif //__REG_REGS_H__
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212 |
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