| 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | * Copyright (C) 2017-2019 by TOPPERS PROJECT Educational Working Group.
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| 9 | *
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| 10 | * 上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
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| 11 | * ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
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| 12 | * 変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
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| 13 | * (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
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| 14 | * 権表示，この利用条件および下記の無保証規定が，そのままの形でソー
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| 15 | * スコード中に含まれていること．
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| 16 | * (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
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| 17 | * 用できる形で再配布する場合には，再配布に伴うドキュメント（利用
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| 18 | * 者マニュアルなど）に，上記の著作権表示，この利用条件および下記
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| 19 | * の無保証規定を掲載すること．
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| 20 | * (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
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| 21 | * 用できない形で再配布する場合には，次のいずれかの条件を満たすこ
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| 22 | * と．
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| 23 | * (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
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| 24 | * 作権表示，この利用条件および下記の無保証規定を掲載すること．
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| 25 | * (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
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| 26 | * 報告すること．
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| 27 | * (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
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| 28 | * 害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
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| 29 | * また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
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| 30 | * 由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
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| 31 | * 免責すること．
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| 32 | *
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| 33 | * 本ソフトウェアは，無保証で提供されているものである．上記著作権者お
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| 34 | * よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
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| 35 | * に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
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| 36 | * アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
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| 37 | * の責任を負わない．
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| 38 | *
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| 39 | * @(#) $Id$
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| 40 | */
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| 41 |
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| 42 | /*
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| 43 | * Copyright 2016 SiFive, Inc.
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| 44 | *
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| 45 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 46 | * you may not use this file except in compliance with the License.
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| 47 | * You may obtain a copy of the License at
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| 48 | *
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| 49 | * http://www.apache.org/licenses/LICENSE-2.0
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| 50 | *
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| 51 | * Unless required by applicable law or agreed to in writing, software
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| 52 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 53 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 54 | * See the License for the specific language governing permissions and
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| 55 | * limitations under the License.
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| 56 | */
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| 57 | /* Copyright 2018 Canaan Inc.
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| 58 | *
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| 59 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 60 | * you may not use this file except in compliance with the License.
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| 61 | * You may obtain a copy of the License at
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| 62 | *
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| 63 | * http://www.apache.org/licenses/LICENSE-2.0
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| 64 | *
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| 65 | * Unless required by applicable law or agreed to in writing, software
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| 66 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 67 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 68 | * See the License for the specific language governing permissions and
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| 69 | * limitations under the License.
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| 70 | */
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| 71 |
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| 72 | #ifndef RISCV_CSR_ENCODING_H
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| 73 | #define RISCV_CSR_ENCODING_H
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| 74 |
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| 75 | #define MSTATUS_UIE 0x00000001
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| 76 | #define MSTATUS_SIE 0x00000002
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| 77 | #define MSTATUS_HIE 0x00000004
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| 78 | #define MSTATUS_MIE 0x00000008
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| 79 | #define MSTATUS_UPIE 0x00000010
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| 80 | #define MSTATUS_SPIE 0x00000020
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| 81 | #define MSTATUS_HPIE 0x00000040
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| 82 | #define MSTATUS_MPIE 0x00000080
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| 83 | #define MSTATUS_SPP 0x00000100
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| 84 | #define MSTATUS_HPP 0x00000600
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| 85 | #define MSTATUS_MPP 0x00001800
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| 86 | #define MSTATUS_FS 0x00006000
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| 87 | #define MSTATUS_XS 0x00018000
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| 88 | #define MSTATUS_MPRV 0x00020000
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| 89 | #define MSTATUS_PUM 0x00040000
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| 90 | #define MSTATUS_MXR 0x00080000
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| 91 | #define MSTATUS_VM 0x1F000000
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| 92 | #define MSTATUS32_SD 0x80000000
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| 93 | #define MSTATUS64_SD 0x8000000000000000
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| 94 |
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| 95 | #define SSTATUS_UIE 0x00000001
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| 96 | #define SSTATUS_SIE 0x00000002
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| 97 | #define SSTATUS_UPIE 0x00000010
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| 98 | #define SSTATUS_SPIE 0x00000020
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| 99 | #define SSTATUS_SPP 0x00000100
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| 100 | #define SSTATUS_FS 0x00006000
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| 101 | #define SSTATUS_XS 0x00018000
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| 102 | #define SSTATUS_PUM 0x00040000
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| 103 | #define SSTATUS32_SD 0x80000000
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| 104 | #define SSTATUS64_SD 0x8000000000000000
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| 105 |
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| 106 | #define DCSR_XDEBUGVER (3<<30)
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| 107 | #define DCSR_NDRESET (1<<29)
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| 108 | #define DCSR_FULLRESET (1<<28)
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| 109 | #define DCSR_EBREAKM (1<<15)
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| 110 | #define DCSR_EBREAKH (1<<14)
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| 111 | #define DCSR_EBREAKS (1<<13)
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| 112 | #define DCSR_EBREAKU (1<<12)
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| 113 | #define DCSR_STOPCYCLE (1<<10)
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| 114 | #define DCSR_STOPTIME (1<<9)
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| 115 | #define DCSR_CAUSE (7<<6)
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| 116 | #define DCSR_DEBUGINT (1<<5)
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| 117 | #define DCSR_HALT (1<<3)
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| 118 | #define DCSR_STEP (1<<2)
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| 119 | #define DCSR_PRV (3<<0)
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| 120 |
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| 121 | #define DCSR_CAUSE_NONE 0
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| 122 | #define DCSR_CAUSE_SWBP 1
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| 123 | #define DCSR_CAUSE_HWBP 2
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| 124 | #define DCSR_CAUSE_DEBUGINT 3
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| 125 | #define DCSR_CAUSE_STEP 4
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| 126 | #define DCSR_CAUSE_HALT 5
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| 127 |
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| 128 | #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
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| 129 | #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
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| 130 | #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
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| 131 |
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| 132 | #define MCONTROL_SELECT (1<<19)
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| 133 | #define MCONTROL_TIMING (1<<18)
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| 134 | #define MCONTROL_ACTION (0x3f<<12)
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| 135 | #define MCONTROL_CHAIN (1<<11)
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| 136 | #define MCONTROL_MATCH (0xf<<7)
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| 137 | #define MCONTROL_M (1<<6)
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| 138 | #define MCONTROL_H (1<<5)
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| 139 | #define MCONTROL_S (1<<4)
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| 140 | #define MCONTROL_U (1<<3)
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| 141 | #define MCONTROL_EXECUTE (1<<2)
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| 142 | #define MCONTROL_STORE (1<<1)
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| 143 | #define MCONTROL_LOAD (1<<0)
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| 144 |
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| 145 | #define MCONTROL_TYPE_NONE 0
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| 146 | #define MCONTROL_TYPE_MATCH 2
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| 147 |
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| 148 | #define MCONTROL_ACTION_DEBUG_EXCEPTION 0
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| 149 | #define MCONTROL_ACTION_DEBUG_MODE 1
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| 150 | #define MCONTROL_ACTION_TRACE_START 2
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| 151 | #define MCONTROL_ACTION_TRACE_STOP 3
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| 152 | #define MCONTROL_ACTION_TRACE_EMIT 4
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| 153 |
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| 154 | #define MCONTROL_MATCH_EQUAL 0
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| 155 | #define MCONTROL_MATCH_NAPOT 1
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| 156 | #define MCONTROL_MATCH_GE 2
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| 157 | #define MCONTROL_MATCH_LT 3
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| 158 | #define MCONTROL_MATCH_MASK_LOW 4
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| 159 | #define MCONTROL_MATCH_MASK_HIGH 5
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| 160 |
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| 161 | #define MIP_SSIP (1 << IRQ_S_SOFT)
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| 162 | #define MIP_HSIP (1 << IRQ_H_SOFT)
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| 163 | #define MIP_MSIP (1 << IRQ_M_SOFT)
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| 164 | #define MIP_STIP (1 << IRQ_S_TIMER)
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| 165 | #define MIP_HTIP (1 << IRQ_H_TIMER)
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| 166 | #define MIP_MTIP (1 << IRQ_M_TIMER)
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| 167 | #define MIP_SEIP (1 << IRQ_S_EXT)
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| 168 | #define MIP_HEIP (1 << IRQ_H_EXT)
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| 169 | #define MIP_MEIP (1 << IRQ_M_EXT)
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| 170 |
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| 171 | #define SIP_SSIP MIP_SSIP
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| 172 | #define SIP_STIP MIP_STIP
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| 173 |
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| 174 | #define PRV_U 0
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| 175 | #define PRV_S 1
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| 176 | #define PRV_H 2
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| 177 | #define PRV_M 3
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| 178 |
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| 179 | #define VM_MBARE 0
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| 180 | #define VM_MBB 1
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| 181 | #define VM_MBBID 2
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| 182 | #define VM_SV32 8
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| 183 | #define VM_SV39 9
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| 184 | #define VM_SV48 10
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| 185 |
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| 186 | #define IRQ_S_SOFT 1
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| 187 | #define IRQ_H_SOFT 2
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| 188 | #define IRQ_M_SOFT 3
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| 189 | #define IRQ_S_TIMER 5
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| 190 | #define IRQ_H_TIMER 6
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| 191 | #define IRQ_M_TIMER 7
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| 192 | #define IRQ_S_EXT 9
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| 193 | #define IRQ_H_EXT 10
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| 194 | #define IRQ_M_EXT 11
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| 195 | #define IRQ_COP 12
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| 196 | #define IRQ_HOST 13
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| 197 |
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| 198 | #define DEFAULT_RSTVEC 0x00001000
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| 199 | #define DEFAULT_NMIVEC 0x00001004
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| 200 | #define DEFAULT_MTVEC 0x00001010
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| 201 | #define CONFIG_STRING_ADDR 0x0000100C
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| 202 | #define EXT_IO_BASE 0x40000000
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| 203 | #define DRAM_BASE 0x80000000
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| 204 |
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| 205 | /* page table entry (PTE) fields */
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| 206 | #define PTE_V 0x001U /* Valid */
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| 207 | #define PTE_R 0x002U /* Read */
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| 208 | #define PTE_W 0x004U /* Write */
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| 209 | #define PTE_X 0x008U /* Execute */
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| 210 | #define PTE_U 0x010U /* User */
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| 211 | #define PTE_G 0x020U /* Global */
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| 212 | #define PTE_A 0x040U /* Accessed */
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| 213 | #define PTE_D 0x080U /* Dirty */
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| 214 | #define PTE_SOFT 0x300U /* Reserved for Software */
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| 215 |
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| 216 | #define PTE_PPN_SHIFT 10
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| 217 |
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| 218 | #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
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| 219 |
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| 220 | #if defined(__riscv)
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| 221 |
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| 222 | #if defined(__riscv64)
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| 223 | # define MSTATUS_SD MSTATUS64_SD
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| 224 | # define SSTATUS_SD SSTATUS64_SD
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| 225 | # define RISCV_PGLEVEL_BITS 9
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| 226 | #else
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| 227 | # define MSTATUS_SD MSTATUS32_SD
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| 228 | # define SSTATUS_SD SSTATUS32_SD
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| 229 | # define RISCV_PGLEVEL_BITS 10
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| 230 | #endif
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| 231 | #define RISCV_PGSHIFT 12
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| 232 | #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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| 233 |
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| 234 | #ifndef TOPPERS_MACRO_ONLY
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| 235 |
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| 236 | #if defined(__GNUC__)
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| 237 |
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| 238 | #define read_csr(reg) ({ unsigned long __tmp; \
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| 239 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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| 240 | __tmp; })
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| 241 |
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| 242 | #define write_csr(reg, val) ({ \
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| 243 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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| 244 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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| 245 | else \
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| 246 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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| 247 |
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| 248 | #define swap_csr(reg, val) ({ unsigned long __tmp; \
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| 249 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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| 250 | asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
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| 251 | else \
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| 252 | asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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| 253 | __tmp; })
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| 254 |
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| 255 | #define set_csr(reg, bit) ({ unsigned long __tmp; \
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| 256 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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| 257 | asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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| 258 | else \
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| 259 | asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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| 260 | __tmp; })
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| 261 |
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| 262 | #define clear_csr(reg, bit) ({ unsigned long __tmp; \
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| 263 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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| 264 | asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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| 265 | else \
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| 266 | asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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| 267 | __tmp; })
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| 268 |
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| 269 | #define read_time() read_csr(mtime)
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| 270 | #define read_cycle() read_csr(mcycle)
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| 271 | #define current_coreid() read_csr(mhartid)
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| 272 |
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| 273 | #endif /* __GNUC__ */
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| 274 |
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| 275 | #endif /* TOPPERS_MACRO_ONLY */
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| 276 |
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| 277 | #endif
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| 278 |
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| 279 | #endif
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| 280 | /* Automatically generated by parse-opcodes */
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| 281 | #ifndef RISCV_ENCODING_H
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| 282 | #define RISCV_ENCODING_H
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| 283 | #define MATCH_BEQ 0x63
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| 284 | #define MASK_BEQ 0x707f
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| 285 | #define MATCH_BNE 0x1063
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| 286 | #define MASK_BNE 0x707f
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| 287 | #define MATCH_BLT 0x4063
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| 288 | #define MASK_BLT 0x707f
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| 289 | #define MATCH_BGE 0x5063
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| 290 | #define MASK_BGE 0x707f
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| 291 | #define MATCH_BLTU 0x6063
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| 292 | #define MASK_BLTU 0x707f
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| 293 | #define MATCH_BGEU 0x7063
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| 294 | #define MASK_BGEU 0x707f
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| 295 | #define MATCH_JALR 0x67
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| 296 | #define MASK_JALR 0x707f
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| 297 | #define MATCH_JAL 0x6f
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| 298 | #define MASK_JAL 0x7f
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| 299 | #define MATCH_LUI 0x37
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| 300 | #define MASK_LUI 0x7f
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| 301 | #define MATCH_AUIPC 0x17
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| 302 | #define MASK_AUIPC 0x7f
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| 303 | #define MATCH_ADDI 0x13
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| 304 | #define MASK_ADDI 0x707f
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| 305 | #define MATCH_SLLI 0x1013
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| 306 | #define MASK_SLLI 0xfc00707f
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| 307 | #define MATCH_SLTI 0x2013
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| 308 | #define MASK_SLTI 0x707f
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| 309 | #define MATCH_SLTIU 0x3013
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| 310 | #define MASK_SLTIU 0x707f
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| 311 | #define MATCH_XORI 0x4013
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| 312 | #define MASK_XORI 0x707f
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| 313 | #define MATCH_SRLI 0x5013
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| 314 | #define MASK_SRLI 0xfc00707f
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| 315 | #define MATCH_SRAI 0x40005013
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| 316 | #define MASK_SRAI 0xfc00707f
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| 317 | #define MATCH_ORI 0x6013
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| 318 | #define MASK_ORI 0x707f
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| 319 | #define MATCH_ANDI 0x7013
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| 320 | #define MASK_ANDI 0x707f
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| 321 | #define MATCH_ADD 0x33
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| 322 | #define MASK_ADD 0xfe00707f
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| 323 | #define MATCH_SUB 0x40000033
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| 324 | #define MASK_SUB 0xfe00707f
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| 325 | #define MATCH_SLL 0x1033
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| 326 | #define MASK_SLL 0xfe00707f
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| 327 | #define MATCH_SLT 0x2033
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| 328 | #define MASK_SLT 0xfe00707f
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| 329 | #define MATCH_SLTU 0x3033
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| 330 | #define MASK_SLTU 0xfe00707f
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| 331 | #define MATCH_XOR 0x4033
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| 332 | #define MASK_XOR 0xfe00707f
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| 333 | #define MATCH_SRL 0x5033
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| 334 | #define MASK_SRL 0xfe00707f
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| 335 | #define MATCH_SRA 0x40005033
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| 336 | #define MASK_SRA 0xfe00707f
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| 337 | #define MATCH_OR 0x6033
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| 338 | #define MASK_OR 0xfe00707f
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| 339 | #define MATCH_AND 0x7033
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| 340 | #define MASK_AND 0xfe00707f
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| 341 | #define MATCH_ADDIW 0x1b
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|---|
| 342 | #define MASK_ADDIW 0x707f
|
|---|
| 343 | #define MATCH_SLLIW 0x101b
|
|---|
| 344 | #define MASK_SLLIW 0xfe00707f
|
|---|
| 345 | #define MATCH_SRLIW 0x501b
|
|---|
| 346 | #define MASK_SRLIW 0xfe00707f
|
|---|
| 347 | #define MATCH_SRAIW 0x4000501b
|
|---|
| 348 | #define MASK_SRAIW 0xfe00707f
|
|---|
| 349 | #define MATCH_ADDW 0x3b
|
|---|
| 350 | #define MASK_ADDW 0xfe00707f
|
|---|
| 351 | #define MATCH_SUBW 0x4000003b
|
|---|
| 352 | #define MASK_SUBW 0xfe00707f
|
|---|
| 353 | #define MATCH_SLLW 0x103b
|
|---|
| 354 | #define MASK_SLLW 0xfe00707f
|
|---|
| 355 | #define MATCH_SRLW 0x503b
|
|---|
| 356 | #define MASK_SRLW 0xfe00707f
|
|---|
| 357 | #define MATCH_SRAW 0x4000503b
|
|---|
| 358 | #define MASK_SRAW 0xfe00707f
|
|---|
| 359 | #define MATCH_LB 0x3
|
|---|
| 360 | #define MASK_LB 0x707f
|
|---|
| 361 | #define MATCH_LH 0x1003
|
|---|
| 362 | #define MASK_LH 0x707f
|
|---|
| 363 | #define MATCH_LW 0x2003
|
|---|
| 364 | #define MASK_LW 0x707f
|
|---|
| 365 | #define MATCH_LD 0x3003
|
|---|
| 366 | #define MASK_LD 0x707f
|
|---|
| 367 | #define MATCH_LBU 0x4003
|
|---|
| 368 | #define MASK_LBU 0x707f
|
|---|
| 369 | #define MATCH_LHU 0x5003
|
|---|
| 370 | #define MASK_LHU 0x707f
|
|---|
| 371 | #define MATCH_LWU 0x6003
|
|---|
| 372 | #define MASK_LWU 0x707f
|
|---|
| 373 | #define MATCH_SB 0x23
|
|---|
| 374 | #define MASK_SB 0x707f
|
|---|
| 375 | #define MATCH_SH 0x1023
|
|---|
| 376 | #define MASK_SH 0x707f
|
|---|
| 377 | #define MATCH_SW 0x2023
|
|---|
| 378 | #define MASK_SW 0x707f
|
|---|
| 379 | #define MATCH_SD 0x3023
|
|---|
| 380 | #define MASK_SD 0x707f
|
|---|
| 381 | #define MATCH_FENCE 0xf
|
|---|
| 382 | #define MASK_FENCE 0x707f
|
|---|
| 383 | #define MATCH_FENCE_I 0x100f
|
|---|
| 384 | #define MASK_FENCE_I 0x707f
|
|---|
| 385 | #define MATCH_MUL 0x2000033
|
|---|
| 386 | #define MASK_MUL 0xfe00707f
|
|---|
| 387 | #define MATCH_MULH 0x2001033
|
|---|
| 388 | #define MASK_MULH 0xfe00707f
|
|---|
| 389 | #define MATCH_MULHSU 0x2002033
|
|---|
| 390 | #define MASK_MULHSU 0xfe00707f
|
|---|
| 391 | #define MATCH_MULHU 0x2003033
|
|---|
| 392 | #define MASK_MULHU 0xfe00707f
|
|---|
| 393 | #define MATCH_DIV 0x2004033
|
|---|
| 394 | #define MASK_DIV 0xfe00707f
|
|---|
| 395 | #define MATCH_DIVU 0x2005033
|
|---|
| 396 | #define MASK_DIVU 0xfe00707f
|
|---|
| 397 | #define MATCH_REM 0x2006033
|
|---|
| 398 | #define MASK_REM 0xfe00707f
|
|---|
| 399 | #define MATCH_REMU 0x2007033
|
|---|
| 400 | #define MASK_REMU 0xfe00707f
|
|---|
| 401 | #define MATCH_MULW 0x200003b
|
|---|
| 402 | #define MASK_MULW 0xfe00707f
|
|---|
| 403 | #define MATCH_DIVW 0x200403b
|
|---|
| 404 | #define MASK_DIVW 0xfe00707f
|
|---|
| 405 | #define MATCH_DIVUW 0x200503b
|
|---|
| 406 | #define MASK_DIVUW 0xfe00707f
|
|---|
| 407 | #define MATCH_REMW 0x200603b
|
|---|
| 408 | #define MASK_REMW 0xfe00707f
|
|---|
| 409 | #define MATCH_REMUW 0x200703b
|
|---|
| 410 | #define MASK_REMUW 0xfe00707f
|
|---|
| 411 | #define MATCH_AMOADD_W 0x202f
|
|---|
| 412 | #define MASK_AMOADD_W 0xf800707f
|
|---|
| 413 | #define MATCH_AMOXOR_W 0x2000202f
|
|---|
| 414 | #define MASK_AMOXOR_W 0xf800707f
|
|---|
| 415 | #define MATCH_AMOOR_W 0x4000202f
|
|---|
| 416 | #define MASK_AMOOR_W 0xf800707f
|
|---|
| 417 | #define MATCH_AMOAND_W 0x6000202f
|
|---|
| 418 | #define MASK_AMOAND_W 0xf800707f
|
|---|
| 419 | #define MATCH_AMOMIN_W 0x8000202f
|
|---|
| 420 | #define MASK_AMOMIN_W 0xf800707f
|
|---|
| 421 | #define MATCH_AMOMAX_W 0xa000202f
|
|---|
| 422 | #define MASK_AMOMAX_W 0xf800707f
|
|---|
| 423 | #define MATCH_AMOMINU_W 0xc000202f
|
|---|
| 424 | #define MASK_AMOMINU_W 0xf800707f
|
|---|
| 425 | #define MATCH_AMOMAXU_W 0xe000202f
|
|---|
| 426 | #define MASK_AMOMAXU_W 0xf800707f
|
|---|
| 427 | #define MATCH_AMOSWAP_W 0x800202f
|
|---|
| 428 | #define MASK_AMOSWAP_W 0xf800707f
|
|---|
| 429 | #define MATCH_LR_W 0x1000202f
|
|---|
| 430 | #define MASK_LR_W 0xf9f0707f
|
|---|
| 431 | #define MATCH_SC_W 0x1800202f
|
|---|
| 432 | #define MASK_SC_W 0xf800707f
|
|---|
| 433 | #define MATCH_AMOADD_D 0x302f
|
|---|
| 434 | #define MASK_AMOADD_D 0xf800707f
|
|---|
| 435 | #define MATCH_AMOXOR_D 0x2000302f
|
|---|
| 436 | #define MASK_AMOXOR_D 0xf800707f
|
|---|
| 437 | #define MATCH_AMOOR_D 0x4000302f
|
|---|
| 438 | #define MASK_AMOOR_D 0xf800707f
|
|---|
| 439 | #define MATCH_AMOAND_D 0x6000302f
|
|---|
| 440 | #define MASK_AMOAND_D 0xf800707f
|
|---|
| 441 | #define MATCH_AMOMIN_D 0x8000302f
|
|---|
| 442 | #define MASK_AMOMIN_D 0xf800707f
|
|---|
| 443 | #define MATCH_AMOMAX_D 0xa000302f
|
|---|
| 444 | #define MASK_AMOMAX_D 0xf800707f
|
|---|
| 445 | #define MATCH_AMOMINU_D 0xc000302f
|
|---|
| 446 | #define MASK_AMOMINU_D 0xf800707f
|
|---|
| 447 | #define MATCH_AMOMAXU_D 0xe000302f
|
|---|
| 448 | #define MASK_AMOMAXU_D 0xf800707f
|
|---|
| 449 | #define MATCH_AMOSWAP_D 0x800302f
|
|---|
| 450 | #define MASK_AMOSWAP_D 0xf800707f
|
|---|
| 451 | #define MATCH_LR_D 0x1000302f
|
|---|
| 452 | #define MASK_LR_D 0xf9f0707f
|
|---|
| 453 | #define MATCH_SC_D 0x1800302f
|
|---|
| 454 | #define MASK_SC_D 0xf800707f
|
|---|
| 455 | #define MATCH_ECALL 0x73
|
|---|
| 456 | #define MASK_ECALL 0xffffffff
|
|---|
| 457 | #define MATCH_EBREAK 0x100073
|
|---|
| 458 | #define MASK_EBREAK 0xffffffff
|
|---|
| 459 | #define MATCH_URET 0x200073
|
|---|
| 460 | #define MASK_URET 0xffffffff
|
|---|
| 461 | #define MATCH_SRET 0x10200073
|
|---|
| 462 | #define MASK_SRET 0xffffffff
|
|---|
| 463 | #define MATCH_HRET 0x20200073
|
|---|
| 464 | #define MASK_HRET 0xffffffff
|
|---|
| 465 | #define MATCH_MRET 0x30200073
|
|---|
| 466 | #define MASK_MRET 0xffffffff
|
|---|
| 467 | #define MATCH_DRET 0x7b200073
|
|---|
| 468 | #define MASK_DRET 0xffffffff
|
|---|
| 469 | #define MATCH_SFENCE_VM 0x10400073
|
|---|
| 470 | #define MASK_SFENCE_VM 0xfff07fff
|
|---|
| 471 | #define MATCH_WFI 0x10500073
|
|---|
| 472 | #define MASK_WFI 0xffffffff
|
|---|
| 473 | #define MATCH_CSRRW 0x1073
|
|---|
| 474 | #define MASK_CSRRW 0x707f
|
|---|
| 475 | #define MATCH_CSRRS 0x2073
|
|---|
| 476 | #define MASK_CSRRS 0x707f
|
|---|
| 477 | #define MATCH_CSRRC 0x3073
|
|---|
| 478 | #define MASK_CSRRC 0x707f
|
|---|
| 479 | #define MATCH_CSRRWI 0x5073
|
|---|
| 480 | #define MASK_CSRRWI 0x707f
|
|---|
| 481 | #define MATCH_CSRRSI 0x6073
|
|---|
| 482 | #define MASK_CSRRSI 0x707f
|
|---|
| 483 | #define MATCH_CSRRCI 0x7073
|
|---|
| 484 | #define MASK_CSRRCI 0x707f
|
|---|
| 485 | #define MATCH_FADD_S 0x53
|
|---|
| 486 | #define MASK_FADD_S 0xfe00007f
|
|---|
| 487 | #define MATCH_FSUB_S 0x8000053
|
|---|
| 488 | #define MASK_FSUB_S 0xfe00007f
|
|---|
| 489 | #define MATCH_FMUL_S 0x10000053
|
|---|
| 490 | #define MASK_FMUL_S 0xfe00007f
|
|---|
| 491 | #define MATCH_FDIV_S 0x18000053
|
|---|
| 492 | #define MASK_FDIV_S 0xfe00007f
|
|---|
| 493 | #define MATCH_FSGNJ_S 0x20000053
|
|---|
| 494 | #define MASK_FSGNJ_S 0xfe00707f
|
|---|
| 495 | #define MATCH_FSGNJN_S 0x20001053
|
|---|
| 496 | #define MASK_FSGNJN_S 0xfe00707f
|
|---|
| 497 | #define MATCH_FSGNJX_S 0x20002053
|
|---|
| 498 | #define MASK_FSGNJX_S 0xfe00707f
|
|---|
| 499 | #define MATCH_FMIN_S 0x28000053
|
|---|
| 500 | #define MASK_FMIN_S 0xfe00707f
|
|---|
| 501 | #define MATCH_FMAX_S 0x28001053
|
|---|
| 502 | #define MASK_FMAX_S 0xfe00707f
|
|---|
| 503 | #define MATCH_FSQRT_S 0x58000053
|
|---|
| 504 | #define MASK_FSQRT_S 0xfff0007f
|
|---|
| 505 | #define MATCH_FADD_D 0x2000053
|
|---|
| 506 | #define MASK_FADD_D 0xfe00007f
|
|---|
| 507 | #define MATCH_FSUB_D 0xa000053
|
|---|
| 508 | #define MASK_FSUB_D 0xfe00007f
|
|---|
| 509 | #define MATCH_FMUL_D 0x12000053
|
|---|
| 510 | #define MASK_FMUL_D 0xfe00007f
|
|---|
| 511 | #define MATCH_FDIV_D 0x1a000053
|
|---|
| 512 | #define MASK_FDIV_D 0xfe00007f
|
|---|
| 513 | #define MATCH_FSGNJ_D 0x22000053
|
|---|
| 514 | #define MASK_FSGNJ_D 0xfe00707f
|
|---|
| 515 | #define MATCH_FSGNJN_D 0x22001053
|
|---|
| 516 | #define MASK_FSGNJN_D 0xfe00707f
|
|---|
| 517 | #define MATCH_FSGNJX_D 0x22002053
|
|---|
| 518 | #define MASK_FSGNJX_D 0xfe00707f
|
|---|
| 519 | #define MATCH_FMIN_D 0x2a000053
|
|---|
| 520 | #define MASK_FMIN_D 0xfe00707f
|
|---|
| 521 | #define MATCH_FMAX_D 0x2a001053
|
|---|
| 522 | #define MASK_FMAX_D 0xfe00707f
|
|---|
| 523 | #define MATCH_FCVT_S_D 0x40100053
|
|---|
| 524 | #define MASK_FCVT_S_D 0xfff0007f
|
|---|
| 525 | #define MATCH_FCVT_D_S 0x42000053
|
|---|
| 526 | #define MASK_FCVT_D_S 0xfff0007f
|
|---|
| 527 | #define MATCH_FSQRT_D 0x5a000053
|
|---|
| 528 | #define MASK_FSQRT_D 0xfff0007f
|
|---|
| 529 | #define MATCH_FLE_S 0xa0000053
|
|---|
| 530 | #define MASK_FLE_S 0xfe00707f
|
|---|
| 531 | #define MATCH_FLT_S 0xa0001053
|
|---|
| 532 | #define MASK_FLT_S 0xfe00707f
|
|---|
| 533 | #define MATCH_FEQ_S 0xa0002053
|
|---|
| 534 | #define MASK_FEQ_S 0xfe00707f
|
|---|
| 535 | #define MATCH_FLE_D 0xa2000053
|
|---|
| 536 | #define MASK_FLE_D 0xfe00707f
|
|---|
| 537 | #define MATCH_FLT_D 0xa2001053
|
|---|
| 538 | #define MASK_FLT_D 0xfe00707f
|
|---|
| 539 | #define MATCH_FEQ_D 0xa2002053
|
|---|
| 540 | #define MASK_FEQ_D 0xfe00707f
|
|---|
| 541 | #define MATCH_FCVT_W_S 0xc0000053
|
|---|
| 542 | #define MASK_FCVT_W_S 0xfff0007f
|
|---|
| 543 | #define MATCH_FCVT_WU_S 0xc0100053
|
|---|
| 544 | #define MASK_FCVT_WU_S 0xfff0007f
|
|---|
| 545 | #define MATCH_FCVT_L_S 0xc0200053
|
|---|
| 546 | #define MASK_FCVT_L_S 0xfff0007f
|
|---|
| 547 | #define MATCH_FCVT_LU_S 0xc0300053
|
|---|
| 548 | #define MASK_FCVT_LU_S 0xfff0007f
|
|---|
| 549 | #define MATCH_FMV_X_S 0xe0000053
|
|---|
| 550 | #define MASK_FMV_X_S 0xfff0707f
|
|---|
| 551 | #define MATCH_FCLASS_S 0xe0001053
|
|---|
| 552 | #define MASK_FCLASS_S 0xfff0707f
|
|---|
| 553 | #define MATCH_FCVT_W_D 0xc2000053
|
|---|
| 554 | #define MASK_FCVT_W_D 0xfff0007f
|
|---|
| 555 | #define MATCH_FCVT_WU_D 0xc2100053
|
|---|
| 556 | #define MASK_FCVT_WU_D 0xfff0007f
|
|---|
| 557 | #define MATCH_FCVT_L_D 0xc2200053
|
|---|
| 558 | #define MASK_FCVT_L_D 0xfff0007f
|
|---|
| 559 | #define MATCH_FCVT_LU_D 0xc2300053
|
|---|
| 560 | #define MASK_FCVT_LU_D 0xfff0007f
|
|---|
| 561 | #define MATCH_FMV_X_D 0xe2000053
|
|---|
| 562 | #define MASK_FMV_X_D 0xfff0707f
|
|---|
| 563 | #define MATCH_FCLASS_D 0xe2001053
|
|---|
| 564 | #define MASK_FCLASS_D 0xfff0707f
|
|---|
| 565 | #define MATCH_FCVT_S_W 0xd0000053
|
|---|
| 566 | #define MASK_FCVT_S_W 0xfff0007f
|
|---|
| 567 | #define MATCH_FCVT_S_WU 0xd0100053
|
|---|
| 568 | #define MASK_FCVT_S_WU 0xfff0007f
|
|---|
| 569 | #define MATCH_FCVT_S_L 0xd0200053
|
|---|
| 570 | #define MASK_FCVT_S_L 0xfff0007f
|
|---|
| 571 | #define MATCH_FCVT_S_LU 0xd0300053
|
|---|
| 572 | #define MASK_FCVT_S_LU 0xfff0007f
|
|---|
| 573 | #define MATCH_FMV_S_X 0xf0000053
|
|---|
| 574 | #define MASK_FMV_S_X 0xfff0707f
|
|---|
| 575 | #define MATCH_FCVT_D_W 0xd2000053
|
|---|
| 576 | #define MASK_FCVT_D_W 0xfff0007f
|
|---|
| 577 | #define MATCH_FCVT_D_WU 0xd2100053
|
|---|
| 578 | #define MASK_FCVT_D_WU 0xfff0007f
|
|---|
| 579 | #define MATCH_FCVT_D_L 0xd2200053
|
|---|
| 580 | #define MASK_FCVT_D_L 0xfff0007f
|
|---|
| 581 | #define MATCH_FCVT_D_LU 0xd2300053
|
|---|
| 582 | #define MASK_FCVT_D_LU 0xfff0007f
|
|---|
| 583 | #define MATCH_FMV_D_X 0xf2000053
|
|---|
| 584 | #define MASK_FMV_D_X 0xfff0707f
|
|---|
| 585 | #define MATCH_FLW 0x2007
|
|---|
| 586 | #define MASK_FLW 0x707f
|
|---|
| 587 | #define MATCH_FLD 0x3007
|
|---|
| 588 | #define MASK_FLD 0x707f
|
|---|
| 589 | #define MATCH_FSW 0x2027
|
|---|
| 590 | #define MASK_FSW 0x707f
|
|---|
| 591 | #define MATCH_FSD 0x3027
|
|---|
| 592 | #define MASK_FSD 0x707f
|
|---|
| 593 | #define MATCH_FMADD_S 0x43
|
|---|
| 594 | #define MASK_FMADD_S 0x600007f
|
|---|
| 595 | #define MATCH_FMSUB_S 0x47
|
|---|
| 596 | #define MASK_FMSUB_S 0x600007f
|
|---|
| 597 | #define MATCH_FNMSUB_S 0x4b
|
|---|
| 598 | #define MASK_FNMSUB_S 0x600007f
|
|---|
| 599 | #define MATCH_FNMADD_S 0x4f
|
|---|
| 600 | #define MASK_FNMADD_S 0x600007f
|
|---|
| 601 | #define MATCH_FMADD_D 0x2000043
|
|---|
| 602 | #define MASK_FMADD_D 0x600007f
|
|---|
| 603 | #define MATCH_FMSUB_D 0x2000047
|
|---|
| 604 | #define MASK_FMSUB_D 0x600007f
|
|---|
| 605 | #define MATCH_FNMSUB_D 0x200004b
|
|---|
| 606 | #define MASK_FNMSUB_D 0x600007f
|
|---|
| 607 | #define MATCH_FNMADD_D 0x200004f
|
|---|
| 608 | #define MASK_FNMADD_D 0x600007f
|
|---|
| 609 | #define MATCH_C_NOP 0x1
|
|---|
| 610 | #define MASK_C_NOP 0xffff
|
|---|
| 611 | #define MATCH_C_ADDI16SP 0x6101
|
|---|
| 612 | #define MASK_C_ADDI16SP 0xef83
|
|---|
| 613 | #define MATCH_C_JR 0x8002
|
|---|
| 614 | #define MASK_C_JR 0xf07f
|
|---|
| 615 | #define MATCH_C_JALR 0x9002
|
|---|
| 616 | #define MASK_C_JALR 0xf07f
|
|---|
| 617 | #define MATCH_C_EBREAK 0x9002
|
|---|
| 618 | #define MASK_C_EBREAK 0xffff
|
|---|
| 619 | #define MATCH_C_LD 0x6000
|
|---|
| 620 | #define MASK_C_LD 0xe003
|
|---|
| 621 | #define MATCH_C_SD 0xe000
|
|---|
| 622 | #define MASK_C_SD 0xe003
|
|---|
| 623 | #define MATCH_C_ADDIW 0x2001
|
|---|
| 624 | #define MASK_C_ADDIW 0xe003
|
|---|
| 625 | #define MATCH_C_LDSP 0x6002
|
|---|
| 626 | #define MASK_C_LDSP 0xe003
|
|---|
| 627 | #define MATCH_C_SDSP 0xe002
|
|---|
| 628 | #define MASK_C_SDSP 0xe003
|
|---|
| 629 | #define MATCH_C_ADDI4SPN 0x0
|
|---|
| 630 | #define MASK_C_ADDI4SPN 0xe003
|
|---|
| 631 | #define MATCH_C_FLD 0x2000
|
|---|
| 632 | #define MASK_C_FLD 0xe003
|
|---|
| 633 | #define MATCH_C_LW 0x4000
|
|---|
| 634 | #define MASK_C_LW 0xe003
|
|---|
| 635 | #define MATCH_C_FLW 0x6000
|
|---|
| 636 | #define MASK_C_FLW 0xe003
|
|---|
| 637 | #define MATCH_C_FSD 0xa000
|
|---|
| 638 | #define MASK_C_FSD 0xe003
|
|---|
| 639 | #define MATCH_C_SW 0xc000
|
|---|
| 640 | #define MASK_C_SW 0xe003
|
|---|
| 641 | #define MATCH_C_FSW 0xe000
|
|---|
| 642 | #define MASK_C_FSW 0xe003
|
|---|
| 643 | #define MATCH_C_ADDI 0x1
|
|---|
| 644 | #define MASK_C_ADDI 0xe003
|
|---|
| 645 | #define MATCH_C_JAL 0x2001
|
|---|
| 646 | #define MASK_C_JAL 0xe003
|
|---|
| 647 | #define MATCH_C_LI 0x4001
|
|---|
| 648 | #define MASK_C_LI 0xe003
|
|---|
| 649 | #define MATCH_C_LUI 0x6001
|
|---|
| 650 | #define MASK_C_LUI 0xe003
|
|---|
| 651 | #define MATCH_C_SRLI 0x8001
|
|---|
| 652 | #define MASK_C_SRLI 0xec03
|
|---|
| 653 | #define MATCH_C_SRAI 0x8401
|
|---|
| 654 | #define MASK_C_SRAI 0xec03
|
|---|
| 655 | #define MATCH_C_ANDI 0x8801
|
|---|
| 656 | #define MASK_C_ANDI 0xec03
|
|---|
| 657 | #define MATCH_C_SUB 0x8c01
|
|---|
| 658 | #define MASK_C_SUB 0xfc63
|
|---|
| 659 | #define MATCH_C_XOR 0x8c21
|
|---|
| 660 | #define MASK_C_XOR 0xfc63
|
|---|
| 661 | #define MATCH_C_OR 0x8c41
|
|---|
| 662 | #define MASK_C_OR 0xfc63
|
|---|
| 663 | #define MATCH_C_AND 0x8c61
|
|---|
| 664 | #define MASK_C_AND 0xfc63
|
|---|
| 665 | #define MATCH_C_SUBW 0x9c01
|
|---|
| 666 | #define MASK_C_SUBW 0xfc63
|
|---|
| 667 | #define MATCH_C_ADDW 0x9c21
|
|---|
| 668 | #define MASK_C_ADDW 0xfc63
|
|---|
| 669 | #define MATCH_C_J 0xa001
|
|---|
| 670 | #define MASK_C_J 0xe003
|
|---|
| 671 | #define MATCH_C_BEQZ 0xc001
|
|---|
| 672 | #define MASK_C_BEQZ 0xe003
|
|---|
| 673 | #define MATCH_C_BNEZ 0xe001
|
|---|
| 674 | #define MASK_C_BNEZ 0xe003
|
|---|
| 675 | #define MATCH_C_SLLI 0x2
|
|---|
| 676 | #define MASK_C_SLLI 0xe003
|
|---|
| 677 | #define MATCH_C_FLDSP 0x2002
|
|---|
| 678 | #define MASK_C_FLDSP 0xe003
|
|---|
| 679 | #define MATCH_C_LWSP 0x4002
|
|---|
| 680 | #define MASK_C_LWSP 0xe003
|
|---|
| 681 | #define MATCH_C_FLWSP 0x6002
|
|---|
| 682 | #define MASK_C_FLWSP 0xe003
|
|---|
| 683 | #define MATCH_C_MV 0x8002
|
|---|
| 684 | #define MASK_C_MV 0xf003
|
|---|
| 685 | #define MATCH_C_ADD 0x9002
|
|---|
| 686 | #define MASK_C_ADD 0xf003
|
|---|
| 687 | #define MATCH_C_FSDSP 0xa002
|
|---|
| 688 | #define MASK_C_FSDSP 0xe003
|
|---|
| 689 | #define MATCH_C_SWSP 0xc002
|
|---|
| 690 | #define MASK_C_SWSP 0xe003
|
|---|
| 691 | #define MATCH_C_FSWSP 0xe002
|
|---|
| 692 | #define MASK_C_FSWSP 0xe003
|
|---|
| 693 | #define MATCH_CUSTOM0 0xb
|
|---|
| 694 | #define MASK_CUSTOM0 0x707f
|
|---|
| 695 | #define MATCH_CUSTOM0_RS1 0x200b
|
|---|
| 696 | #define MASK_CUSTOM0_RS1 0x707f
|
|---|
| 697 | #define MATCH_CUSTOM0_RS1_RS2 0x300b
|
|---|
| 698 | #define MASK_CUSTOM0_RS1_RS2 0x707f
|
|---|
| 699 | #define MATCH_CUSTOM0_RD 0x400b
|
|---|
| 700 | #define MASK_CUSTOM0_RD 0x707f
|
|---|
| 701 | #define MATCH_CUSTOM0_RD_RS1 0x600b
|
|---|
| 702 | #define MASK_CUSTOM0_RD_RS1 0x707f
|
|---|
| 703 | #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
|
|---|
| 704 | #define MASK_CUSTOM0_RD_RS1_RS2 0x707f
|
|---|
| 705 | #define MATCH_CUSTOM1 0x2b
|
|---|
| 706 | #define MASK_CUSTOM1 0x707f
|
|---|
| 707 | #define MATCH_CUSTOM1_RS1 0x202b
|
|---|
| 708 | #define MASK_CUSTOM1_RS1 0x707f
|
|---|
| 709 | #define MATCH_CUSTOM1_RS1_RS2 0x302b
|
|---|
| 710 | #define MASK_CUSTOM1_RS1_RS2 0x707f
|
|---|
| 711 | #define MATCH_CUSTOM1_RD 0x402b
|
|---|
| 712 | #define MASK_CUSTOM1_RD 0x707f
|
|---|
| 713 | #define MATCH_CUSTOM1_RD_RS1 0x602b
|
|---|
| 714 | #define MASK_CUSTOM1_RD_RS1 0x707f
|
|---|
| 715 | #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
|
|---|
| 716 | #define MASK_CUSTOM1_RD_RS1_RS2 0x707f
|
|---|
| 717 | #define MATCH_CUSTOM2 0x5b
|
|---|
| 718 | #define MASK_CUSTOM2 0x707f
|
|---|
| 719 | #define MATCH_CUSTOM2_RS1 0x205b
|
|---|
| 720 | #define MASK_CUSTOM2_RS1 0x707f
|
|---|
| 721 | #define MATCH_CUSTOM2_RS1_RS2 0x305b
|
|---|
| 722 | #define MASK_CUSTOM2_RS1_RS2 0x707f
|
|---|
| 723 | #define MATCH_CUSTOM2_RD 0x405b
|
|---|
| 724 | #define MASK_CUSTOM2_RD 0x707f
|
|---|
| 725 | #define MATCH_CUSTOM2_RD_RS1 0x605b
|
|---|
| 726 | #define MASK_CUSTOM2_RD_RS1 0x707f
|
|---|
| 727 | #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
|
|---|
| 728 | #define MASK_CUSTOM2_RD_RS1_RS2 0x707f
|
|---|
| 729 | #define MATCH_CUSTOM3 0x7b
|
|---|
| 730 | #define MASK_CUSTOM3 0x707f
|
|---|
| 731 | #define MATCH_CUSTOM3_RS1 0x207b
|
|---|
| 732 | #define MASK_CUSTOM3_RS1 0x707f
|
|---|
| 733 | #define MATCH_CUSTOM3_RS1_RS2 0x307b
|
|---|
| 734 | #define MASK_CUSTOM3_RS1_RS2 0x707f
|
|---|
| 735 | #define MATCH_CUSTOM3_RD 0x407b
|
|---|
| 736 | #define MASK_CUSTOM3_RD 0x707f
|
|---|
| 737 | #define MATCH_CUSTOM3_RD_RS1 0x607b
|
|---|
| 738 | #define MASK_CUSTOM3_RD_RS1 0x707f
|
|---|
| 739 | #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
|
|---|
| 740 | #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
|
|---|
| 741 | #define CSR_FFLAGS 0x1
|
|---|
| 742 | #define CSR_FRM 0x2
|
|---|
| 743 | #define CSR_FCSR 0x3
|
|---|
| 744 | #define CSR_CYCLE 0xc00
|
|---|
| 745 | #define CSR_TIME 0xc01
|
|---|
| 746 | #define CSR_INSTRET 0xc02
|
|---|
| 747 | #define CSR_HPMCOUNTER3 0xc03
|
|---|
| 748 | #define CSR_HPMCOUNTER4 0xc04
|
|---|
| 749 | #define CSR_HPMCOUNTER5 0xc05
|
|---|
| 750 | #define CSR_HPMCOUNTER6 0xc06
|
|---|
| 751 | #define CSR_HPMCOUNTER7 0xc07
|
|---|
| 752 | #define CSR_HPMCOUNTER8 0xc08
|
|---|
| 753 | #define CSR_HPMCOUNTER9 0xc09
|
|---|
| 754 | #define CSR_HPMCOUNTER10 0xc0a
|
|---|
| 755 | #define CSR_HPMCOUNTER11 0xc0b
|
|---|
| 756 | #define CSR_HPMCOUNTER12 0xc0c
|
|---|
| 757 | #define CSR_HPMCOUNTER13 0xc0d
|
|---|
| 758 | #define CSR_HPMCOUNTER14 0xc0e
|
|---|
| 759 | #define CSR_HPMCOUNTER15 0xc0f
|
|---|
| 760 | #define CSR_HPMCOUNTER16 0xc10
|
|---|
| 761 | #define CSR_HPMCOUNTER17 0xc11
|
|---|
| 762 | #define CSR_HPMCOUNTER18 0xc12
|
|---|
| 763 | #define CSR_HPMCOUNTER19 0xc13
|
|---|
| 764 | #define CSR_HPMCOUNTER20 0xc14
|
|---|
| 765 | #define CSR_HPMCOUNTER21 0xc15
|
|---|
| 766 | #define CSR_HPMCOUNTER22 0xc16
|
|---|
| 767 | #define CSR_HPMCOUNTER23 0xc17
|
|---|
| 768 | #define CSR_HPMCOUNTER24 0xc18
|
|---|
| 769 | #define CSR_HPMCOUNTER25 0xc19
|
|---|
| 770 | #define CSR_HPMCOUNTER26 0xc1a
|
|---|
| 771 | #define CSR_HPMCOUNTER27 0xc1b
|
|---|
| 772 | #define CSR_HPMCOUNTER28 0xc1c
|
|---|
| 773 | #define CSR_HPMCOUNTER29 0xc1d
|
|---|
| 774 | #define CSR_HPMCOUNTER30 0xc1e
|
|---|
| 775 | #define CSR_HPMCOUNTER31 0xc1f
|
|---|
| 776 | #define CSR_SSTATUS 0x100
|
|---|
| 777 | #define CSR_SIE 0x104
|
|---|
| 778 | #define CSR_STVEC 0x105
|
|---|
| 779 | #define CSR_SSCRATCH 0x140
|
|---|
| 780 | #define CSR_SEPC 0x141
|
|---|
| 781 | #define CSR_SCAUSE 0x142
|
|---|
| 782 | #define CSR_SBADADDR 0x143
|
|---|
| 783 | #define CSR_SIP 0x144
|
|---|
| 784 | #define CSR_SPTBR 0x180
|
|---|
| 785 | #define CSR_MSTATUS 0x300
|
|---|
| 786 | #define CSR_MISA 0x301
|
|---|
| 787 | #define CSR_MEDELEG 0x302
|
|---|
| 788 | #define CSR_MIDELEG 0x303
|
|---|
| 789 | #define CSR_MIE 0x304
|
|---|
| 790 | #define CSR_MTVEC 0x305
|
|---|
| 791 | #define CSR_MSCRATCH 0x340
|
|---|
| 792 | #define CSR_MEPC 0x341
|
|---|
| 793 | #define CSR_MCAUSE 0x342
|
|---|
| 794 | #define CSR_MBADADDR 0x343
|
|---|
| 795 | #define CSR_MIP 0x344
|
|---|
| 796 | #define CSR_TSELECT 0x7a0
|
|---|
| 797 | #define CSR_TDATA1 0x7a1
|
|---|
| 798 | #define CSR_TDATA2 0x7a2
|
|---|
| 799 | #define CSR_TDATA3 0x7a3
|
|---|
| 800 | #define CSR_DCSR 0x7b0
|
|---|
| 801 | #define CSR_DPC 0x7b1
|
|---|
| 802 | #define CSR_DSCRATCH 0x7b2
|
|---|
| 803 | #define CSR_MCYCLE 0xb00
|
|---|
| 804 | #define CSR_MINSTRET 0xb02
|
|---|
| 805 | #define CSR_MHPMCOUNTER3 0xb03
|
|---|
| 806 | #define CSR_MHPMCOUNTER4 0xb04
|
|---|
| 807 | #define CSR_MHPMCOUNTER5 0xb05
|
|---|
| 808 | #define CSR_MHPMCOUNTER6 0xb06
|
|---|
| 809 | #define CSR_MHPMCOUNTER7 0xb07
|
|---|
| 810 | #define CSR_MHPMCOUNTER8 0xb08
|
|---|
| 811 | #define CSR_MHPMCOUNTER9 0xb09
|
|---|
| 812 | #define CSR_MHPMCOUNTER10 0xb0a
|
|---|
| 813 | #define CSR_MHPMCOUNTER11 0xb0b
|
|---|
| 814 | #define CSR_MHPMCOUNTER12 0xb0c
|
|---|
| 815 | #define CSR_MHPMCOUNTER13 0xb0d
|
|---|
| 816 | #define CSR_MHPMCOUNTER14 0xb0e
|
|---|
| 817 | #define CSR_MHPMCOUNTER15 0xb0f
|
|---|
| 818 | #define CSR_MHPMCOUNTER16 0xb10
|
|---|
| 819 | #define CSR_MHPMCOUNTER17 0xb11
|
|---|
| 820 | #define CSR_MHPMCOUNTER18 0xb12
|
|---|
| 821 | #define CSR_MHPMCOUNTER19 0xb13
|
|---|
| 822 | #define CSR_MHPMCOUNTER20 0xb14
|
|---|
| 823 | #define CSR_MHPMCOUNTER21 0xb15
|
|---|
| 824 | #define CSR_MHPMCOUNTER22 0xb16
|
|---|
| 825 | #define CSR_MHPMCOUNTER23 0xb17
|
|---|
| 826 | #define CSR_MHPMCOUNTER24 0xb18
|
|---|
| 827 | #define CSR_MHPMCOUNTER25 0xb19
|
|---|
| 828 | #define CSR_MHPMCOUNTER26 0xb1a
|
|---|
| 829 | #define CSR_MHPMCOUNTER27 0xb1b
|
|---|
| 830 | #define CSR_MHPMCOUNTER28 0xb1c
|
|---|
| 831 | #define CSR_MHPMCOUNTER29 0xb1d
|
|---|
| 832 | #define CSR_MHPMCOUNTER30 0xb1e
|
|---|
| 833 | #define CSR_MHPMCOUNTER31 0xb1f
|
|---|
| 834 | #define CSR_MUCOUNTEREN 0x320
|
|---|
| 835 | #define CSR_MSCOUNTEREN 0x321
|
|---|
| 836 | #define CSR_MHPMEVENT3 0x323
|
|---|
| 837 | #define CSR_MHPMEVENT4 0x324
|
|---|
| 838 | #define CSR_MHPMEVENT5 0x325
|
|---|
| 839 | #define CSR_MHPMEVENT6 0x326
|
|---|
| 840 | #define CSR_MHPMEVENT7 0x327
|
|---|
| 841 | #define CSR_MHPMEVENT8 0x328
|
|---|
| 842 | #define CSR_MHPMEVENT9 0x329
|
|---|
| 843 | #define CSR_MHPMEVENT10 0x32a
|
|---|
| 844 | #define CSR_MHPMEVENT11 0x32b
|
|---|
| 845 | #define CSR_MHPMEVENT12 0x32c
|
|---|
| 846 | #define CSR_MHPMEVENT13 0x32d
|
|---|
| 847 | #define CSR_MHPMEVENT14 0x32e
|
|---|
| 848 | #define CSR_MHPMEVENT15 0x32f
|
|---|
| 849 | #define CSR_MHPMEVENT16 0x330
|
|---|
| 850 | #define CSR_MHPMEVENT17 0x331
|
|---|
| 851 | #define CSR_MHPMEVENT18 0x332
|
|---|
| 852 | #define CSR_MHPMEVENT19 0x333
|
|---|
| 853 | #define CSR_MHPMEVENT20 0x334
|
|---|
| 854 | #define CSR_MHPMEVENT21 0x335
|
|---|
| 855 | #define CSR_MHPMEVENT22 0x336
|
|---|
| 856 | #define CSR_MHPMEVENT23 0x337
|
|---|
| 857 | #define CSR_MHPMEVENT24 0x338
|
|---|
| 858 | #define CSR_MHPMEVENT25 0x339
|
|---|
| 859 | #define CSR_MHPMEVENT26 0x33a
|
|---|
| 860 | #define CSR_MHPMEVENT27 0x33b
|
|---|
| 861 | #define CSR_MHPMEVENT28 0x33c
|
|---|
| 862 | #define CSR_MHPMEVENT29 0x33d
|
|---|
| 863 | #define CSR_MHPMEVENT30 0x33e
|
|---|
| 864 | #define CSR_MHPMEVENT31 0x33f
|
|---|
| 865 | #define CSR_MVENDORID 0xf11
|
|---|
| 866 | #define CSR_MARCHID 0xf12
|
|---|
| 867 | #define CSR_MIMPID 0xf13
|
|---|
| 868 | #define CSR_MHARTID 0xf14
|
|---|
| 869 | #define CSR_CYCLEH 0xc80
|
|---|
| 870 | #define CSR_TIMEH 0xc81
|
|---|
| 871 | #define CSR_INSTRETH 0xc82
|
|---|
| 872 | #define CSR_HPMCOUNTER3H 0xc83
|
|---|
| 873 | #define CSR_HPMCOUNTER4H 0xc84
|
|---|
| 874 | #define CSR_HPMCOUNTER5H 0xc85
|
|---|
| 875 | #define CSR_HPMCOUNTER6H 0xc86
|
|---|
| 876 | #define CSR_HPMCOUNTER7H 0xc87
|
|---|
| 877 | #define CSR_HPMCOUNTER8H 0xc88
|
|---|
| 878 | #define CSR_HPMCOUNTER9H 0xc89
|
|---|
| 879 | #define CSR_HPMCOUNTER10H 0xc8a
|
|---|
| 880 | #define CSR_HPMCOUNTER11H 0xc8b
|
|---|
| 881 | #define CSR_HPMCOUNTER12H 0xc8c
|
|---|
| 882 | #define CSR_HPMCOUNTER13H 0xc8d
|
|---|
| 883 | #define CSR_HPMCOUNTER14H 0xc8e
|
|---|
| 884 | #define CSR_HPMCOUNTER15H 0xc8f
|
|---|
| 885 | #define CSR_HPMCOUNTER16H 0xc90
|
|---|
| 886 | #define CSR_HPMCOUNTER17H 0xc91
|
|---|
| 887 | #define CSR_HPMCOUNTER18H 0xc92
|
|---|
| 888 | #define CSR_HPMCOUNTER19H 0xc93
|
|---|
| 889 | #define CSR_HPMCOUNTER20H 0xc94
|
|---|
| 890 | #define CSR_HPMCOUNTER21H 0xc95
|
|---|
| 891 | #define CSR_HPMCOUNTER22H 0xc96
|
|---|
| 892 | #define CSR_HPMCOUNTER23H 0xc97
|
|---|
| 893 | #define CSR_HPMCOUNTER24H 0xc98
|
|---|
| 894 | #define CSR_HPMCOUNTER25H 0xc99
|
|---|
| 895 | #define CSR_HPMCOUNTER26H 0xc9a
|
|---|
| 896 | #define CSR_HPMCOUNTER27H 0xc9b
|
|---|
| 897 | #define CSR_HPMCOUNTER28H 0xc9c
|
|---|
| 898 | #define CSR_HPMCOUNTER29H 0xc9d
|
|---|
| 899 | #define CSR_HPMCOUNTER30H 0xc9e
|
|---|
| 900 | #define CSR_HPMCOUNTER31H 0xc9f
|
|---|
| 901 | #define CSR_MCYCLEH 0xb80
|
|---|
| 902 | #define CSR_MINSTRETH 0xb82
|
|---|
| 903 | #define CSR_MHPMCOUNTER3H 0xb83
|
|---|
| 904 | #define CSR_MHPMCOUNTER4H 0xb84
|
|---|
| 905 | #define CSR_MHPMCOUNTER5H 0xb85
|
|---|
| 906 | #define CSR_MHPMCOUNTER6H 0xb86
|
|---|
| 907 | #define CSR_MHPMCOUNTER7H 0xb87
|
|---|
| 908 | #define CSR_MHPMCOUNTER8H 0xb88
|
|---|
| 909 | #define CSR_MHPMCOUNTER9H 0xb89
|
|---|
| 910 | #define CSR_MHPMCOUNTER10H 0xb8a
|
|---|
| 911 | #define CSR_MHPMCOUNTER11H 0xb8b
|
|---|
| 912 | #define CSR_MHPMCOUNTER12H 0xb8c
|
|---|
| 913 | #define CSR_MHPMCOUNTER13H 0xb8d
|
|---|
| 914 | #define CSR_MHPMCOUNTER14H 0xb8e
|
|---|
| 915 | #define CSR_MHPMCOUNTER15H 0xb8f
|
|---|
| 916 | #define CSR_MHPMCOUNTER16H 0xb90
|
|---|
| 917 | #define CSR_MHPMCOUNTER17H 0xb91
|
|---|
| 918 | #define CSR_MHPMCOUNTER18H 0xb92
|
|---|
| 919 | #define CSR_MHPMCOUNTER19H 0xb93
|
|---|
| 920 | #define CSR_MHPMCOUNTER20H 0xb94
|
|---|
| 921 | #define CSR_MHPMCOUNTER21H 0xb95
|
|---|
| 922 | #define CSR_MHPMCOUNTER22H 0xb96
|
|---|
| 923 | #define CSR_MHPMCOUNTER23H 0xb97
|
|---|
| 924 | #define CSR_MHPMCOUNTER24H 0xb98
|
|---|
| 925 | #define CSR_MHPMCOUNTER25H 0xb99
|
|---|
| 926 | #define CSR_MHPMCOUNTER26H 0xb9a
|
|---|
| 927 | #define CSR_MHPMCOUNTER27H 0xb9b
|
|---|
| 928 | #define CSR_MHPMCOUNTER28H 0xb9c
|
|---|
| 929 | #define CSR_MHPMCOUNTER29H 0xb9d
|
|---|
| 930 | #define CSR_MHPMCOUNTER30H 0xb9e
|
|---|
| 931 | #define CSR_MHPMCOUNTER31H 0xb9f
|
|---|
| 932 | #define CAUSE_MISALIGNED_FETCH 0x0
|
|---|
| 933 | #define CAUSE_FAULT_FETCH 0x1
|
|---|
| 934 | #define CAUSE_ILLEGAL_INSTRUCTION 0x2
|
|---|
| 935 | #define CAUSE_BREAKPOINT 0x3
|
|---|
| 936 | #define CAUSE_MISALIGNED_LOAD 0x4
|
|---|
| 937 | #define CAUSE_FAULT_LOAD 0x5
|
|---|
| 938 | #define CAUSE_MISALIGNED_STORE 0x6
|
|---|
| 939 | #define CAUSE_FAULT_STORE 0x7
|
|---|
| 940 | #define CAUSE_USER_ECALL 0x8
|
|---|
| 941 | #define CAUSE_SUPERVISOR_ECALL 0x9
|
|---|
| 942 | #define CAUSE_HYPERVISOR_ECALL 0xa
|
|---|
| 943 | #define CAUSE_MACHINE_ECALL 0xb
|
|---|
| 944 | #endif
|
|---|
| 945 | #if defined(DECLARE_INSN)
|
|---|
| 946 | DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
|
|---|
| 947 | DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
|
|---|
| 948 | DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
|
|---|
| 949 | DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
|
|---|
| 950 | DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
|
|---|
| 951 | DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
|
|---|
| 952 | DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
|
|---|
| 953 | DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
|
|---|
| 954 | DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
|
|---|
| 955 | DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
|
|---|
| 956 | DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
|
|---|
| 957 | DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
|
|---|
| 958 | DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
|
|---|
| 959 | DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
|
|---|
| 960 | DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
|
|---|
| 961 | DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
|
|---|
| 962 | DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
|
|---|
| 963 | DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
|
|---|
| 964 | DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
|
|---|
| 965 | DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
|
|---|
| 966 | DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
|
|---|
| 967 | DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
|
|---|
| 968 | DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
|
|---|
| 969 | DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
|
|---|
| 970 | DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
|
|---|
| 971 | DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
|
|---|
| 972 | DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
|
|---|
| 973 | DECLARE_INSN(or, MATCH_OR, MASK_OR)
|
|---|
| 974 | DECLARE_INSN(and, MATCH_AND, MASK_AND)
|
|---|
| 975 | DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
|
|---|
| 976 | DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
|
|---|
| 977 | DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
|
|---|
| 978 | DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
|
|---|
| 979 | DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
|
|---|
| 980 | DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
|
|---|
| 981 | DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
|
|---|
| 982 | DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
|
|---|
| 983 | DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
|
|---|
| 984 | DECLARE_INSN(lb, MATCH_LB, MASK_LB)
|
|---|
| 985 | DECLARE_INSN(lh, MATCH_LH, MASK_LH)
|
|---|
| 986 | DECLARE_INSN(lw, MATCH_LW, MASK_LW)
|
|---|
| 987 | DECLARE_INSN(ld, MATCH_LD, MASK_LD)
|
|---|
| 988 | DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
|
|---|
| 989 | DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
|
|---|
| 990 | DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
|
|---|
| 991 | DECLARE_INSN(sb, MATCH_SB, MASK_SB)
|
|---|
| 992 | DECLARE_INSN(sh, MATCH_SH, MASK_SH)
|
|---|
| 993 | DECLARE_INSN(sw, MATCH_SW, MASK_SW)
|
|---|
| 994 | DECLARE_INSN(sd, MATCH_SD, MASK_SD)
|
|---|
| 995 | DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
|
|---|
| 996 | DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
|
|---|
| 997 | DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
|
|---|
| 998 | DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
|
|---|
| 999 | DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
|---|
| 1000 | DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
|
|---|
| 1001 | DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
|
|---|
| 1002 | DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
|
|---|
| 1003 | DECLARE_INSN(rem, MATCH_REM, MASK_REM)
|
|---|
| 1004 | DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
|
|---|
| 1005 | DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
|
|---|
| 1006 | DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
|
|---|
| 1007 | DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
|
|---|
| 1008 | DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
|
|---|
| 1009 | DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
|
|---|
| 1010 | DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
|
|---|
| 1011 | DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
|
|---|
| 1012 | DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
|
|---|
| 1013 | DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
|
|---|
| 1014 | DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
|
|---|
| 1015 | DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
|
|---|
| 1016 | DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
|
|---|
| 1017 | DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
|
|---|
| 1018 | DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
|
|---|
| 1019 | DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
|
|---|
| 1020 | DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
|
|---|
| 1021 | DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
|
|---|
| 1022 | DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
|
|---|
| 1023 | DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
|
|---|
| 1024 | DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
|
|---|
| 1025 | DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
|
|---|
| 1026 | DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
|
|---|
| 1027 | DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
|
|---|
| 1028 | DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
|
|---|
| 1029 | DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
|
|---|
| 1030 | DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
|
|---|
| 1031 | DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
|
|---|
| 1032 | DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
|
|---|
| 1033 | DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
|
|---|
| 1034 | DECLARE_INSN(uret, MATCH_URET, MASK_URET)
|
|---|
| 1035 | DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
|
|---|
| 1036 | DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
|
|---|
| 1037 | DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
|
|---|
| 1038 | DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
|
|---|
| 1039 | DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
|
|---|
| 1040 | DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
|
|---|
| 1041 | DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
|
|---|
| 1042 | DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
|
|---|
| 1043 | DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
|
|---|
| 1044 | DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
|
|---|
| 1045 | DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
|
|---|
| 1046 | DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
|
|---|
| 1047 | DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
|
|---|
| 1048 | DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
|
|---|
| 1049 | DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
|
|---|
| 1050 | DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
|
|---|
| 1051 | DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
|
|---|
| 1052 | DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
|
|---|
| 1053 | DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
|
|---|
| 1054 | DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
|
|---|
| 1055 | DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
|
|---|
| 1056 | DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
|
|---|
| 1057 | DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
|
|---|
| 1058 | DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
|
|---|
| 1059 | DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
|
|---|
| 1060 | DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
|
|---|
| 1061 | DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
|
|---|
| 1062 | DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
|
|---|
| 1063 | DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
|
|---|
| 1064 | DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
|
|---|
| 1065 | DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
|
|---|
| 1066 | DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
|
|---|
| 1067 | DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
|
|---|
| 1068 | DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
|
|---|
| 1069 | DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
|
|---|
| 1070 | DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
|
|---|
| 1071 | DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
|---|
| 1072 | DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
|---|
| 1073 | DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
|
|---|
| 1074 | DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
|
|---|
| 1075 | DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
|
|---|
| 1076 | DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
|
|---|
| 1077 | DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
|
|---|
| 1078 | DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
|
|---|
| 1079 | DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
|
|---|
| 1080 | DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
|
|---|
| 1081 | DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
|
|---|
| 1082 | DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
|
|---|
| 1083 | DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
|
|---|
| 1084 | DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
|
|---|
| 1085 | DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
|
|---|
| 1086 | DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
|
|---|
| 1087 | DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
|
|---|
| 1088 | DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
|
|---|
| 1089 | DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
|
|---|
| 1090 | DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
|
|---|
| 1091 | DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
|
|---|
| 1092 | DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
|
|---|
| 1093 | DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
|
|---|
| 1094 | DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
|
|---|
| 1095 | DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
|
|---|
| 1096 | DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
|
|---|
| 1097 | DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
|
|---|
| 1098 | DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
|
|---|
| 1099 | DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
|
|---|
| 1100 | DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
|
|---|
| 1101 | DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
|
|---|
| 1102 | DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
|
|---|
| 1103 | DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
|
|---|
| 1104 | DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
|
|---|
| 1105 | DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
|
|---|
| 1106 | DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
|
|---|
| 1107 | DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
|
|---|
| 1108 | DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
|
|---|
| 1109 | DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
|
|---|
| 1110 | DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
|
|---|
| 1111 | DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
|
|---|
| 1112 | DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
|
|---|
| 1113 | DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
|
|---|
| 1114 | DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
|
|---|
| 1115 | DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
|
|---|
| 1116 | DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
|
|---|
| 1117 | DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
|
|---|
| 1118 | DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
|---|
| 1119 | DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
|
|---|
| 1120 | DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
|
|---|
| 1121 | DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
|
|---|
| 1122 | DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
|
|---|
| 1123 | DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
|
|---|
| 1124 | DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
|
|---|
| 1125 | DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
|
|---|
| 1126 | DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
|
|---|
| 1127 | DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
|
|---|
| 1128 | DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
|
|---|
| 1129 | DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
|
|---|
| 1130 | DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
|
|---|
| 1131 | DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
|
|---|
| 1132 | DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
|
|---|
| 1133 | DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
|
|---|
| 1134 | DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
|
|---|
| 1135 | DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
|
|---|
| 1136 | DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
|
|---|
| 1137 | DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
|
|---|
| 1138 | DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
|
|---|
| 1139 | DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
|
|---|
| 1140 | DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
|
|---|
| 1141 | DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
|
|---|
| 1142 | DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
|
|---|
| 1143 | DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
|
|---|
| 1144 | DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
|---|
| 1145 | DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
|
|---|
| 1146 | DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
|
|---|
| 1147 | DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
|
|---|
| 1148 | DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
|
|---|
| 1149 | DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
|
|---|
| 1150 | DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
|
|---|
| 1151 | DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
|
|---|
| 1152 | DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
|
|---|
| 1153 | DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
|
|---|
| 1154 | DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
|
|---|
| 1155 | DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
|
|---|
| 1156 | DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
|
|---|
| 1157 | DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
|
|---|
| 1158 | DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
|
|---|
| 1159 | DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
|
|---|
| 1160 | DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
|
|---|
| 1161 | DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
|
|---|
| 1162 | DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
|
|---|
| 1163 | DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
|
|---|
| 1164 | DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
|
|---|
| 1165 | DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
|
|---|
| 1166 | DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
|
|---|
| 1167 | DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
|
|---|
| 1168 | DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
|
|---|
| 1169 | DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
|
|---|
| 1170 | DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
|
|---|
| 1171 | DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
|
|---|
| 1172 | DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
|
|---|
| 1173 | DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
|
|---|
| 1174 | DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
|
|---|
| 1175 | #endif
|
|---|
| 1176 | #if defined(DECLARE_CSR)
|
|---|
| 1177 | DECLARE_CSR(fflags, CSR_FFLAGS)
|
|---|
| 1178 | DECLARE_CSR(frm, CSR_FRM)
|
|---|
| 1179 | DECLARE_CSR(fcsr, CSR_FCSR)
|
|---|
| 1180 | DECLARE_CSR(cycle, CSR_CYCLE)
|
|---|
| 1181 | DECLARE_CSR(time, CSR_TIME)
|
|---|
| 1182 | DECLARE_CSR(instret, CSR_INSTRET)
|
|---|
| 1183 | DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
|
|---|
| 1184 | DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
|
|---|
| 1185 | DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
|
|---|
| 1186 | DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
|
|---|
| 1187 | DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
|
|---|
| 1188 | DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
|
|---|
| 1189 | DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
|
|---|
| 1190 | DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
|
|---|
| 1191 | DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
|
|---|
| 1192 | DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
|
|---|
| 1193 | DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
|
|---|
| 1194 | DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
|
|---|
| 1195 | DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
|
|---|
| 1196 | DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
|
|---|
| 1197 | DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
|
|---|
| 1198 | DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
|
|---|
| 1199 | DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
|
|---|
| 1200 | DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
|
|---|
| 1201 | DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
|
|---|
| 1202 | DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
|
|---|
| 1203 | DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
|
|---|
| 1204 | DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
|
|---|
| 1205 | DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
|
|---|
| 1206 | DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
|
|---|
| 1207 | DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
|
|---|
| 1208 | DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
|
|---|
| 1209 | DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
|
|---|
| 1210 | DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
|
|---|
| 1211 | DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
|
|---|
| 1212 | DECLARE_CSR(sstatus, CSR_SSTATUS)
|
|---|
| 1213 | DECLARE_CSR(sie, CSR_SIE)
|
|---|
| 1214 | DECLARE_CSR(stvec, CSR_STVEC)
|
|---|
| 1215 | DECLARE_CSR(sscratch, CSR_SSCRATCH)
|
|---|
| 1216 | DECLARE_CSR(sepc, CSR_SEPC)
|
|---|
| 1217 | DECLARE_CSR(scause, CSR_SCAUSE)
|
|---|
| 1218 | DECLARE_CSR(sbadaddr, CSR_SBADADDR)
|
|---|
| 1219 | DECLARE_CSR(sip, CSR_SIP)
|
|---|
| 1220 | DECLARE_CSR(sptbr, CSR_SPTBR)
|
|---|
| 1221 | DECLARE_CSR(mstatus, CSR_MSTATUS)
|
|---|
| 1222 | DECLARE_CSR(misa, CSR_MISA)
|
|---|
| 1223 | DECLARE_CSR(medeleg, CSR_MEDELEG)
|
|---|
| 1224 | DECLARE_CSR(mideleg, CSR_MIDELEG)
|
|---|
| 1225 | DECLARE_CSR(mie, CSR_MIE)
|
|---|
| 1226 | DECLARE_CSR(mtvec, CSR_MTVEC)
|
|---|
| 1227 | DECLARE_CSR(mscratch, CSR_MSCRATCH)
|
|---|
| 1228 | DECLARE_CSR(mepc, CSR_MEPC)
|
|---|
| 1229 | DECLARE_CSR(mcause, CSR_MCAUSE)
|
|---|
| 1230 | DECLARE_CSR(mbadaddr, CSR_MBADADDR)
|
|---|
| 1231 | DECLARE_CSR(mip, CSR_MIP)
|
|---|
| 1232 | DECLARE_CSR(tselect, CSR_TSELECT)
|
|---|
| 1233 | DECLARE_CSR(tdata1, CSR_TDATA1)
|
|---|
| 1234 | DECLARE_CSR(tdata2, CSR_TDATA2)
|
|---|
| 1235 | DECLARE_CSR(tdata3, CSR_TDATA3)
|
|---|
| 1236 | DECLARE_CSR(dcsr, CSR_DCSR)
|
|---|
| 1237 | DECLARE_CSR(dpc, CSR_DPC)
|
|---|
| 1238 | DECLARE_CSR(dscratch, CSR_DSCRATCH)
|
|---|
| 1239 | DECLARE_CSR(mcycle, CSR_MCYCLE)
|
|---|
| 1240 | DECLARE_CSR(minstret, CSR_MINSTRET)
|
|---|
| 1241 | DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
|
|---|
| 1242 | DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
|
|---|
| 1243 | DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
|
|---|
| 1244 | DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
|
|---|
| 1245 | DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
|
|---|
| 1246 | DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
|
|---|
| 1247 | DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
|
|---|
| 1248 | DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
|
|---|
| 1249 | DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
|
|---|
| 1250 | DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
|
|---|
| 1251 | DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
|
|---|
| 1252 | DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
|
|---|
| 1253 | DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
|
|---|
| 1254 | DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
|
|---|
| 1255 | DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
|
|---|
| 1256 | DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
|
|---|
| 1257 | DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
|
|---|
| 1258 | DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
|
|---|
| 1259 | DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
|
|---|
| 1260 | DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
|
|---|
| 1261 | DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
|
|---|
| 1262 | DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
|
|---|
| 1263 | DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
|
|---|
| 1264 | DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
|
|---|
| 1265 | DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
|
|---|
| 1266 | DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
|
|---|
| 1267 | DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
|
|---|
| 1268 | DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
|
|---|
| 1269 | DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
|
|---|
| 1270 | DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
|
|---|
| 1271 | DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
|
|---|
| 1272 | DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
|
|---|
| 1273 | DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
|
|---|
| 1274 | DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
|
|---|
| 1275 | DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
|
|---|
| 1276 | DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
|
|---|
| 1277 | DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
|
|---|
| 1278 | DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
|
|---|
| 1279 | DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
|
|---|
| 1280 | DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
|
|---|
| 1281 | DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
|
|---|
| 1282 | DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
|
|---|
| 1283 | DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
|
|---|
| 1284 | DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
|
|---|
| 1285 | DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
|
|---|
| 1286 | DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
|
|---|
| 1287 | DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
|
|---|
| 1288 | DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
|
|---|
| 1289 | DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
|
|---|
| 1290 | DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
|
|---|
| 1291 | DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
|
|---|
| 1292 | DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
|
|---|
| 1293 | DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
|
|---|
| 1294 | DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
|
|---|
| 1295 | DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
|
|---|
| 1296 | DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
|
|---|
| 1297 | DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
|
|---|
| 1298 | DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
|
|---|
| 1299 | DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
|
|---|
| 1300 | DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
|
|---|
| 1301 | DECLARE_CSR(mvendorid, CSR_MVENDORID)
|
|---|
| 1302 | DECLARE_CSR(marchid, CSR_MARCHID)
|
|---|
| 1303 | DECLARE_CSR(mimpid, CSR_MIMPID)
|
|---|
| 1304 | DECLARE_CSR(mhartid, CSR_MHARTID)
|
|---|
| 1305 | DECLARE_CSR(cycleh, CSR_CYCLEH)
|
|---|
| 1306 | DECLARE_CSR(timeh, CSR_TIMEH)
|
|---|
| 1307 | DECLARE_CSR(instreth, CSR_INSTRETH)
|
|---|
| 1308 | DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
|
|---|
| 1309 | DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
|
|---|
| 1310 | DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
|
|---|
| 1311 | DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
|
|---|
| 1312 | DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
|
|---|
| 1313 | DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
|
|---|
| 1314 | DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
|
|---|
| 1315 | DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
|
|---|
| 1316 | DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
|
|---|
| 1317 | DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
|
|---|
| 1318 | DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
|
|---|
| 1319 | DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
|
|---|
| 1320 | DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
|
|---|
| 1321 | DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
|
|---|
| 1322 | DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
|
|---|
| 1323 | DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
|
|---|
| 1324 | DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
|
|---|
| 1325 | DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
|
|---|
| 1326 | DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
|
|---|
| 1327 | DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
|
|---|
| 1328 | DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
|
|---|
| 1329 | DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
|
|---|
| 1330 | DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
|
|---|
| 1331 | DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
|
|---|
| 1332 | DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
|
|---|
| 1333 | DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
|
|---|
| 1334 | DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
|
|---|
| 1335 | DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
|
|---|
| 1336 | DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
|
|---|
| 1337 | DECLARE_CSR(mcycleh, CSR_MCYCLEH)
|
|---|
| 1338 | DECLARE_CSR(minstreth, CSR_MINSTRETH)
|
|---|
| 1339 | DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
|
|---|
| 1340 | DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
|
|---|
| 1341 | DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
|
|---|
| 1342 | DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
|
|---|
| 1343 | DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
|
|---|
| 1344 | DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
|
|---|
| 1345 | DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
|
|---|
| 1346 | DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
|
|---|
| 1347 | DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
|
|---|
| 1348 | DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
|
|---|
| 1349 | DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
|
|---|
| 1350 | DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
|
|---|
| 1351 | DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
|
|---|
| 1352 | DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
|
|---|
| 1353 | DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
|
|---|
| 1354 | DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
|
|---|
| 1355 | DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
|
|---|
| 1356 | DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
|
|---|
| 1357 | DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
|
|---|
| 1358 | DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
|
|---|
| 1359 | DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
|
|---|
| 1360 | DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
|
|---|
| 1361 | DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
|
|---|
| 1362 | DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
|
|---|
| 1363 | DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
|
|---|
| 1364 | DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
|
|---|
| 1365 | DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
|
|---|
| 1366 | DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
|
|---|
| 1367 | DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
|
|---|
| 1368 | #endif
|
|---|
| 1369 | #if defined(DECLARE_CAUSE)
|
|---|
| 1370 | DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
|
|---|
| 1371 | DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
|
|---|
| 1372 | DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
|
|---|
| 1373 | DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
|
|---|
| 1374 | DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
|
|---|
| 1375 | DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
|
|---|
| 1376 | DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
|
|---|
| 1377 | DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
|
|---|
| 1378 | DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
|
|---|
| 1379 | DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
|
|---|
| 1380 | DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
|
|---|
| 1381 | DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
|
|---|
| 1382 | #endif
|
|---|
| 1383 |
|
|---|
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