[453] | 1 | /*
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| 2 | * @(#) $Id$
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * K210 LEDデモプログラムのシステムコンフィギュレーションファイル
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| 7 | */
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| 8 | INCLUDE("target_timer.cfg");
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| 9 | INCLUDE("syssvc/syslog.cfg");
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| 10 | INCLUDE("syssvc/banner.cfg");
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| 11 | INCLUDE("syssvc/serial.cfg");
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| 12 | INCLUDE("syssvc/logtask.cfg");
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| 13 | INCLUDE("pdic/k210/device.cfg");
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| 14 | INCLUDE("pdic/k210/dvp.cfg");
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| 15 | INCLUDE("files/storagedevice.cfg");
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| 16 | INCLUDE("files/ff/fatfs.cfg");
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| 17 | INCLUDE("monitor/monitor.cfg");
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| 18 |
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| 19 | #include "itron.h"
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| 20 | #include "device.h"
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| 21 | #include "kpu_main.h"
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| 22 | #include "main.h"
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| 23 |
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| 24 | ATT_INI({ TA_NULL, 0, rtc_init });
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| 25 | ATT_INI({ TA_NULL, 0, rtc_info_init });
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| 26 | ATT_INI({ TA_NULL, heap_param, heap_init });
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| 27 | ATT_INI({ TA_NULL, 0, device_info_init });
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| 28 | ATT_INI({ TA_NULL, 0, at_info_init });
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| 29 |
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| 30 | CRE_DTQ(DTQ_ESP_AT, { TA_NULL, NUM_ESP_AT, NULL });
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| 31 |
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| 32 | CRE_SEM(SPI1TRN_SEM, { TA_TPRI, 0, 1 });
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| 33 | CRE_SEM(SPI1DMATX_SEM, { TA_TPRI, 0, 1 });
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| 34 | CRE_SEM(SPI1LOCK_SEM, { TA_TPRI, 1, 1 });
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| 35 |
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| 36 | CRE_SEM(SPI2TRN_SEM, { TA_TPRI, 0, 1 });
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| 37 | CRE_SEM(SPI2DMATX_SEM, { TA_TPRI, 0, 1 });
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| 38 | CRE_SEM(SPI2LOCK_SEM, { TA_TPRI, 1, 1 });
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| 39 |
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| 40 | CRE_TSK(MAIN_TASK, { TA_ACT, 0, main_task, MAIN_PRIORITY, STACK_SIZE, NULL });
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| 41 | CRE_TSK(KPU_TASK, { TA_ACT, 0, kpu_task, KPU_PRIORITY, KPU_STACK_SIZE, NULL });
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| 42 |
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| 43 | ATT_ISR({TA_NULL, SPI_PORTID, INTNO_SPI, spi_isr, 1 });
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| 44 | CFG_INT(INTNO_SPI, { TA_ENAINT | INTATR_SPI, INTPRI_SPI });
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| 45 | ATT_ISR({TA_NULL, SIPEED_DMA_CH, INTNO_DMATX, channel_dmac_isr, 1 });
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| 46 | CFG_INT(INTNO_DMATX, { TA_ENAINT | INTATR_DMATX, INTPRI_DMATX });
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| 47 |
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| 48 | ATT_ISR({TA_NULL, SPICARD_PORTID, INTNO_SPIC, spi_isr, 1 });
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| 49 | CFG_INT(INTNO_SPIC, { TA_ENAINT | INTATR_SPIC, INTPRI_SPIC });
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| 50 | ATT_ISR({TA_NULL, SPI_DMA1_CH, INTNO_DMARX, channel_dmac_isr, 1 });
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| 51 | CFG_INT(INTNO_DMARX, { TA_ENAINT | INTATR_DMARX, INTPRI_DMARX });
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| 52 |
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| 53 | ATT_ISR({TA_NULL, 0, INTNO_AI, ai_done_isr, 1 });
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| 54 | CFG_INT(INTNO_AI, { TA_ENAINT | INTATR_AI, INTPRI_AI });
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| 55 | ATT_ISR({TA_NULL, AI_DMA_CH, INTNO_DMAAI, channel_dmac_isr, 1 });
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| 56 | CFG_INT(INTNO_DMAAI, { TA_ENAINT | INTATR_DMAAI, INTPRI_DMAAI });
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