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2 | /* Copyright 2018 Canaan Inc.
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3 | *
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4 | * Licensed under the Apache License, Version 2.0 (the "License");
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5 | * you may not use this file except in compliance with the License.
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6 | * You may obtain a copy of the License at
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7 | *
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8 | * http://www.apache.org/licenses/LICENSE-2.0
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9 | *
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10 | * Unless required by applicable law or agreed to in writing, software
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11 | * distributed under the License is distributed on an "AS IS" BASIS,
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12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | * See the License for the specific language governing permissions and
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14 | * limitations under the License.
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15 | */
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16 | #ifndef _BSP_ATOMIC_H
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17 | #define _BSP_ATOMIC_H
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18 |
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19 | #ifdef __cplusplus
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20 | extern "C" {
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21 | #endif
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22 |
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23 | #define SPINLOCK_INIT \
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24 | { \
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25 | 0 \
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26 | }
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27 |
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28 | #define CORELOCK_INIT \
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29 | { \
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30 | .lock = SPINLOCK_INIT, \
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31 | .count = 0, \
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32 | .core = -1 \
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33 | }
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34 |
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35 | /* Defination of memory barrier macro */
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36 | #define mb() \
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37 | { \
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38 | asm volatile("fence" :: \
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39 | : "memory"); \
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40 | }
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41 |
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42 | #define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
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43 | #define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
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44 |
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45 | #ifndef __riscv_atomic
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46 | #error "atomic extension is required."
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47 | #endif
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48 | #define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
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49 | #define atomic_or(ptr, inc) __sync_fetch_and_or(ptr, inc)
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50 | #define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
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51 | #define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)
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52 |
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53 | typedef struct _spinlock
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54 | {
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55 | int lock;
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56 | } spinlock_t;
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57 |
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58 | typedef struct _semaphore
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59 | {
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60 | spinlock_t lock;
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61 | int count;
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62 | int waiting;
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63 | } semaphore_t;
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64 |
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65 | typedef struct _corelock
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66 | {
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67 | spinlock_t lock;
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68 | int count;
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69 | int core;
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70 | } corelock_t;
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71 |
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72 | static inline int spinlock_trylock(spinlock_t *lock)
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73 | {
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74 | int res = atomic_swap(&lock->lock, -1);
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75 | /* Use memory barrier to keep coherency */
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76 | mb();
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77 | return res;
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78 | }
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79 |
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80 | static inline void spinlock_lock(spinlock_t *lock)
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81 | {
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82 | while(spinlock_trylock(lock))
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83 | ;
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84 | }
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85 |
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86 | static inline void spinlock_unlock(spinlock_t *lock)
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87 | {
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88 | /* Use memory barrier to keep coherency */
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89 | mb();
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90 | atomic_set(&lock->lock, 0);
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91 | asm volatile("nop");
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92 | }
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93 |
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94 | static inline void semaphore_signal(semaphore_t *semaphore, int i)
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95 | {
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96 | spinlock_lock(&(semaphore->lock));
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97 | semaphore->count += i;
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98 | spinlock_unlock(&(semaphore->lock));
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99 | }
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100 |
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101 | static inline void semaphore_wait(semaphore_t *semaphore, int i)
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102 | {
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103 | atomic_add(&(semaphore->waiting), 1);
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104 | while(1)
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105 | {
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106 | spinlock_lock(&(semaphore->lock));
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107 | if(semaphore->count >= i)
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108 | {
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109 | semaphore->count -= i;
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110 | atomic_add(&(semaphore->waiting), -1);
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111 | spinlock_unlock(&(semaphore->lock));
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112 | break;
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113 | }
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114 | spinlock_unlock(&(semaphore->lock));
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115 | }
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116 | }
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117 |
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118 | static inline int semaphore_count(semaphore_t *semaphore)
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119 | {
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120 | int res = 0;
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121 |
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122 | spinlock_lock(&(semaphore->lock));
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123 | res = semaphore->count;
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124 | spinlock_unlock(&(semaphore->lock));
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125 | return res;
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126 | }
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127 |
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128 | static inline int semaphore_waiting(semaphore_t *semaphore)
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129 | {
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130 | return atomic_read(&(semaphore->waiting));
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131 | }
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132 |
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133 | static inline int corelock_trylock(corelock_t *lock)
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134 | {
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135 | int res = 0;
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136 | unsigned long core;
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137 |
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138 | asm volatile("csrr %0, mhartid;"
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139 | : "=r"(core));
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140 | if(spinlock_trylock(&lock->lock))
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141 | {
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142 | return -1;
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143 | }
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144 |
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145 | if(lock->count == 0)
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146 | {
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147 | /* First time get lock */
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148 | lock->count++;
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149 | lock->core = core;
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150 | res = 0;
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151 | } else if(lock->core == core)
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152 | {
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153 | /* Same core get lock */
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154 | lock->count++;
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155 | res = 0;
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156 | } else
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157 | {
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158 | /* Different core get lock */
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159 | res = -1;
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160 | }
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161 | spinlock_unlock(&lock->lock);
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162 |
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163 | return res;
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164 | }
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165 |
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166 | static inline void corelock_lock(corelock_t *lock)
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167 | {
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168 | unsigned long core;
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169 |
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170 | asm volatile("csrr %0, mhartid;"
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171 | : "=r"(core));
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172 | spinlock_lock(&lock->lock);
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173 |
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174 | if(lock->count == 0)
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175 | {
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176 | /* First time get lock */
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177 | lock->count++;
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178 | lock->core = core;
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179 | } else if(lock->core == core)
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180 | {
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181 | /* Same core get lock */
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182 | lock->count++;
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183 | } else
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184 | {
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185 | /* Different core get lock */
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186 | spinlock_unlock(&lock->lock);
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187 |
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188 | do
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189 | {
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190 | while(atomic_read(&lock->count))
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191 | ;
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192 | } while(corelock_trylock(lock));
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193 | return;
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194 | }
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195 | spinlock_unlock(&lock->lock);
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196 | }
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197 |
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198 | static inline void corelock_unlock(corelock_t *lock)
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199 | {
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200 | unsigned long core;
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201 |
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202 | asm volatile("csrr %0, mhartid;"
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203 | : "=r"(core));
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204 | spinlock_lock(&lock->lock);
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205 |
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206 | if(lock->core == core)
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207 | {
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208 | /* Same core release lock */
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209 | lock->count--;
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210 | if(lock->count <= 0)
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211 | {
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212 | lock->core = -1;
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213 | lock->count = 0;
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214 | }
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215 | } else
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216 | {
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217 | /* Different core release lock */
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218 | spinlock_unlock(&lock->lock);
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219 |
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220 | register unsigned long a7 asm("a7") = 93;
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221 | register unsigned long a0 asm("a0") = 0;
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222 | register unsigned long a1 asm("a1") = 0;
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223 | register unsigned long a2 asm("a2") = 0;
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224 |
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225 | asm volatile("scall"
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226 | : "+r"(a0)
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227 | : "r"(a1), "r"(a2), "r"(a7));
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228 | }
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229 | spinlock_unlock(&lock->lock);
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230 | }
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231 |
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232 | #ifdef __cplusplus
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233 | }
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234 | #endif
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235 |
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236 | #endif /* _BSP_ATOMIC_H */
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